1 files changed, 106 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h
new file mode 100644
index 0000000000..612b166010
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+++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h
@@ -0,0 +1,106 @@
+/** @file
+  This file contains define definitions specific to processor
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _POWER_MGMT_DEFINITIONS_H_
+#define _POWER_MGMT_DEFINITIONS_H_
+
+#define CSTATE_SUPPORTED          0x1
+#define ENHANCED_CSTATE_SUPPORTED 0x2
+#define C6_C7_SHORT_LATENCY_SUPPORTED 0x01
+#define C6_C7_LONG_LATENCY_SUPPORTED  0x02
+#define C7s_SHORT_LATENCY_SUPPORTED   0x03
+#define C7s_LONG_LATENCY_SUPPORTED    0x04
+//
+// Voltage offset definitions
+//
+#define OC_LIB_OFFSET_ADAPTIVE  0
+#define OC_LIB_OFFSET_OVERRIDE  1
+//
+// Platform Power Management Flags Bit Definitions:
+//   These defines are also used in CPU0CST.ASL to check platform configuration
+//   and build C-state table accordingly.
+//
+#define PPM_EIST                BIT0   ///< Enhanced Intel Speed Step Technology.
+#define PPM_C1                  BIT1   ///< C1 enabled, supported.
+#define PPM_C1E                 BIT2   ///< C1E enabled.
+#define PPM_C3                  BIT3   ///< C3 enabled, supported.
+#define PPM_C6                  BIT4   ///< C6 enabled, supported.
+#define PPM_C7                  BIT5   ///< C7 enabled, supported.
+#define PPM_C7S                 BIT6   ///< C7S enabled, supported
+#define PPM_TM                  BIT7   ///< Adaptive Thermal Monitor.
+#define PPM_TURBO               BIT8   ///< Long duration turbo mode
+#define PPM_CMP                 BIT9   ///< CMP.
+#define PPM_TSTATES             BIT10  ///< CPU throttling states
+#define PPM_MWAIT_EXT           BIT11  ///< MONITIOR/MWAIT Extensions supported.
+#define PPM_EEPST               BIT12  ///< Energy efficient P-State Feature enabled
+#define PPM_TSTATE_FINE_GRAINED BIT13  ///< Fine grained CPU Throttling states
+#define PPM_CD                  BIT14  ///< Deep Cstate - C8/C9/C10
+#define PPM_TIMED_MWAIT         BIT15  ///< Timed Mwait support
+#define C6_LONG_LATENCY_ENABLE  BIT16  ///< 1=C6 Long and Short,0=C6 Short only
+#define C7_LONG_LATENCY_ENABLE  BIT17  ///< 1=C7 Long and Short,0=C7 Short only
+#define C7s_LONG_LATENCY_ENABLE BIT18  ///< 1=C7s Long and Short,0=C7s Short only
+#define PPM_C8                  BIT19  ///< 1= C8 enabled/supported
+#define PPM_C9                  BIT20  ///< 1= C9 enabled/supported
+#define PPM_C10                 BIT21  ///< 1= C10 enabled/supported
+#define PPM_HWP                 BIT22  ///< 1= HWP enabled/supported
+#define PPM_HWP_LVT             BIT23  ///< 1= HWP LVT enabled/supported
+#define PPM_OC_UNLOCKED         BIT24  ///< 1= Overclocking fully unlocked
+
+#define PPM_C_STATES            0x7A    ///< PPM_C1 + PPM_C3 + PPM_C6 + PPM_C7 + PPM_C7S
+#define C3_LATENCY              0x4E
+#define C6_C7_SHORT_LATENCY     0x76
+#define C6_C7_LONG_LATENCY      0x94
+#define C8_LATENCY              0xFA
+#define C9_LATENCY              0x14C
+#define C10_LATENCY             0x3F2
+
+//
+// The following definitions are based on assumed location for the  ACPI
+// Base Address.  Modify as necessary base on platform-specific requirements.
+//
+#define PCH_ACPI_PBLK 0x1810
+#define PCH_ACPI_LV2  0x1814
+#define PCH_ACPI_LV3  0x1815
+#define PCH_ACPI_LV4  0x1816
+#define PCH_ACPI_LV6  0x1818
+#define PCH_ACPI_LV5  0x1817
+#define PCH_ACPI_LV7  0x1819
+
+//
+// C-State Latency (us) and Power (mW) for C1
+//
+#define C1_LATENCY                        1
+#define C1_POWER                          0x3E8
+#define C3_POWER                          0x1F4
+#define C6_POWER                          0x15E
+#define C7_POWER                          0xC8
+#define C8_POWER                          0xC8
+#define C9_POWER                          0xC8
+#define C10_POWER                         0xC8
+
+
+#define PID_DOMAIN_KP                     0
+#define PID_DOMAIN_KI                     1
+#define PID_DOMAIN_KD                     2
+#define MAILBOX_PARAM_1_OFFSET            8
+
+///
+///  VR Domain Definitions
+///
+#define SKL_VR_DOMAIN_SA           0x0
+#define SKL_VR_DOMAIN_IA           0x1
+#define SKL_VR_DOMAIN_GTUS         0x2
+#define SKL_VR_DOMAIN_GTS          0x3
+
+#endif