diff options
Diffstat (limited to 'Silicon/Intel/KabylakeSiliconPkg/Cpu')
41 files changed, 5311 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h new file mode 100644 index 0000000000..863a4fcdf8 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h @@ -0,0 +1,101 @@ +/** @file
+ CPU Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_CONFIG_H_
+#define _CPU_CONFIG_H_
+
+#include <ConfigBlock/CpuConfigFspData.h>
+#define CPU_CONFIG_REVISION 3
+
+
+extern EFI_GUID gCpuConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Configuration Structure.
+ This structure is identical to CPU_CONFIG_FSP.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Add SkipMpInit : Silicon Initialization will skip MP Initialization for FSP only
+ <b>Revision 3</b>:
+ - Deprecated and moved FclkFrequency, VmxEnable to CPU_CONFIG_LIB_PREMEM_CONFIG
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Enable or Disable Advanced Encryption Standard (AES) feature.
+ For some countries, this should be disabled for legal reasons.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 AesEnable : 1;
+ /**
+ @deprecated since revision 3. Moved to CPU_CONFIG_LIB_PREMEM_CONFIG
+ Processor Early Power On Configuration FCLK setting.
+ - <b>0: 800 MHz (ULT/ULX)</b>.
+ - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
+ - 2: 400 MHz.
+ - 3: Reserved.
+ **/
+ UINT32 FClkFrequency : 2;
+ UINT32 EnableRsr : 1; ///< Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
+ /**
+ Policies to obtain CPU temperature.
+ - <b>0: ACPI thermal management uses EC reported temperature values</b>.
+ - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values.
+ - 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition.
+ **/
+ UINT32 EnableDts : 2;
+ UINT32 SmmbaseSwSmiNumber : 8; ///< Software SMI number for handler to save CPU information in SMRAM.
+ /**
+ @deprecated since revision 3. Moved to CPU_CONFIG_LIB_PREMEM_CONFIG
+ Enable or Disable Virtual Machine Extensions (VMX) feature.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 VmxEnable : 1;
+ /**
+ Enable or Disable Trusted Execution Technology (TXT) feature.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 TxtEnable : 1;
+ UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
+ UINT32 RsvdBits : 15; ///< Reserved for future use
+ EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor.
+} CPU_CONFIG;
+
+/**
+ FSP CPU Configuration Structure.
+ This structure is identical to CPU_CONFIG.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 Data; ///< Config Block Data
+ EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcode patch that is suitable for this processor.
+} CPU_CONFIG_FSP;
+
+typedef union {
+ CPU_CONFIG CpuConfig;
+ CPU_CONFIG_FSP CpuConfigFsp;
+} CPU_CONFIG_UNION;
+
+#pragma pack (pop)
+
+#endif // _CPU_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigFspData.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigFspData.h new file mode 100644 index 0000000000..8f333cffeb --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigFspData.h @@ -0,0 +1,65 @@ +/** @file
+ FSP CPU Data Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_CONFIG_FSP_DATA_H_
+#define _CPU_CONFIG_FSP_DATA_H_
+
+#pragma pack (push,1)
+typedef union {
+ struct {
+ /**
+ Enable or Disable Advanced Encryption Standard (AES) feature.
+ For some countries, this should be disabled for legal reasons.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 AesEnable : 1;
+ /**
+ Processor Early Power On Configuration FCLK setting.
+ - <b>0: 800 MHz (ULT/ULX)</b>.
+ - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
+ - 2: 400 MHz.
+ - 3: Reserved.
+ **/
+ UINT32 FClkFrequency : 2;
+ UINT32 EnableRsr : 1; ///< Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
+ /**
+ Policies to obtain CPU temperature.
+ - <b>0: ACPI thermal management uses EC reported temperature values</b>.
+ - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values.
+ - 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition.
+ **/
+ UINT32 EnableDts : 2;
+ UINT32 SmmbaseSwSmiNumber : 8; ///< Software SMI number for handler to save CPU information in SMRAM.
+ /**
+ Enable or Disable Virtual Machine Extensions (VMX) feature.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 VmxEnable : 1;
+ /**
+ Enable or Disable Trusted Execution Technology (TXT) feature.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 TxtEnable : 1;
+ UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
+ UINT32 RsvdBits : 15; ///< Reserved for future use
+ UINT32 Reserved;
+ } Bits;
+ UINT32 Uint32[2];
+ } CPU_CONFIG_FSP_DATA;
+
+#pragma pack (pop)
+
+#endif // _CPU_CONFIG_FSP_DATA_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h new file mode 100644 index 0000000000..19e41287ce --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreMemConfig.h @@ -0,0 +1,101 @@ +/** @file
+ CPU PreMemory Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
+
+#define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 2
+
+extern EFI_GUID gCpuConfigLibPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Config Library PreMemory Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+
+ <b>Revision 2</b>:
+ - Added PeciC10Reset.
+ - Added PeciSxReset.
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 HyperThreading : 1; ///< Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>.
+ /**
+ Enable or disable override of default max non-turbo ratio. If enabled, BIOS will take the value specified in
+ CpuRatio policy and updates the max non-turbo ratio. See policy CpuRatio for more details.
+ If disabled, BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting.
+ - <b>0: Disable</b>
+ - 1: Enable
+ **/
+ UINT32 CpuRatioOverride : 1;
+ /**
+ Sets the boot frequency starting from reset vector.
+ - 0: Maximum battery performance.
+ - <b>1: Maximum non-turbo performance</b>.
+ - 2: Turbo performance.
+ @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
+ **/
+ UINT32 BootFrequency : 2;
+ /**
+ Number of processor cores to enable.
+ - <b> 0: All cores</b>
+ - 1: 1 core
+ - 2: 2 cores
+ - 3: 3 cores
+ **/
+ UINT32 ActiveCoreCount : 3;
+ /**
+ Processor Early Power On Configuration FCLK setting.
+ - <b>0: 800 MHz (ULT/ULX)</b>.
+ - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
+ - 2: 400 MHz.
+ - 3: Reserved.
+ **/
+ UINT32 FClkFrequency : 2;
+ UINT32 JtagC10PowerGateDisable : 1; ///< Power JTAG in C10 and deeper power states; <b>0: Disable</b>; 1: Enable.
+ UINT32 BistOnReset : 1; ///< <b>(Test)</b> Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
+ /**
+ Enable or Disable Virtual Machine Extensions (VMX) feature.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 VmxEnable : 1;
+ /**
+ Enables a mailbox command to resolve rare PECI related Sx issues.
+ @note This should only be used on systems that observe PECI Sx issues.
+ - <b>0: Disable</b>
+ - 1: Enable
+ **/
+ UINT32 PeciSxReset : 1;
+ /**
+ Enables a mailbox command to resolve rare PECI related C10 issues.
+ @note This should only be used on systems that observe PECI C10 issues.
+ - <b>0: Disable</b>
+ - 1: Enable
+ **/
+ UINT32 PeciC10Reset : 1;
+ UINT32 RsvdBits : 18;
+ /**
+ CpuRatio - When CpuRatioOverride is enabled, max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio.
+ **/
+ UINT8 CpuRatio;
+ UINT8 Reserved[3]; ///< Reserved for alignment
+} CPU_CONFIG_LIB_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclockingConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclockingConfig.h new file mode 100644 index 0000000000..735e79c491 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclockingConfig.h @@ -0,0 +1,151 @@ +/** @file
+ CPU Overclocking Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_OVERCLOCKING_PREMEM_CONFIG_H_
+#define _CPU_OVERCLOCKING_PREMEM_CONFIG_H_
+
+#define CPU_OVERCLOCKING_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gCpuOverclockingPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Overclocking Premem Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Overclocking support. This controls whether OC mailbox transactions are sent.
+ If disabled, all policies in this config block besides OcSupport and OcLock will be ignored.
+ <b>0: Disable</b>;
+ 1: Enable.
+ @note If PcdOverclockEnable is disabled, this should also be disabled.
+ **/
+ UINT32 OcSupport : 1;
+ UINT32 OcLock : 1; ///< If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration settings.; <b>0: Disable</b>; 1: Enable (Lock).
+ /**
+ Core voltage mode, specifies which voltage mode the processor will be operating.
+ <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
+ 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
+ **/
+ UINT32 CoreVoltageMode : 1;
+ UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
+ UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
+ UINT32 Avx3RatioOffset : 5; ///< AVX3 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX3 ratio to maximize possible ratio for SSE workload.
+ UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Voltage enable/disable. <b>0: Disabled</b>, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
+ /**
+ Ring Downbin enable/disable.
+ When enabled, the CPU will force the ring ratio to be lower than the core ratio.
+ Disabling will allow the ring and core ratios to run at the same frequency.
+ Uses OC Mailbox command 0x19.
+ <b>0: Disables Ring Downbin feature</b>. 1: Enables Ring downbin feature.
+ **/
+ UINT32 RingDownBin : 1;
+ UINT32 RsvdBits : 11; ///< Reserved for future use
+ /**
+ Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).
+ <b>0. no override/HW defaults.</b>. Range 0-83.
+ **/
+ UINT16 CoreMaxOcRatio;
+ /**
+ The core voltage override which is applied to the entire range of cpu core frequencies.
+ Used when CoreVoltageMode = Override.
+ <b>0. no override</b>. Range 0-2000 mV.
+ **/
+ UINT16 CoreVoltageOverride;
+ /**
+ Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range.
+ Used when CoreVoltageMode = Adaptive.
+ <b>0. no override</b>. Range 0-2000mV.
+ **/
+ UINT16 CoreVoltageAdaptive;
+ /**
+ The core voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
+ This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
+ **/
+ INT16 CoreVoltageOffset;
+ UINT8 RingMaxOcRatio; ///< Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83.
+ UINT8 RingMinOcRatio; ///< Minimum ring ratio override. <b>0: Hardware defaults.</b> Range: 0-83.
+ UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
+ UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
+ UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
+ UINT32 McPllVoltageOffset : 6; ///< Memory Controller PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 17.5mv units.
+ UINT32 RsvdBits1 : 8;
+ UINT8 Rsvd[2]; ///< Reserved for future use & Config block alignment
+} CPU_OVERCLOCKING_PREMEM_CONFIG;
+
+/**
+ @deprecated CPU_OVERCLOCKING_CONFIG since revision 2.
+ This structure is not used, use CPU_OVERCLOCKING_PREMEM_CONFIG instead
+
+ CPU Overclocking Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+
+ <b>Revision 2</b>:
+ - Deprecated CPU_OVERCLOCKING_CONFIG
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 OcSupport : 1; ///< @deprecated since revision 2. Overclocking support. This controls whether OC mailbox transactions are sent. <b>0: Disable</b>; 1: Enable.
+ UINT32 OcLock : 1; ///< @deprecated since revision 2. If enabled, sets OC lock bit in MSR 0x194[20], locking the OC mailbox and other OC configuration settings.; <b>0: Disable</b>; 1: Enable (Lock).
+ /**
+ Core voltage mode, specifies which voltage mode the processor will be operating.
+ <b>0: Adaptive Mode</b> allows the processor to interpolate a voltage curve when beyond fused P0 range;
+ 1: Override, sets one voltage for for the entire frequency range, Pn-P0.
+ **/
+ UINT32 CoreVoltageMode : 1;
+ UINT32 CorePllVoltageOffset : 6; ///< @deprecated since revision 2. Core PLL voltage offset. <b>0: No offset</b>. Range 0-63 in 15mv units.
+ UINT32 Avx2RatioOffset : 5; ///< @deprecated since revision 2. AVX2 Ratio Offset. <b>0: No offset</b>. Range is 0-31. Used to lower the AVX ratio to maximize possible ratio for SSE workload.
+ UINT32 BclkAdaptiveVoltage : 1; ///< @deprecated since revision 2. Bclk Adaptive Voltage enable/disable. <b>0: Disabled</b>, 1: Enabled. When enabled, the CPU V/F curves are aware of BCLK frequency when calculated.
+ UINT32 RsvdBits : 17; ///< Reserved for future use
+ /**
+ @deprecated since revision 2.
+ Maximum core turbo ratio override allows to increase CPU core frequency beyond the fused max turbo ratio limit (P0).
+ <b>0. no override/HW defaults.</b>. Range 0-83.
+ **/
+ UINT16 CoreMaxOcRatio;
+ /**
+ @deprecated since revision 2.
+ The core voltage override which is applied to the entire range of cpu core frequencies.
+ Used when CoreVoltageMode = Override.
+ <b>0. no override</b>. Range 0-2000 mV.
+ **/
+ UINT16 CoreVoltageOverride;
+ /**
+ @deprecated since revision 2.
+ Adaptive Turbo voltage target used to define the interpolation voltage point when the cpu is operating in turbo mode range.
+ Used when CoreVoltageMode = Adaptive.
+ <b>0. no override</b>. Range 0-2000mV.
+ **/
+ UINT16 CoreVoltageAdaptive;
+ /**
+ @deprecated since revision 2.
+ The core voltage offset applied on top of all other voltage modes. This offset is applied over the entire frequency range.
+ This is a 2's complement number in mV units. <b>Default: 0</b> Range: -1000 to 1000.
+ **/
+ INT16 CoreVoltageOffset;
+ UINT8 RingMaxOcRatio; ///< @deprecated since revision 2. Maximum ring ratio override allows to increase CPU ring frequency beyond the fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83.
+ UINT8 RingMinOcRatio; ///< @deprecated since revision 2. Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-83.
+ UINT8 Rsvd[2]; ///< Reserved for future use & Config block alignment
+} CPU_OVERCLOCKING_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_OVERCLOCKING_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.h new file mode 100644 index 0000000000..d8b5a2ed98 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig.h @@ -0,0 +1,59 @@ +/** @file
+ CPU PID Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_PID_TEST_CONFIG_H_
+#define _CPU_PID_TEST_CONFIG_H_
+
+#define CPU_PID_TEST_CONFIG_REVISION 1
+
+extern EFI_GUID gCpuPidTestConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ PID Tuning Configuration Structure.
+ Domain is mapped to Kp = 0, Ki = 1, Kd = 2.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT16 Ratl[3]; ///< RATL setting, in 1/256 units. Range is 0 - 65280
+ UINT16 VrTdcVr0[3]; ///< VR Thermal Design Current for VR0. In 1/256 units. Range is 0 - 65280
+ UINT16 VrTdcVr1[3]; ///< VR Thermal Design Current for VR1. In 1/256 units. Range is 0 - 65280
+ UINT16 VrTdcVr2[3]; ///< VR Thermal Design Current for VR2. In 1/256 units. Range is 0 - 65280
+ UINT16 VrTdcVr3[3]; ///< VR Thermal Design Current for VR3. In 1/256 units. Range is 0 - 65280
+ UINT16 PbmPsysPl1Msr[3]; ///< Power Budget Management Psys PL1 MSR. In 1/256 units. Range is 0 - 65280
+ UINT16 PbmPsysPl1MmioPcs[3]; ///< Power Budget Management Psys PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280
+ UINT16 PbmPsysPl2Msr[3]; ///< Power Budget Management Psys PL2 MSR. In 1/256 units. Range is 0 - 65280
+ UINT16 PbmPsysPl2MmioPcs[3]; ///< Power Budget Management Psys PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280
+ UINT16 PbmPkgPl1Msr[3]; ///< Power Budget Management Package PL1 MSR. In 1/256 units. Range is 0 - 65280
+ UINT16 PbmPkgPl1MmioPcs[3]; ///< Power Budget Management Package PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280
+ UINT16 PbmPkgPl2Msr[3]; ///< Power Budget Management Package PL2 MSR. In 1/256 units. Range is 0 - 65280
+ UINT16 PbmPkgPl2MmioPcs[3]; ///< Power Budget Management Package PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280
+ UINT16 DdrPl1Msr[3]; ///< DDR PL1 MSR. In 1/256 units. Range is 0 - 65280
+ UINT16 DdrPl1MmioPcs[3]; ///< DDR PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280
+ UINT16 DdrPl2Msr[3]; ///< DDR PL2 MSR. In 1/256 units. Range is 0 - 65280
+ UINT16 DdrPl2MmioPcs[3]; ///< DDR PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280
+ /**
+ Enable or Disable PID Tuning programming flow.
+ If disabled, all other policies in this config block are ignored.
+ **/
+ UINT8 PidTuning;
+ UINT8 Rsvd; ///< Reserved for DWORD alignment.
+} CPU_PID_TEST_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_PID_TEST_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasicConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasicConfig.h new file mode 100644 index 0000000000..68dc9195ae --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasicConfig.h @@ -0,0 +1,178 @@ +/** @file
+ CPU Power Management Basic Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_POWER_MGMT_BASIC_CONFIG_H_
+#define _CPU_POWER_MGMT_BASIC_CONFIG_H_
+
+#define CPU_POWER_MGMT_BASIC_CONFIG_REVISION 2
+
+extern EFI_GUID gCpuPowerMgmtBasicConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Power Management Basic Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Deprecated S3RestoreMsrSwSmiNumber.
+ Replace SW SMI number to restore the power mgmt MSRs with CpuPowerMgmtLib during S3 resume.
+ <b>Revision 3</b>:
+ - Added FiveCoreRatioLimit, SixCoreRatioLimit, SevenCoreRatioLimit, EightCoreRatioLimit for 6 and 8 core support.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Sets the boot frequency starting from reset vector.
+ - 0: Maximum battery performance.
+ - <b>1: Maximum non-turbo performance</b>.
+ - 2: Turbo performance.
+ @note If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
+ **/
+ UINT32 BootFrequency : 2;
+ UINT32 SkipSetBootPState : 1; ///< Choose whether to skip SetBootPState function for all APs; <b>0: Do not skip</b>; 1: Skip.
+ /**
+ Enable or Disable Intel Speed Shift Technology.
+ Enabling allows for processor control of P-state transitions.
+ 0: Disable; <b>1: Enable;</b> Bit 1 is ignored.
+ @note Currently this feature is recommended to be enabled only on win10
+ **/
+ UINT32 Hwp : 2;
+ /**
+ Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
+ HDC enables the processor to autonomously force components to enter into an idle state to lower effective frequency.
+ This allows for increased package level C6 residency.
+ @note Currently this feature is recommended to be enabled only on win10
+ **/
+ UINT32 HdcControl : 2;
+ UINT32 PowerLimit2 : 1; ///< Enable or Disable short duration Power Limit (PL2). 0: Disable; <b>1: Enable</b>
+ UINT32 TurboPowerLimitLock : 1; ///< MSR 0x610[63] and 0x618[63]: Locks all Turbo power limit settings to read-only; <b>0: Disable</b>; 1: Enable (Lock).
+ UINT32 PowerLimit3DutyCycle : 8; ///< Package PL3 Duty Cycle. Specifies the PL3 duty cycle percentage, Range 0-100. <b>Default: 0</b>.
+ UINT32 PowerLimit3Lock : 1; ///< Package PL3 MSR 615h lock; <b>0: Disable</b>; 1: Enable (Lock).
+ UINT32 PowerLimit4Lock : 1; ///< Package PL4 MSR 601h lock; <b>0: Disable</b>; 1: Enable (Lock).
+ /**
+ Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.
+ For Y SKU, the recommended default for this policy is <b>1: Enabled</b>, which indicates throttling below P1 is allowed.
+ For all other SKUs the recommended default are <b>0: Disabled</b>.
+ **/
+ UINT32 TccOffsetClamp : 1;
+ UINT32 TccOffsetLock : 1; ///< Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A2h; <b>0: Disabled</b>; 1: Enabled (Lock).
+ UINT32 TurboMode : 1; ///< Enable or Disable Turbo Mode. Disable; <b>1: Enable</b>
+ UINT32 RsvdBits : 10; ///< Reserved for future use.
+ /**
+ 1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. For overclocking parts: LFM to Fused 1-Core Ratio Limit + OC Bins.
+ Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
+ - This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.
+ **/
+ UINT8 OneCoreRatioLimit;
+ /**
+ 2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking part: LFM to Fused 2-Core Ratio Limit + OC Bins.
+ Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
+ - This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ **/
+ UINT8 TwoCoreRatioLimit;
+ /**
+ 3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking part: LFM to Fused 3-Core Ratio Limit + OC Bins.
+ Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
+ - This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ **/
+ UINT8 ThreeCoreRatioLimit;
+ /**
+ 4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking part: LFM to Fused 4-Core Ratio Limit + OC Bins.
+ Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
+ - This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ **/
+ UINT8 FourCoreRatioLimit;
+ UINT8 S3RestoreMsrSwSmiNumber; ///< @deprecated SW SMI number to restore the power mgmt MSRs during S3 resume. Deprecated since revision 2
+ /**
+ TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated.
+ TCC will be activated at (TCC Activation Temperature - TCC Activation Offset), in degrees Celcius.
+ For Y SKU, the recommended default for this policy is <b>10</b>
+ For all other SKUs the recommended default are <b>0</b>, causing TCC to activate at TCC Activation temperature.
+ @note The policy is recommended for validation purpose only.
+ **/
+ UINT8 TccActivationOffset;
+ UINT8 Rsvd[2]; ///< Reserved for future use and config block alignment
+ /**
+ Package Long duration turbo mode power limit (PL1).
+ Default is the TDP power limit of processor. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ **/
+ UINT16 PowerLimit1;
+ /**
+ Package Short duration turbo mode power limit (PL2). Allows for short excursions above TDP power limit.
+ Default = 1.25 * TDP Power Limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ **/
+ UINT16 PowerLimit2Power;
+ /**
+ Package PL3 power limit. PL3 is the CPU Peak Power Occurences Limit.
+ <b>Default: 0</b>. Range 0-65535. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ **/
+ UINT16 PowerLimit3;
+ /**
+ Package PL4 power limit. PL4 is a Preemptive CPU Package Peak Power Limit, it will never be exceeded.
+ Power is premptively lowered before limit is reached. <b>Default: 0</b>. Range 0-65535.
+ Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ **/
+ UINT16 PowerLimit4;
+ /**
+ Package Long duration turbo mode power limit (PL1) time window in seconds.
+ Used in calculating the average power over time.
+ Mobile: <b> 28s</b>
+ Desktop: <b> 8s</b>
+ Range: 0 - 128s
+ **/
+ UINT32 PowerLimit1Time;
+ /**
+ Power Limit 3 (PL3) time window in milliseconds.
+ Default: <b> 0 - Auto, use hw defaults</b>
+ Range: 0 - 750ms
+ Valid values are: 0,3-8,10,12,14,16,20,24,28,32,40,48,55,56,64
+ **/
+ UINT32 PowerLimit3Time;
+ /**
+ Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Average Temperature Limit (RATL).
+ For Y SKU, the recommended default for this policy is <b>5000: 5 seconds</b>, For all other SKUs the recommended default are <b>0: Disabled</b>
+ **/
+ UINT32 TccOffsetTimeWindowForRatl;
+
+ /**
+ 5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking part: LFM to Fused 5-Core Ratio Limit + OC Bins.
+ Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
+ - This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ **/
+ UINT8 FiveCoreRatioLimit;
+ /**
+ 6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking part: LFM to Fused 6-Core Ratio Limit + OC Bins.
+ Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
+ - This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ **/
+ UINT8 SixCoreRatioLimit;
+ /**
+ 7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking part: LFM to Fused 7-Core Ratio Limit + OC Bins.
+ Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
+ - This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ **/
+ UINT8 SevenCoreRatioLimit;
+ /**
+ 8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking part: LFM to Fused 8-Core Ratio Limit + OC Bins.
+ Note: OC Bins = 7 means fully unlocked, so range is LFM to 83.
+ - This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.
+ **/
+ UINT8 EightCoreRatioLimit;
+
+} CPU_POWER_MGMT_BASIC_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_POWER_MGMT_BASIC_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCustomConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCustomConfig.h new file mode 100644 index 0000000000..edb8182db5 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCustomConfig.h @@ -0,0 +1,76 @@ +/** @file
+ CPU Power Managment Custom Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
+#define _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
+
+#define CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION 1
+
+extern EFI_GUID gCpuPowerMgmtCustomConfigGuid;
+
+#pragma pack (push,1)
+
+///
+/// Defines the maximum number of custom ratio states supported.
+///
+#define MAX_CUSTOM_RATIO_TABLE_ENTRIES 40
+
+///
+/// Defines the maximum number of custom ConfigTdp entries supported.
+/// @warning: Changing this define would cause DWORD alignment issues in policy structures.
+///
+#define MAX_CUSTOM_CTDP_ENTRIES 3
+
+///
+/// This structure is used to describe the custom processor ratio table desired by the platform.
+///
+typedef struct {
+ UINT16 MaxRatio; ///< The maximum ratio of the custom ratio table.
+ UINT8 NumberOfEntries; ///< The number of custom ratio state entries, ranges from 2 to 16 for a valid custom ratio table.
+ UINT8 Rsvd0; ///< Reserved for DWORD alignment.
+ UINT32 Cpuid; ///< The CPU ID for which this custom ratio table applies.
+ UINT16 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The processor ratios in the custom ratio table.
+#if (MAX_CUSTOM_RATIO_TABLE_ENTRIES % 2)
+ UINT16 Rsvd1; ///< If there is an odd number of array entries, add padding for dword alignment.
+#endif
+} PPM_CUSTOM_RATIO_TABLE;
+
+///
+/// PPM Custom ConfigTdp Settings
+///
+typedef struct _PPM_CUSTOM_CTDP_TABLE {
+ UINT32 CustomPowerLimit1Time : 8; ///< Short term Power Limit time window value for custom cTDP level.
+ UINT32 CustomTurboActivationRatio : 8; ///< Turbo Activation Ratio for custom cTDP level.
+ UINT32 RsvdBits : 16; ///< Bits reserved for DWORD alignment.
+ UINT16 CustomPowerLimit1; ///< Short term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ UINT16 CustomPowerLimit2; ///< Long term Power Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+} PPM_CUSTOM_CTDP_TABLE;
+
+/**
+ CPU Power Management Custom Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ PPM_CUSTOM_RATIO_TABLE CustomRatioTable; ///< Custom Processor Ration Table Instance
+ PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES]; ///< Custom ConfigTdp Settings Instance
+ UINT32 ConfigTdpLock : 1; ///< Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable.
+ UINT32 ConfigTdpBios : 1; ///< Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 30; ///< Reserved for future use
+} CPU_POWER_MGMT_CUSTOM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_POWER_MGMT_CUSTOM_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtPsysConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtPsysConfig.h new file mode 100644 index 0000000000..05b1efd5b6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtPsysConfig.h @@ -0,0 +1,43 @@ +/** @file
+ CPU Power Management Psys(Platform) Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_POWER_MGMT_PSYS_CONFIG_H_
+#define _CPU_POWER_MGMT_PSYS_CONFIG_H_
+
+#define CPU_POWER_MGMT_PSYS_CONFIG_REVISION 1
+
+extern EFI_GUID gCpuPowerMgmtPsysConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Power Management Psys(Platform) Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 PsysPowerLimit1 : 1; ///< MSR 0x65C[15]: PL1 Enable activates the PL1 value to limit average platform power
+ UINT32 PsysPowerLimit1Time : 8; ///< MSR 0x65C[23:17]: PL1 timewindow in seconds.
+ UINT32 PsysPowerLimit2 : 1; ///< MSR 0x65C[47]: PL2 Enable activates the PL2 value to limit average platform power
+ UINT32 RsvdBits : 22; ///< Reserved for future use.
+ UINT16 PsysPowerLimit1Power; ///< MSR 0x65C[14:0]: Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ UINT16 PsysPowerLimit2Power; ///< MSR 0x65C[46:32]]: Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ UINT16 PsysPmax; ///< PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments. 0-1024 Watts. Value of 800 = 100W.
+ UINT8 Rsvd[2]; ///< Reserved for future use and config block alignment
+} CPU_POWER_MGMT_PSYS_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_POWER_MGMT_PSYS_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTestConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTestConfig.h new file mode 100644 index 0000000000..bf6e829fa3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTestConfig.h @@ -0,0 +1,145 @@ +/** @file
+ CPU Power Management Test Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_POWER_MGMT_TEST_CONFIG_H_
+#define _CPU_POWER_MGMT_TEST_CONFIG_H_
+
+#define CPU_POWER_MGMT_TEST_CONFIG_REVISION 1
+
+extern EFI_GUID gCpuPowerMgmtTestConfigGuid;
+
+#pragma pack (push,1)
+
+///
+/// PPM Package C State Limit
+///
+typedef enum {
+ PkgC0C1 = 0,
+ PkgC2,
+ PkgC3,
+ PkgC6,
+ PkgC7,
+ PkgC7s,
+ PkgC8,
+ PkgC9,
+ PkgC10,
+ PkgCMax,
+ PkgCpuDefault = 254,
+ PkgAuto = 255
+} MAX_PKG_C_STATE;
+
+///
+/// PPM Package C State Time Limit
+///
+typedef enum {
+ TimeUnit1ns = 0,
+ TimeUnit32ns,
+ TimeUnit1024ns,
+ TimeUnit32768ns,
+ TimeUnit1048576ns,
+ TimeUnit33554432ns,
+ TimeUnitMax
+} C_STATE_TIME_UNIT;
+
+///
+/// Custom Power Units. User can choose to enter in watts or 125 milliwatt increments.
+///
+typedef enum {
+ PowerUnitWatts = 0, ///< in Watts.
+ PowerUnit125MilliWatts, ///< in 125 milliwatt increments. Example: 90 power units times 125 mW equals 11.250 W.
+ PowerUnitMax
+} CUSTOM_POWER_UNIT;
+
+///
+/// PPM Interrupt Redirection Mode Selection
+///
+typedef enum {
+ PpmIrmFixedPriority = 0,
+ PpmIrmRoundRobin,
+ PpmIrmHashVector,
+ PpmIrmReserved1,
+ PpmIrmPairFixedPriority,
+ PpmIrmPairRoundRobin,
+ PpmIrmPairHashVector,
+ PpmIrmNoChange
+} PPM_IRM_SETTING;
+
+/**
+ CPU Power Management Test Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT32 Eist : 1; ///< Offset 28-31 Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
+ UINT32 EnergyEfficientPState : 1; ///< Enable or Disable Energy Efficient P-state will be applied in Turbo mode. 0: Disable; <b>1: Enable</b>
+ UINT32 EnergyEfficientTurbo : 1; ///< Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. 0: Disable; <b>1: Enable</b>
+ UINT32 TStates : 1; ///< Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
+ UINT32 BiProcHot : 1; ///< Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>.
+ UINT32 DisableProcHotOut : 1; ///< Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
+ UINT32 ProcHotResponse : 1; ///< Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
+ UINT32 DisableVrThermalAlert : 1; ///< Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
+ UINT32 AutoThermalReporting : 1; ///< Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
+ UINT32 ThermalMonitor : 1; ///< Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>.
+ UINT32 Cx : 1; ///< Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
+ UINT32 PmgCstCfgCtrlLock : 1; ///< If enabled, sets MSR 0xE2[15]; 0: Disable; <b>1: Enable</b>.
+ UINT32 C1e : 1; ///< Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
+ UINT32 C1AutoDemotion : 1; ///< Enable or Disable C6/C7 auto demotion to C1. 0: Disabled; <b>1: C1 Auto demotion</b>
+ UINT32 C1UnDemotion : 1; ///< Enable or Disable C1UnDemotion. 0: Disabled; <b>1: C1 Auto undemotion</b>
+ UINT32 C3AutoDemotion : 1; ///< Enable or Disable C6/C7 auto demotion to C3 0: Disabled; <b>1: C3 Auto demotion</b>
+ UINT32 C3UnDemotion : 1; ///< Enable or Disable C3UnDemotion. 0: Disabled; <b>1: C3 Auto undemotion</b>
+ UINT32 PkgCStateDemotion : 1; ///< Enable or Disable Package Cstate Demotion. 0: Disable; <b>1: Enable</b>
+ UINT32 PkgCStateUnDemotion : 1; ///< Enable or Disable Package Cstate UnDemotion. 0: Disable; <b>1: Enable</b>
+ UINT32 CStatePreWake : 1; ///< Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
+ UINT32 TimedMwait : 1; ///< Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
+ UINT32 CstCfgCtrIoMwaitRedirection : 1; ///< Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
+ UINT32 ProcHotLock : 1; ///< If enabled, sets MSR 0x1FC[23]; <b>0: Disable</b>; 1: Enable.
+ UINT32 RaceToHalt : 1; ///< Enable or Disable Race To Halt feature; 0: Disable; <b>1: Enable </b>. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)
+ UINT32 ConfigTdpLevel : 8; ///< Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP Up.
+ UINT16 CstateLatencyControl0Irtl; ///< Offset 32-33 Interrupt Response Time Limit of LatencyContol0 MSR 0x60A[9:0].
+ UINT16 CstateLatencyControl1Irtl; ///< Offset 34-35 Interrupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].
+ UINT16 CstateLatencyControl2Irtl; ///< Offset 36-37 Interrupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].
+ UINT16 CstateLatencyControl3Irtl; ///< Offset 38-39 Interrupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].
+ UINT16 CstateLatencyControl4Irtl; ///< Offset 40-41 Interrupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].
+ UINT16 CstateLatencyControl5Irtl; ///< Offset 42-43 Interrupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].
+ MAX_PKG_C_STATE PkgCStateLimit; ///< Offset 44 This field is used to set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state.
+ C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit; ///< Offset 45 TimeUnit for Latency Control0 MSR 0x60A[12:10]; <b>2: 1024ns</b>.
+ C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< Offset 46 TimeUnit for Latency Control1 MSR 0x60B[12:10]; <b>2: 1024ns</b>.
+ C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< Offset 47 TimeUnit for Latency Control2 MSR 0x60C[12:10]; <b>2: 1024ns</b>.
+ C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< Offset 48 TimeUnit for Latency Control3 MSR 0x633[12:10]; <b>2: 1024ns</b>.
+ C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< Offset 49 TimeUnit for Latency Control4 MSR 0x634[12:10]; <b>2: 1024ns</b>.
+ C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< Offset 50 TimeUnit for Latency Control5 MSR 0x635[12:10]; <b>2: 1024ns</b>.
+ /**
+ Offset 51 Default power unit in watts or in 125 milliwatt increments.
+ - 0: PowerUnitWatts.
+ - <b>1: PowerUnit125MilliWatts</b>.
+ **/
+ CUSTOM_POWER_UNIT CustomPowerUnit;
+ /**
+ Offset 52 Interrupt Redirection Mode Select.
+ - 0: Fixed priority.
+ - 1: Round robin.
+ - 2: Hash vector.
+ - <b>4: PAIR with fixed priority</b>.
+ - 5: PAIR with round robin.
+ - 6: PAIR with hash vector.
+ - 7: No change.
+ **/
+ PPM_IRM_SETTING PpmIrmSetting;
+ UINT8 Rsvd[4]; ///< Offset 53-56 Reserved for future use and config block alignment
+} CPU_POWER_MGMT_TEST_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_POWER_MGMT_TEST_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtVrConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtVrConfig.h new file mode 100644 index 0000000000..ad4ed76250 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtVrConfig.h @@ -0,0 +1,104 @@ +/** @file
+ CPU Power Management VR Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_POWER_MGMT_VR_CONFIG_H_
+#define _CPU_POWER_MGMT_VR_CONFIG_H_
+
+#define CPU_POWER_MGMT_VR_CONFIG_REVISION 2
+
+extern EFI_GUID gCpuPowerMgmtVrConfigGuid;
+
+#pragma pack (push,1)
+
+///
+/// Defines the maximum number of VR domains supported.
+/// @warning: Changing this define would cause DWORD alignment issues in policy structures.
+///
+#define MAX_NUM_VRS 4
+
+/**
+ CPU Power Management VR Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Deprecate SendVrMbxCmd
+ - Add SendVrMbxCmd1 for VR specific mailbox commands:
+ 001b: MPS IMPV8 VR mailbox command.
+ 010b: VR specific command sent for PS4 exit issue.
+ 100b: VR specific command sent for MPS VR decay issue.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 AcousticNoiseMitigation : 1; ///< Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
+ UINT32 FastPkgCRampDisableIa : 1; ///< Disable Fast Slew Rate for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True
+ UINT32 FastPkgCRampDisableGt : 1; ///< Disable Fast Slew Rate for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True
+ UINT32 FastPkgCRampDisableSa : 1; ///< Disable Fast Slew Rate for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. <b>0: False</b>; 1: True
+ UINT32 SlowSlewRateForIa : 2; ///< Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ UINT32 SlowSlewRateForGt : 2; ///< Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ UINT32 SlowSlewRateForSa : 2; ///< Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
+ /**
+ Deprecated:
+ VR specific mailbox commands.
+ <b>00b - no VR specific command sent.</b>
+ 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent.
+ 10b - VR specific command sent for PS4 exit issue.
+ 11b - Reserved.
+ **/
+ UINT32 SendVrMbxCmd : 2;
+ /**
+ VR specific mailbox commands.
+ <b>000b - no VR specific command sent.</b>
+ 001b - A VR mailbox command specifically for the MPS IMPV8 VR will be sent.
+ 010b - VR specific command sent for PS4 exit issue.
+ 100b - VR specific command sent for MPS VR decay issue.
+ Bitwise encoding. Allows for any combination of commands to be sent.
+ example 110b - to send both PS4 exit issue and MPS VR decay issue commands.
+ **/
+ UINT32 SendVrMbxCmd1 : 3;
+ UINT32 RsvdBits : 17; ///< Reserved for future use.
+ UINT8 PsysSlope; ///< PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in 1/100 increment values. Range is 0-200. 125 = 1.25.
+ UINT8 PsysOffset; ///< PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4, Range 0-255. Value of 100 = 100/4 = 25 offset.
+ UINT8 Rsvd[2]; ///< Reserved for future use and config block alignment
+ /** @name VR Settings
+ The VR related settings are sorted in an array where each index maps to the VR domain as defined below:
+ - 0 = System Agent VR
+ - 1 = IA Core VR
+ - 2 = GT unsliced VR
+ - 3 = GT sliced VR
+
+ The VR settings for a given domain must be populated in the appropriate index.
+ **/
+ ///@{
+ UINT16 TdcPowerLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. Range is 0-4095. 1000 = 125A. <b>0: 0 Amps</b>
+ UINT16 AcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.</b>
+ UINT16 DcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
+ UINT16 Psi1Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. <b>Default Value = 20A.</b>
+ UINT16 Psi2Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. <b>Default Value = 5A.</b>
+ UINT16 Psi3Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. <b>Default Value = 1A.</b>
+ UINT8 Psi3Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
+ UINT8 Psi4Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.
+ UINT8 ImonSlope[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. Range is 0-200. 125 = 1.25. <b>0: Auto</b>
+ INT16 ImonOffset[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
+ UINT16 IccMax[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A. <b>Default: 0 - Auto, no override</b>
+ UINT16 VrVoltageLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
+ UINT8 VrConfigEnable[MAX_NUM_VRS]; ///< Enable/Disable BIOS configuration of VR; 0: Disable; <b>1: Enable.</b>
+ UINT8 TdcEnable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable; </b>1: Enable
+ UINT8 TdcTimeWindow[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. <b>1ms default</b>
+ UINT8 TdcLock[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.
+ ///@}
+} CPU_POWER_MGMT_VR_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_POWER_MGMT_VR_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h new file mode 100644 index 0000000000..2b1fa5b3a5 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h @@ -0,0 +1,122 @@ +/** @file
+ CPU Test Config Block.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_TEST_CONFIG_H_
+#define _CPU_TEST_CONFIG_H_
+
+#define CPU_TEST_CONFIG_REVISION 2
+
+extern EFI_GUID gCpuTestConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ CPU Test Configuration Structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+
+ <b>Revision 2</b>:
+ - Deprecated and moved Hyperthreading to CPU_CONFIG_LIB_PREMEM_CONFIG
+ - Deprecated and moved CpuRatioOverride to CPU_CONFIG_LIB_PREMEM_CONFIG
+ - Deprecated and moved CpuRatio to CPU_CONFIG_LIB_PREMEM_CONFIG
+ - Deprecated and moved ActiveCoreCount to CPU_CONFIG_LIB_PREMEM_CONFIG
+ - Deprecated and moved JtagC10PowerGateDisable to CPU_CONFIG_LIB_PREMEM_CONFIG
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 HyperThreading : 1; ///< Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>.
+ /**
+ @deprecated since revision 2. Moved to CPU_CONFIG_LIB_PREMEM_CONFIG
+ Enable or disable override of default max non-turbo ratio. If enabled, BIOS will take the value specified in
+ CpuRatio policy and updates the max non-turbo ratio. See policy CpuRatio for more details.
+ - 0: Disable
+ - <b>1: Enable</b>
+ **/
+ UINT32 CpuRatioOverride : 1; ///< @deprecated since revision 2. Moved to CPU_CONFIG_LIB_PREMEM_CONFIG
+ UINT32 MlcStreamerPrefetcher : 1; ///< Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
+ UINT32 MlcSpatialPrefetcher : 1; ///< Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>.
+ UINT32 MonitorMwaitEnable : 1; ///< Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
+ UINT32 MachineCheckEnable : 1; ///< Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
+ UINT32 DebugInterfaceEnable : 1; ///< Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
+ UINT32 DebugInterfaceLockEnable : 1; ///< Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
+ /**
+ AP Idle Manner of waiting - Manner of which APs are waiting to be tasked by MP Services
+ - 1: HALT loop
+ - <b>2: MWAIT loop</b>
+ - 3: Run loop
+ **/
+ UINT32 ApIdleManner : 2;
+ /**
+ Settings for AP Handoff to OS - Type of loop AP is placed in before handing control to OS.
+ - 1: HALT loop
+ - <b>2: MWAIT loop</b>
+ **/
+ UINT32 ApHandoffManner : 2;
+ /**
+ @deprecated since revision 2. Moved to CPU_CONFIG_LIB_PREMEM_CONFIG
+ Number of processor cores to enable.
+ - <b> 0: All cores</b>
+ - 1: 1 core
+ - 2: 2 cores
+ - 3: 3 cores
+ **/
+ UINT32 ActiveCoreCount : 3; ///< @deprecated since revision 2. Moved to CPU_CONFIG_LIB_PREMEM_CONFIG
+ UINT32 JtagC10PowerGateDisable : 1; ///< Power JTAG in C10 and deeper power states; <b>0: Disable</b>; 1: Enable.
+ UINT32 ProcTraceOutputScheme : 1; ///< Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
+ UINT32 ProcTraceEnable : 1; ///< Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
+ /**
+ Memory region allocation for Processor Trace.
+ Total memory required is equal to the requested value * 2 (for memory alignment) * number of active processor threads.
+ Based on MEMORY_CONFIG_NO_CRC.PlatformMemorySize default, up to 2MB policy setting with up to 8 active threads is supported (32MB memory total).
+ For larger size requests, MEMORY_CONFIG_NO_CRC.PlatformMemorySize needs to be increased.
+ - 0: 4K
+ - 1: 8K
+ - 2: 16K
+ - 3: 32K
+ - 4: 64K
+ - 5: 128K
+ - 6: 256K
+ - 7: 512K
+ - 8: 1M
+ - 9: 2M
+ - 10: 4M
+ - 11: 8M
+ - 12: 16M
+ - 13: 32M
+ - 14: 64M
+ - 15: 128M
+ - <b>255: Disable</b>
+ **/
+ UINT32 ProcTraceMemSize : 8;
+ UINT32 ThreeStrikeCounterDisable : 1; ///< Disable Three strike counter; <b>0: FALSE</b>; 1: TRUE.
+ /**
+ This policy should be used to enable or disable Voltage Optimization feature.
+ Recommended defaults:
+ Enable - For Mobile SKUs(U/Y)
+ Disable - Rest of all SKUs other than Mobile.
+ **/
+ UINT32 VoltageOptimization : 1;
+ UINT32 RsvdBits : 4; ///< Reserved for future use
+ /**
+ @deprecated since revision 2. Moved to CPU_CONFIG_LIB_PREMEM_CONFIG
+ CpuRatio - When CpuRatioOverride is enabled, max non-turbo ratio (Flexible Ratio Boot) is set to CpuRatio.
+ **/
+ UINT8 CpuRatio;
+ UINT8 Rsvd[3]; ///< Reserved for future use
+} CPU_TEST_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_TEST_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuAccess.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuAccess.h new file mode 100644 index 0000000000..dc62fea6eb --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuAccess.h @@ -0,0 +1,21 @@ +/** @file
+ Macros to simplify and abstract the interface to CPU configuration.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPUACCESS_H_
+#define _CPUACCESS_H_
+
+#include "CpuRegs.h"
+#include "CpuDataStruct.h"
+#include "CpuPowerMgmt.h"
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h new file mode 100644 index 0000000000..e7caafa416 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuDataStruct.h @@ -0,0 +1,194 @@ +/** @file
+ This file declares various data structures used in CPU reference code.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_DATA_STRUCT_H
+#define _CPU_DATA_STRUCT_H
+
+//
+// The reason for changing the state of the processor Only applies to Disabling processors.
+// In future, we can add add/remove support
+//
+#define CPU_CAUSE_NOT_DISABLED 0x0000
+#define CPU_CAUSE_INTERNAL_ERROR 0x0001
+#define CPU_CAUSE_THERMAL_ERROR 0x0002
+#define CPU_CAUSE_SELFTEST_FAILURE 0x0004
+#define CPU_CAUSE_PREBOOT_TIMEOUT 0x0008
+#define CPU_CAUSE_FAILED_TO_START 0x0010
+#define CPU_CAUSE_CONFIG_ERROR 0x0020
+#define CPU_CAUSE_USER_SELECTION 0x0080
+#define CPU_CAUSE_BY_ASSOCIATION 0x0100
+#define CPU_CAUSE_UNSPECIFIED 0x8000
+
+typedef UINT32 CPU_STATE_CHANGE_CAUSE;
+
+///
+/// The data structure is used retrieve data required for MP initialization during S3 resume.
+///
+typedef struct {
+ BOOLEAN APState; ///< Indicates whether the newstate of the AP is enabled or disabled.
+ BOOLEAN S3BootPath; ///< TRUE: S3 Boot path. FALSE: Regular boot path.
+ EFI_PHYSICAL_ADDRESS WakeUpBuffer; ///< Buffer location used during AP Initialization
+ EFI_PHYSICAL_ADDRESS GdtrProfile; ///< Address of Global Descriptor Table
+ EFI_PHYSICAL_ADDRESS IdtrProfile; ///< address of Interrupt Descriptor Table
+ EFI_PHYSICAL_ADDRESS CpuPrivateData; ///< Address of CPU_PRIVATE_DATA structure
+ EFI_PHYSICAL_ADDRESS StackAddress; ///< Address of APs's stacks
+ EFI_PHYSICAL_ADDRESS SmramBase; ///< @deprecated Address of SMRAM base as seen by software executing on the processors
+ EFI_PHYSICAL_ADDRESS SmmStartImageBase; ///< @deprecated Address of SMM Start Image Base
+ UINT32 SmmStartImageSize; ///< @deprecated Size of SMM Start Image
+ UINT32 NumberOfCpus; ///< Number of processors
+} ACPI_CPU_DATA;
+
+///
+/// CPU information stored in SMRAM during DXE.
+///
+typedef struct {
+ //
+ // Guid as Signature.
+ //
+ EFI_GUID HeaderGuid;
+ EFI_PHYSICAL_ADDRESS AcpiCpuPointer;
+ ACPI_CPU_DATA AcpiCpuData;
+
+ //
+ // It points the data defined below.
+ //
+ EFI_PHYSICAL_ADDRESS GdtrProfileOffset;
+ EFI_PHYSICAL_ADDRESS GdtOffset;
+ EFI_PHYSICAL_ADDRESS IdtrProfileOffset;
+ EFI_PHYSICAL_ADDRESS IdtOffset;
+ EFI_PHYSICAL_ADDRESS CpuPrivateDataOffset;
+ EFI_PHYSICAL_ADDRESS S3BspMtrrTableOffset;
+ ///
+ /// We need put all the data buffer here as well.
+ /// These data will be copied to original location in S3.
+ ///
+ //
+ // DataBuffer size
+ //
+ UINT32 GdtrProfileSize;
+ UINT32 GdtSize;
+ UINT32 IdtrProfileSize;
+ UINT32 IdtSize;
+ UINT32 CpuPrivateDataSize;
+ UINT32 S3BspMtrrTableSize;
+} SMRAM_CPU_DATA;
+
+///
+/// Structure to hold the return value of AsmCpuid instruction
+///
+typedef struct {
+ UINT32 RegEax; ///< Value of EAX.
+ UINT32 RegEbx; ///< Value of EBX.
+ UINT32 RegEcx; ///< Value of ECX.
+ UINT32 RegEdx; ///< Value of EDX.
+} EFI_CPUID_REGISTER;
+
+///
+/// Structure to describe microcode header
+///
+typedef struct {
+ UINT32 HeaderVersion; ///< Version number of the update header.
+ UINT32 UpdateRevision; ///< Unique version number for the update.
+ UINT32 Date; ///< Date of the update creation.
+ UINT32 ProcessorId; ///< Signature of the processor that requires this update.
+ UINT32 Checksum; ///< Checksum of update data and header.
+ UINT32 LoaderRevision; ///< Version number of the microcode loader program.
+ UINT32 ProcessorFlags; ///< Lower 4 bits denoting platform type information.
+ UINT32 DataSize; ///< Size of encoded data in bytes.
+ UINT32 TotalSize; ///< Total size of microcode update in bytes.
+ UINT8 Reserved[12]; ///< Reserved bits.
+} CPU_MICROCODE_HEADER;
+
+///
+/// Structure to describe the extended signature table header of the microcode update
+///
+typedef struct {
+ UINT32 ExtendedSignatureCount; ///< Number of extended signature structures.
+ UINT32 ExtendedTableChecksum; ///< Checksum of update extended processor signature table.
+ UINT8 Reserved[12]; ///< Reserved bits.
+} CPU_MICROCODE_EXTENDED_TABLE_HEADER;
+
+///
+/// Structure to describe the data of the extended table of the microcode update
+///
+typedef struct {
+ UINT32 ProcessorSignature; ///< Extended signature of the processor that requires this update
+ UINT32 ProcessorFlag; ///< Lower 4 bits denoting platform type information
+ UINT32 ProcessorChecksum; ///< checksum of each of the extended update
+} CPU_MICROCODE_EXTENDED_TABLE;
+
+#pragma pack(1)
+///
+/// MSR_REGISTER definition as a Union of QWORDS, DWORDS and BYTES
+///
+typedef union _MSR_REGISTER {
+ UINT64 Qword; ///< MSR value in 64 bit QWORD.
+
+ ///
+ /// MSR value represented in two DWORDS
+ ///
+ struct {
+ UINT32 Low; ///< Lower DWORD of the 64 bit MSR value.
+ UINT32 High; ///< Higher DWORD of the 64 bit MSR value.
+ } Dwords;
+
+ ///
+ /// MSR value represented in eight bytes.
+ ///
+ struct {
+ UINT8 FirstByte; ///< First byte of the 64 bit MSR value.
+ UINT8 SecondByte; ///< Second byte of the 64 bit MSR value.
+ UINT8 ThirdByte; ///< Third byte of the 64 bit MSR value.
+ UINT8 FouthByte; ///< Fourth byte of the 64 bit MSR value.
+ UINT8 FifthByte; ///< Fifth byte of the 64 bit MSR value.
+ UINT8 SixthByte; ///< Sixth byte of the 64 bit MSR value.
+ UINT8 SeventhByte; ///< Seventh byte of the 64 bit MSR value.
+ UINT8 EighthByte; ///< Eigth byte of the 64 bit MSR value.
+ } Bytes;
+} MSR_REGISTER;
+
+///
+/// Store BIST data for BSP.
+///
+typedef struct {
+ UINT32 ApicId; ///< APIC ID
+ UINT32 Health; ///< BIST result
+} BIST_HOB_DATA;
+
+///
+/// Processor trace buffer size selection.
+///
+typedef enum {
+ Enum4K = 0,
+ Enum8K,
+ Enum16K,
+ Enum32K,
+ Enum64K,
+ Enum128K,
+ Enum256K,
+ Enum512K,
+ Enum1M,
+ Enum2M,
+ Enum4M,
+ Enum8M,
+ Enum16M,
+ Enum32M,
+ Enum64M,
+ Enum128M,
+ EnumProcTraceMemDisable
+} PROC_TRACE_MEM_SIZE;
+
+#pragma pack()
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h new file mode 100644 index 0000000000..a8ee41ec99 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h @@ -0,0 +1,29 @@ +/** @file
+ CPU Policy structure definition which will contain several config blocks during runtime.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_POLICY_COMMON_H_
+#define _CPU_POLICY_COMMON_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/CpuOverclockingConfig.h>
+#include <ConfigBlock/CpuConfig.h>
+#include <ConfigBlock/CpuPidTestConfig.h>
+#include <ConfigBlock/CpuPowerMgmtBasicConfig.h>
+#include <ConfigBlock/CpuPowerMgmtCustomConfig.h>
+#include <ConfigBlock/CpuPowerMgmtPsysConfig.h>
+#include <ConfigBlock/CpuPowerMgmtTestConfig.h>
+#include <ConfigBlock/CpuPowerMgmtVrConfig.h>
+#include <ConfigBlock/CpuTestConfig.h>
+#include <ConfigBlock/CpuConfigLibPreMemConfig.h>
+
+#endif // _CPU_POLICY_COMMON_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h new file mode 100644 index 0000000000..612b166010 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h @@ -0,0 +1,106 @@ +/** @file
+ This file contains define definitions specific to processor
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _POWER_MGMT_DEFINITIONS_H_
+#define _POWER_MGMT_DEFINITIONS_H_
+
+#define CSTATE_SUPPORTED 0x1
+#define ENHANCED_CSTATE_SUPPORTED 0x2
+#define C6_C7_SHORT_LATENCY_SUPPORTED 0x01
+#define C6_C7_LONG_LATENCY_SUPPORTED 0x02
+#define C7s_SHORT_LATENCY_SUPPORTED 0x03
+#define C7s_LONG_LATENCY_SUPPORTED 0x04
+//
+// Voltage offset definitions
+//
+#define OC_LIB_OFFSET_ADAPTIVE 0
+#define OC_LIB_OFFSET_OVERRIDE 1
+//
+// Platform Power Management Flags Bit Definitions:
+// These defines are also used in CPU0CST.ASL to check platform configuration
+// and build C-state table accordingly.
+//
+#define PPM_EIST BIT0 ///< Enhanced Intel Speed Step Technology.
+#define PPM_C1 BIT1 ///< C1 enabled, supported.
+#define PPM_C1E BIT2 ///< C1E enabled.
+#define PPM_C3 BIT3 ///< C3 enabled, supported.
+#define PPM_C6 BIT4 ///< C6 enabled, supported.
+#define PPM_C7 BIT5 ///< C7 enabled, supported.
+#define PPM_C7S BIT6 ///< C7S enabled, supported
+#define PPM_TM BIT7 ///< Adaptive Thermal Monitor.
+#define PPM_TURBO BIT8 ///< Long duration turbo mode
+#define PPM_CMP BIT9 ///< CMP.
+#define PPM_TSTATES BIT10 ///< CPU throttling states
+#define PPM_MWAIT_EXT BIT11 ///< MONITIOR/MWAIT Extensions supported.
+#define PPM_EEPST BIT12 ///< Energy efficient P-State Feature enabled
+#define PPM_TSTATE_FINE_GRAINED BIT13 ///< Fine grained CPU Throttling states
+#define PPM_CD BIT14 ///< Deep Cstate - C8/C9/C10
+#define PPM_TIMED_MWAIT BIT15 ///< Timed Mwait support
+#define C6_LONG_LATENCY_ENABLE BIT16 ///< 1=C6 Long and Short,0=C6 Short only
+#define C7_LONG_LATENCY_ENABLE BIT17 ///< 1=C7 Long and Short,0=C7 Short only
+#define C7s_LONG_LATENCY_ENABLE BIT18 ///< 1=C7s Long and Short,0=C7s Short only
+#define PPM_C8 BIT19 ///< 1= C8 enabled/supported
+#define PPM_C9 BIT20 ///< 1= C9 enabled/supported
+#define PPM_C10 BIT21 ///< 1= C10 enabled/supported
+#define PPM_HWP BIT22 ///< 1= HWP enabled/supported
+#define PPM_HWP_LVT BIT23 ///< 1= HWP LVT enabled/supported
+#define PPM_OC_UNLOCKED BIT24 ///< 1= Overclocking fully unlocked
+
+#define PPM_C_STATES 0x7A ///< PPM_C1 + PPM_C3 + PPM_C6 + PPM_C7 + PPM_C7S
+#define C3_LATENCY 0x4E
+#define C6_C7_SHORT_LATENCY 0x76
+#define C6_C7_LONG_LATENCY 0x94
+#define C8_LATENCY 0xFA
+#define C9_LATENCY 0x14C
+#define C10_LATENCY 0x3F2
+
+//
+// The following definitions are based on assumed location for the ACPI
+// Base Address. Modify as necessary base on platform-specific requirements.
+//
+#define PCH_ACPI_PBLK 0x1810
+#define PCH_ACPI_LV2 0x1814
+#define PCH_ACPI_LV3 0x1815
+#define PCH_ACPI_LV4 0x1816
+#define PCH_ACPI_LV6 0x1818
+#define PCH_ACPI_LV5 0x1817
+#define PCH_ACPI_LV7 0x1819
+
+//
+// C-State Latency (us) and Power (mW) for C1
+//
+#define C1_LATENCY 1
+#define C1_POWER 0x3E8
+#define C3_POWER 0x1F4
+#define C6_POWER 0x15E
+#define C7_POWER 0xC8
+#define C8_POWER 0xC8
+#define C9_POWER 0xC8
+#define C10_POWER 0xC8
+
+
+#define PID_DOMAIN_KP 0
+#define PID_DOMAIN_KI 1
+#define PID_DOMAIN_KD 2
+#define MAILBOX_PARAM_1_OFFSET 8
+
+///
+/// VR Domain Definitions
+///
+#define SKL_VR_DOMAIN_SA 0x0
+#define SKL_VR_DOMAIN_IA 0x1
+#define SKL_VR_DOMAIN_GTUS 0x2
+#define SKL_VR_DOMAIN_GTS 0x3
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuRegs.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuRegs.h new file mode 100644 index 0000000000..21b6dd6f4b --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/CpuRegs.h @@ -0,0 +1,330 @@ +/** @file
+ Register names for CPU registers
+
+ <b>Conventions</b>
+ - Definitions beginning with "MSR_" are MSRs
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_REGS_H_
+#define _CPU_REGS_H_
+
+///
+/// Arch-specific MSR defines in SDM, but not defined for SKL
+/// @{
+
+#define MSR_PLATFORM_INFO 0x000000CE
+#define N_PLATFORM_INFO_MIN_RATIO 40
+#define B_PLATFORM_INFO_RATIO_MASK 0xFF
+#define N_PLATFORM_INFO_MAX_RATIO 8
+#define B_MSR_PLATFORM_INFO_BIOSGUARD_AVAIL BIT35
+#define N_MSR_PLATFORM_INFO_CONFIG_TDP_NUM_LEVELS_OFFSET 33
+#define V_CONFIG_TDP_NUM_LEVELS_MASK (BIT34 | BIT33)
+#define B_PLATFORM_INFO_TDC_TDP_LIMIT BIT29
+#define N_PLATFORM_INFO_RATIO_LIMIT 28
+#define B_PLATFORM_INFO_RATIO_LIMIT BIT28
+#define B_PLATFORM_INFO_SAMPLE_PART BIT27
+#define B_PLATFORM_INFO_SMM_SAVE_CONTROL BIT16
+#define N_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET 30
+#define B_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET BIT30
+#define B_PLATFORM_INFO_TIMED_MWAIT_SUPPORTED BIT37
+#define B_PLATFORM_INFO_EDRAM_EN BIT57
+
+//
+// MSR_BROADWELL_PKG_CST_CONFIG_CONTROL: related defines
+//
+#define B_TIMED_MWAIT_ENABLE BIT31 ///< @todo Remove when bitfield definition is available.
+#define V_CSTATE_LIMIT_C1 0x01
+#define V_CSTATE_LIMIT_C3 0x02
+#define V_CSTATE_LIMIT_C6 0x03
+#define V_CSTATE_LIMIT_C7 0x04
+#define V_CSTATE_LIMIT_C7S 0x05
+#define V_CSTATE_LIMIT_C8 0x06
+#define V_CSTATE_LIMIT_C9 0x07
+#define V_CSTATE_LIMIT_C10 0x08
+
+#define MSR_PMG_IO_CAPTURE_BASE 0x000000E4
+#define B_MSR_PMG_CST_RANGE (BIT18 | BIT17 | BIT16)
+#define V_IO_CAPT_LVL2 (0x0 << 16) ///< C3
+#define V_IO_CAPT_LVL3 (0x1 << 16) ///< C6
+#define V_IO_CAPT_LVL4 (0x2 << 16) ///< C7
+#define V_IO_CAPT_LVL5 (0x3 << 16) ///< C8
+#define V_IO_CAPT_LVL6 (0x4 << 16) ///< C9
+#define V_IO_CAPT_LVL7 (0x5 << 16) ///< C10
+#define V_IO_CAPT_LVL2_BASE_ADDR_MASK 0xFFFF
+
+#define MSR_TEMPERATURE_TARGET 0x000001A2
+#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LOCK BIT31
+#define N_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LIMIT 24
+#define V_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_OFFSET_MASK 0x3F
+#define N_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_OFFSET (16)
+#define B_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_MASK (0xFF << 16)
+#define N_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET 8
+#define B_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET (0xFF << 8)
+#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_TIME_WINDOW (0x7F)
+#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_MASK 0xFF
+#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_CLAMP_BIT BIT7
+
+
+#define MSR_TURBO_RATIO_LIMIT 0x000001AD
+#define N_MSR_TURBO_RATIO_LIMIT_1C 0
+#define B_MSR_TURBO_RATIO_LIMIT_1C (0xFFULL << 0)
+#define N_MSR_TURBO_RATIO_LIMIT_2C 8
+#define B_MSR_TURBO_RATIO_LIMIT_2C (0xFFULL << 8)
+#define N_MSR_TURBO_RATIO_LIMIT_3C 16
+#define B_MSR_TURBO_RATIO_LIMIT_3C (0xFFULL << 16)
+#define N_MSR_TURBO_RATIO_LIMIT_4C 24
+#define B_MSR_TURBO_RATIO_LIMIT_4C (0xFFULL << 24)
+#define N_MSR_TURBO_RATIO_LIMIT_5C 32
+#define B_MSR_TURBO_RATIO_LIMIT_5C (0xFFULL << 32)
+#define N_MSR_TURBO_RATIO_LIMIT_6C 40
+#define B_MSR_TURBO_RATIO_LIMIT_6C (0xFFULL << 40)
+#define N_MSR_TURBO_RATIO_LIMIT_7C 48
+#define B_MSR_TURBO_RATIO_LIMIT_7C (0xFFULL << 48)
+#define N_MSR_TURBO_RATIO_LIMIT_8C 56
+#define B_MSR_TURBO_RATIO_LIMIT_8C (0xFFULL << 56)
+
+#define MSR_IA32_FEATURE_CONFIG 0x0000013C
+#define B_IA32_FEATURE_CONFIG_AES_DIS BIT1
+#define B_IA32_FEATURE_CONFIG_LOCK BIT0
+
+
+//
+// MSRs for SMM State Save Register
+//
+#define MSR_SMM_MCA_CAP 0x0000017D
+#define B_TARGETED_SMI BIT56
+#define N_TARGETED_SMI 56
+#define B_SMM_CPU_SVRSTR BIT57
+#define N_SMM_CPU_SVRSTR 57
+#define B_SMM_CODE_ACCESS_CHK BIT58
+#define N_SMM_CODE_ACCESS_CHK 58
+#define B_LONG_FLOW_INDICATION BIT59
+#define N_LONG_FLOW_INDICATION 59
+#define MSR_SMM_FEATURE_CONTROL 0x000004E0
+#define B_SMM_FEATURE_CONTROL_LOCK BIT0
+#define B_SMM_CPU_SAVE_EN BIT1
+#define B_SMM_CODE_CHK_EN BIT2
+
+/// @}
+
+
+///
+/// Bit defines for MSRs defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h.
+/// @{
+
+//
+// Number of fixed MTRRs
+//
+#define V_FIXED_MTRR_NUMBER 11
+
+
+//
+// Number of variable MTRRs
+//
+#define V_MAXIMUM_VARIABLE_MTRR_NUMBER 10
+
+//
+// Bit defines for MSR_IA32_MTRR_DEF_TYPE
+//
+#define B_CACHE_MTRR_VALID BIT11
+#define B_CACHE_FIXED_MTRR_VALID BIT10
+
+//
+// Bit defines for MSR_IA32_DEBUG_INTERFACE
+//
+#define B_DEBUG_INTERFACE_ENABLE BIT0
+#define B_DEBUG_INTERFACE_LOCK BIT30
+#define B_DEBUG_INTERFACE_DEBUG_STATUS BIT31
+
+/// @}
+
+///
+/// Other defines
+///
+
+//
+// Local APIC defines
+//
+#define APIC_REGISTER_LOCAL_ID_OFFSET 0x00000020
+#define APIC_REGISTER_APIC_VERSION_OFFSET 0x00000030
+#define APIC_REGISTER_SPURIOUS_VECTOR_OFFSET 0x000000F0
+#define APIC_REGISTER_ICR_LOW_OFFSET 0x00000300
+#define APIC_REGISTER_ICR_HIGH_OFFSET 0x00000310
+#define APIC_REGISTER_LINT0_VECTOR_OFFSET 0x00000350
+#define APIC_REGISTER_LINT1_VECTOR_OFFSET 0x00000360
+
+#define BROADCAST_MODE_SPECIFY_CPU 0x00
+#define BROADCAST_MODE_ALL_INCLUDING_SELF 0x01
+#define BROADCAST_MODE_ALL_EXCLUDING_SELF 0x02
+
+#ifndef DELIVERY_MODE_FIXED
+#define DELIVERY_MODE_FIXED 0x0
+#endif
+#ifndef DELIVERY_MODE_LOWEST_PRIORITY
+#define DELIVERY_MODE_LOWEST_PRIORITY 0x1
+#endif
+#ifndef DELIVERY_MODE_SMI
+#define DELIVERY_MODE_SMI 0x2
+#endif
+#ifndef DELIVERY_MODE_REMOTE_READ
+#define DELIVERY_MODE_REMOTE_READ 0x3
+#endif
+#ifndef DELIVERY_MODE_NMI
+#define DELIVERY_MODE_NMI 0x4
+#endif
+#ifndef DELIVERY_MODE_INIT
+#define DELIVERY_MODE_INIT 0x5
+#endif
+#ifndef DELIVERY_MODE_SIPI
+#define DELIVERY_MODE_SIPI 0x6
+#endif
+#ifndef DELIVERY_MODE_MAX
+#define DELIVERY_MODE_MAX 0x7
+#endif
+
+#ifndef TRIGGER_MODE_EDGE
+#define TRIGGER_MODE_EDGE 0x00
+#endif
+#ifndef TRIGGER_MODE_LEVEL
+#define TRIGGER_MODE_LEVEL 0x01
+#endif
+
+#ifndef CPU_FEATURE_DISABLE
+#define CPU_FEATURE_DISABLE 0
+#endif
+#ifndef CPU_FEATURE_ENABLE
+#define CPU_FEATURE_ENABLE 1
+#endif
+
+#define CACHE_UNCACHEABLE 0
+#define CACHE_WRITECOMBINING 1
+#define CACHE_WRITETHROUGH 4
+#define CACHE_WRITEPROTECTED 5
+#define CACHE_WRITEBACK 6
+
+
+//
+// Processor Definitions
+//
+#define CPUID_FULL_STEPPING 0x0000000F
+#define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0
+#define CPUID_FULL_FAMILY_MODEL_STEPPING 0x0FFF0FFF
+#define CPUID_FULL_FAMILY_MODEL_SKYLAKE_ULT_ULX 0x000406E0
+#define CPUID_FULL_FAMILY_MODEL_SKYLAKE_DT_HALO 0x000506E0
+#define CPUID_FULL_FAMILY_MODEL_KABYLAKE_ULT_ULX 0x000806E0
+#define CPUID_FULL_FAMILY_MODEL_KABYLAKE_DT_HALO 0x000906E0
+
+#ifndef STALL_ONE_MICRO_SECOND
+#define STALL_ONE_MICRO_SECOND 1
+#endif
+#ifndef STALL_ONE_MILLI_SECOND
+#define STALL_ONE_MILLI_SECOND 1000
+#endif
+
+#define BITS(x) (1 << (x))
+
+/**
+Notes :
+ 1. Bit position always starts at 0.
+ 2. Following macros are applicable only for Word aligned integers.
+**/
+#define BIT(Pos, Value) (1 << (Pos) & (Value))
+#define BITRANGE(From, Width, Value) (((Value) >> (From)) & ((1 << (Width)) - 1))
+
+///
+/// Enums for CPU Family IDs
+///
+typedef enum {
+ EnumCpuSklUltUlx = CPUID_FULL_FAMILY_MODEL_SKYLAKE_ULT_ULX,
+ EnumCpuSklDtHalo = CPUID_FULL_FAMILY_MODEL_SKYLAKE_DT_HALO,
+ EnumCpuKblUltUlxG0 = EnumCpuSklUltUlx,
+ EnumCpuKblDtHaloA0 = EnumCpuSklDtHalo,
+ EnumCpuKblUltUlx = CPUID_FULL_FAMILY_MODEL_KABYLAKE_ULT_ULX,
+ EnumCpuKblDtHalo = CPUID_FULL_FAMILY_MODEL_KABYLAKE_DT_HALO,
+ EnumCpuMax = CPUID_FULL_FAMILY_MODEL
+} CPU_FAMILY;
+
+///
+/// Enums for CPU Stepping IDs
+///
+typedef enum {
+ ///
+ /// Skylake ULX/ULT Steppings
+ ///
+ EnumSklB0 = 1,
+ EnumSklJ0 = 2,
+ EnumSklC0 = 2,
+ EnumSklK0 = 3,
+ EnumSklD0 = 3,
+ EnumSklMaxUltUlxStep = EnumSklD0,
+
+ ///
+ /// Kabylake ULX/ULT Steppings
+ ///
+ EnumKblG0 = 8,
+ EnumKblH0 = 9,
+ EnumKblJ0 = 9,
+ EnumKblY0 = 0xA,
+ EnumKblMaxUltUlxStep = EnumKblY0,
+
+ ///
+ /// Skylake DT/Halo Steppings
+ ///
+ EnumSklP0 = 0,
+ EnumSklQ0 = 1,
+ EnumSklM0 = 2,
+ EnumSklR0 = 3,
+ EnumSklS0 = 3,
+ EnumSklN0 = 3,
+ EnumSklMaxDtHaloStep = EnumSklN0,
+
+ ///
+ /// Kabylake DT/Halo Steppings
+ ///
+ EnumKblA0 = 8,
+ EnumKblB0 = 9,
+ EnumKblS0 = 9,
+ EnumKblM0 = 9,
+ EnumKblN0 = 0xA,
+ EnumKblMaxDtHaloStep = EnumKblN0,
+
+ ///
+ /// Max Stepping
+ ///
+ EnumCpuSteppingMax = CPUID_FULL_STEPPING
+} CPU_STEPPING;
+
+///
+/// Enums for CPU SKU IDs
+///
+typedef enum {
+ EnumCpuUlt = 0,
+ EnumCpuTrad,
+ EnumCpuUlx,
+ EnumCpuHalo,
+ EnumCpuUnknown
+} CPU_SKU;
+
+///
+/// Enums for CPU Generation
+///
+typedef enum {
+ EnumSklCpu = 0,
+ EnumKblCpu,
+ EnumCpuUnknownGeneration
+} CPU_GENERATION;
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h new file mode 100644 index 0000000000..0c2df2ff80 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h @@ -0,0 +1,96 @@ +/** @file
+ Header file for Cpu Mailbox Lib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_MAILBOX_LIB_H_
+#define _CPU_MAILBOX_LIB_H_
+
+//
+// Mailbox Related Definitions
+//
+
+/**
+ Generic Mailbox function for mailbox write commands. This function will
+ poll the mailbox interface for control, issue the write request, poll
+ for completion, and verify the write was succussful.
+
+ @param[in] MailboxType The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
+ @param[in] MailboxCommand Overclocking mailbox command data
+ @param[in] MailboxData Overclocking mailbox interface data
+ @param[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status values are:
+ - SUCCESS (0) Command succeeded.
+ - OC_LOCKED (1) Overclocking is locked. Service is read-only.
+ - INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
+ - MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
+ - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
+ - OC_NOT_SUPPORTED (5) Domain does not support overclocking.
+
+ @retval EFI_STATUS
+ - EFI_SUCCESS Command succeeded.
+ - EFI_INVALID_PARAMETER Invalid read data detected from pcode.
+ - EFI_UNSUPPORTED Unsupported MailboxType parameter.
+**/
+EFI_STATUS
+EFIAPI
+MailboxWrite (
+ IN UINT32 MailboxType,
+ IN UINT32 MailboxCommand,
+ IN UINT32 MailboxData,
+ OUT UINT32 *MailboxStatus
+ );
+
+/**
+ Generic Mailbox function for mailbox read commands. This function will write
+ the read request from MailboxType, and populate the read results in the MailboxDataPtr.
+
+ @param[in] MailboxType The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
+ @param[in] MailboxCommand Overclocking mailbox command data
+ @param[out] *MailboxDataPtr Pointer to the overclocking mailbox interface data
+ @param[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status are
+ - SUCCESS (0) Command succeeded.
+ - OC_LOCKED (1) Overclocking is locked. Service is read-only.
+ - INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
+ - MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
+ - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
+ - OC_NOT_SUPPORTED (5) Domain does not support overclocking.
+
+ @retval EFI_STATUS
+ - EFI_SUCCESS Command succeeded.
+ - EFI_INVALID_PARAMETER Invalid read data detected from pcode.
+ - EFI_UNSUPPORTED Unsupported MailboxType parameter.
+
+**/
+EFI_STATUS
+EFIAPI
+MailboxRead (
+ IN UINT32 MailboxType,
+ IN UINT32 MailboxCommand,
+ OUT UINT32 *MailboxDataPtr,
+ OUT UINT32 *MailboxStatus
+ );
+
+/**
+ Poll the run/busy bit of the mailbox until available or timeout expires.
+
+ @param[in] MailboxType
+
+ @retval EFI_STATUS
+ - EFI_SUCCESS Command succeeded.
+ - EFI_TIMEOUT Command timeout.
+**/
+EFI_STATUS
+EFIAPI
+PollMailboxReady (
+ IN UINT32 MailboxType
+ );
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h new file mode 100644 index 0000000000..d1ccc5e7fb --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h @@ -0,0 +1,102 @@ +/** @file
+ Header file for CpuPlatform Lib.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_PLATFORM_LIB_H_
+#define _CPU_PLATFORM_LIB_H_
+
+#include <CpuRegs.h>
+#include <CpuDataStruct.h>
+
+/**
+ Check CPU Type of the platform
+
+ @retval CPU_FAMILY CPU type
+**/
+CPU_FAMILY
+EFIAPI
+GetCpuFamily (
+ VOID
+ );
+
+/**
+ Return Cpu stepping type
+
+ @retval CPU_STEPPING Cpu stepping type
+**/
+CPU_STEPPING
+EFIAPI
+GetCpuStepping (
+ VOID
+ );
+
+/**
+ Return CPU Sku
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+EFIAPI
+GetCpuSku (
+ VOID
+ );
+
+
+/**
+ Returns the processor microcode revision of the processor installed in the system.
+
+ @retval Processor Microcode Revision
+**/
+UINT32
+GetCpuUcodeRevision (
+ VOID
+ );
+
+/**
+ Check if this microcode is correct one for processor
+
+ @param[in] Cpuid - processor CPUID
+ @param[in] MicrocodeEntryPoint - entry point of microcode
+ @param[in] Revision - revision of microcode
+
+ @retval CorrectMicrocode if this microcode is correct
+**/
+BOOLEAN
+CheckMicrocode (
+ IN UINT32 Cpuid,
+ IN CPU_MICROCODE_HEADER *MicrocodeEntryPoint,
+ IN UINT32 *Revision
+ );
+
+
+/**
+ Check on the processor if SGX is supported.
+
+ @retval True if SGX supported or FALSE if not
+**/
+BOOLEAN
+IsSgxSupported (
+ VOID
+ );
+
+/**
+ Get processor generation
+
+ @retval EnumSklCpu Executing thread is Skylake
+ @retval EnumKblCpu Executing thread is Kabylake
+**/
+CPU_GENERATION
+GetCpuGeneration (
+ VOID
+ );
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h new file mode 100644 index 0000000000..f05c5743d7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h @@ -0,0 +1,54 @@ +/** @file
+ Prototype of the CpuPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_POLICY_LIB_H_
+#define _CPU_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ Print whole CPU config blocks of SiPolicyPpi and serial out.
+
+ @param[in] SiPolicyPpi The SI Policy PPI instance
+**/
+VOID
+CpuPrintPolicy (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ );
+
+/**
+ Get CPU config block table total size.
+
+ @retval Size of CPU config block table
+**/
+UINT16
+EFIAPI
+CpuGetConfigBlockTotalSize (
+ VOID
+ );
+
+/**
+ CpuAddConfigBlocks add all Cpu config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add CPU config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+CpuAddConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+#endif // _PEI_CPU_POLICY_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuPolicyLibPreMem.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuPolicyLibPreMem.h new file mode 100644 index 0000000000..905937ec88 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Library/CpuPolicyLibPreMem.h @@ -0,0 +1,54 @@ +/** @file
+ Prototype of the CpuPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_PREMEM_POLICY_LIB_H_
+#define _CPU_PREMEM_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ Print whole CPU related config blocks of SI_PREMEM_POLICY_PPI and serial out.
+
+ @param[in] SiPreMemPolicyPpi The Si PreMem Policy PPI instance
+**/
+VOID
+CpuPreMemPrintPolicy (
+IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+);
+
+/**
+ Get CPU PREMEM config block table total size.
+
+ @retval Size of CPU PREMEM config block table
+**/
+UINT16
+EFIAPI
+CpuGetPreMemConfigBlockTotalSize (
+ VOID
+ );
+
+/**
+ CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add CPU PREMEM config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+CpuAddPreMemConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+#endif // _CPU_PREMEM_POLICY_LIB_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Protocol/CpuGlobalNvsArea.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Protocol/CpuGlobalNvsArea.h new file mode 100644 index 0000000000..6e807a3504 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Protocol/CpuGlobalNvsArea.h @@ -0,0 +1,167 @@ +/** @file
+ Definition of the CPU global NVS area protocol. This protocol
+ publishes the address and format of a global ACPI NVS buffer used as a communications
+ buffer between SMM/DXE/PEI code and ASL code.
+
+ @note Data structures defined in this protocol are not naturally aligned.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_GLOBAL_NVS_AREA_H_
+#define _CPU_GLOBAL_NVS_AREA_H_
+
+typedef struct _CPU_GLOBAL_NVS_AREA_PROTOCOL CPU_GLOBAL_NVS_AREA_PROTOCOL;
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gCpuGlobalNvsAreaProtocolGuid;
+
+//
+// Processor GlobalNvs Revisions
+//
+#define CPU_GLOBAL_NVS_AREA_REVISION 2
+
+#pragma pack(1)
+///
+/// Config TDP level settings.
+///
+typedef struct {
+ UINT16 CtdpPowerLimit1; ///< CTDP Power Limit1
+ UINT16 CtdpPowerLimit2; ///< CTDP Power Limit2
+ UINT8 CtdpPowerLimitWindow; ///< CTDP Power Limit Time Window
+ UINT8 CtdpCtc; ///< CTDP CTC
+ UINT8 CtdpTar; ///< CTDP TAR
+ UINT8 CtdpPpc; ///< CTDP PPC
+} PPM_CTDP_LEVEL_SETTINGS;
+
+///
+/// Global NVS Area definition
+///
+typedef struct {
+ /**
+ This member specifies the revision of the CPU_GLOBAL_NVS_AREA. This field is used to indicate backward
+ compatible changes to the NVS AREA. Any such changes to this PPI will result in an update in the revision number.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ **/
+ UINT8 Revision; ///< (0) CPU GlobalNvs Revision
+ //
+ // PPM Flag Values
+ //
+ UINT32 PpmFlags; ///< (1-4) PPM Flags
+ UINT8 Reserved; ///< (5) Reserved
+ //
+ // Thermal Configuration Values
+ //
+ UINT8 AutoCriticalTripPoint; ///< (6) Auto Critical Trip Point
+ UINT8 AutoPassiveTripPoint; ///< (7) Auto Passive Trip Point
+ UINT8 AutoActiveTripPoint; ///< (8) Auto Active Trip Point
+ UINT32 Cpuid; ///< (9) CPUID
+ //
+ // ConfigTDP Values
+ //
+ UINT8 ConfigurablePpc; ///< (13) Boot Mode vlues for _PPC
+ //
+ // ConfigTDP Level settngs
+ //
+ UINT8 CtdpLevelsSupported; ///< (14) ConfigTdp Number Of Levels
+ UINT8 ConfigTdpBootModeIndex; ///< (15) CTDP Boot Mode Index
+ ///
+ /// (16) CTDP Level 0 Power Limit1
+ /// (18) CTDP Level 0 Power Limit2
+ /// (20) CTDP Level 0 Power Limit1 Time Window
+ /// (21) CTDP Level 0 CTC
+ /// (22) CTDP Level 0 TAR
+ /// (23) CTDP Level 0 PPC
+ /// (24) CTDP Level 1 Power Limit1
+ /// (26) CTDP Level 1 Power Limit2
+ /// (28) CTDP Level 1 Power Limit1 Time Window
+ /// (29) CTDP Level 1 CTC
+ /// (30) CTDP Level 1 TAR
+ /// (31) CTDP Level 1 PPC
+ /// (32) CTDP Level 2 Power Limit1
+ /// (34) CTDP Level 2 Power Limit2
+ /// (36) CTDP Level 2 Power Limit1 Time Window
+ /// (37) CTDP Level 2 CTC
+ /// (38) CTDP Level 2 TAR
+ /// (39) CTDP Level 2 PPC
+ ///
+ PPM_CTDP_LEVEL_SETTINGS CtdpLevelSettings[3];
+ //
+ // Mwait Hints and Latency values for C3/C6/C7/C7S
+ //
+ UINT8 C3MwaitValue; ///< (40) Mwait Hint value for C3
+ UINT8 C6MwaitValue; ///< (41) Mwait Hint value for C6
+ UINT8 C7MwaitValue; ///< (42) Mwait Hint value for C6
+ UINT8 CDMwaitValue; ///< (43) Mwait Hint value for C7/C8/C9/C10
+ UINT16 C3Latency; ///< (44-45) Latency value for C3
+ UINT16 C6Latency; ///< (46-47) Latency Value for C6
+ UINT16 C7Latency; ///< (48-49) Latency Value for C6
+ UINT16 CDLatency; ///< (50-51) Latency Value for C7/C8/C9/C10
+ UINT16 CDIOLevel; ///< (52-53) IO Level Value for C7/C8/C9/C10
+ UINT16 CDPowerValue; ///< (54-55) Power Value for C7/C8/C9/C10
+ UINT8 MiscPowerManagementFlags; ///< (55) MiscPowerManagementFlags
+ //
+ // DTS
+ //
+ UINT8 EnableDigitalThermalSensor; ///< (57) DTS Function enable
+ UINT8 BspDigitalThermalSensorTemperature; ///< (58) Temperature of BSP
+ UINT8 ApDigitalThermalSensorTemperature; ///< (59) Temperature of AP
+ UINT8 DigitalThermalSensorSmiFunction; ///< (60) SMI function call via DTS IO Trap
+ UINT8 PackageDTSTemperature; ///< (61) Package temperature
+ UINT8 IsPackageTempMSRAvailable; ///< (62) Package Temperature MSR available
+ UINT8 Ap2DigitalThermalSensorTemperature; ///< (63) Temperature of the second AP
+ UINT8 Ap3DigitalThermalSensorTemperature; ///< (64) Temperature of the third AP
+ //
+ // BIOS Guard
+ //
+ UINT64 BiosGuardMemAddress; ///< (65-72) BIOS Guard Memory Address for Tool Interface
+ UINT8 BiosGuardMemSize; ///< (73) BIOS Guard Memory Size for Tool Interface
+ UINT16 BiosGuardIoTrapAddress; ///< (74-75) IoTrap Address for Tool Interface
+ UINT16 BiosGuardIoTrapLength; ///< (76-77) IoTrap Length for Tool Interface
+ //
+ // DTS I/O Trap
+ //
+ UINT16 DtsIoTrapAddress; ///< (78-79) DTS IO trap Address
+ UINT8 DtsIoTrapLength; ///< (80) DTS IO trap Length
+ UINT8 DtsAcpiEnable; ///< (81) DTS is in ACPI Mode Enabled
+
+ //
+ // Software Guard Extension
+ //
+ UINT8 SgxStatus; ///< (82) SE Status
+ UINT64 EpcBaseAddress; ///< (83-90) EPC Base Address
+ UINT64 EpcLength; ///< (91-98) EPC Length
+
+ //
+ // HWP
+ //
+ UINT8 HwpVersion; ///< (99) HWP Status
+ UINT16 HwpIoTrapAddress; ///< (100-101) IoTrap Address for HWP
+ UINT16 HwpIoTrapLength; ///< (102-103) IoTrap Length for HWP
+
+ UINT8 PowerState; ///< (104) Power State
+ UINT8 EnableHdcPolicy; ///< (105) Hardware Duty Cycling Policy
+
+ UINT8 HwpInterruptStatus; ///< (106) HWP Interrupt Status
+ UINT8 DtsInterruptStatus; ///< (107) DTS Interrupt Status
+} CPU_GLOBAL_NVS_AREA;
+#pragma pack()
+///
+/// CPU Global NVS Area Protocol
+///
+struct _CPU_GLOBAL_NVS_AREA_PROTOCOL {
+ CPU_GLOBAL_NVS_AREA *Area; ///< CPU NVS Area
+};
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h new file mode 100644 index 0000000000..d59994471d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h @@ -0,0 +1,128 @@ +/** @file
+ Protocol used to report CPU information
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_INFO_H_
+#define _CPU_INFO_H_
+
+#include <CpuDataStruct.h>
+
+typedef struct _CPU_INFO_PROTOCOL CPU_INFO_PROTOCOL;
+
+
+extern EFI_GUID gCpuInfoProtocolGuid;
+
+//
+// DXE_CPU_INFO_PROTOCOL revisions
+//
+#define CPU_INFO_PROTOCOL_REVISION 1
+
+//
+// Processor feature definitions.
+//
+#define TXT_SUPPORT BIT0
+#define VMX_SUPPORT BIT1
+#define XD_SUPPORT BIT2
+#define DCA_SUPPORT BIT3
+#define X2APIC_SUPPORT BIT4
+#define AES_SUPPORT BIT5
+#define HT_SUPPORT BIT6
+#define DEBUG_SUPPORT BIT7
+#define DEBUG_LOCK_SUPPORT BIT8
+#define PROC_TRACE_SUPPORT BIT9
+#define HDC_SUPPORT BIT10
+
+
+#pragma pack(1)
+///
+/// Cache descriptor information
+///
+typedef struct {
+ UINT8 Desc; ///< Cache Descriptor
+ UINT8 Level; ///< Cache Level
+ UINT8 Type; ///< Cache Type. 0: Data, 1: Instruction, 3: Unified
+ UINT32 Size; ///< Cache Size.
+ UINT16 Associativity; ///< Cache Ways of Associativity.
+} CACHE_DESCRIPTOR_INFO;
+
+///
+/// Processor information
+///
+typedef struct {
+ UINT32 CpuSignature; ///< Processor signature and version information.
+ UINT64 Features; ///< Features availability in the CPU based on reading ECX after doing Asmcpuid(EAX=1).
+ CHAR8 *BrandString; ///< Processor Brand String.
+ UINT8 NumSupportedCores; ///< Total Number of Supported Cores in CPU Package. If Dual core, 2 cores.
+ UINT8 NumSupportedThreadsPerCore; ///< Number of Supported Threads per Core.
+ UINT8 NumCores; ///< Number of Enabled or Active Cores.
+ UINT8 NumHts; ///< Number of Enabled Threads per Core. This will be 1 or 2.
+ UINT32 IntendedFreq; ///< Maximum non turbo ratio in MHz
+ UINT32 ActualFreq; ///< Actual frequency in MHz
+ UINT32 Voltage; ///< Current operating voltage.
+ CACHE_DESCRIPTOR_INFO *CacheInfo; ///< Cache descriptor information.
+ UINT8 MaxCacheSupported; ///< Maximum cache supported.
+ UINT8 SmmbaseSwSmiNumber; ///< Software SMI Number from Smbase.
+ UINT16 NumberOfPStates; ///< Number of P-States.
+} CPU_INFO;
+
+///
+/// This HOB is data structure representing two different address location in SMRAM to hold SMRAM CPU DATA.
+///
+typedef struct {
+ EFI_PHYSICAL_ADDRESS LockBoxData; ///< First location (address) of SMRAM CPU DATA.
+ EFI_PHYSICAL_ADDRESS SmramCpuData; ///< Second location (Address) of SMRAM CPU DATA.
+ UINT64 LockBoxSize; ///< Size of SMRAM CPU DATA.
+} SMRAM_CPU_INFO;
+
+///
+/// SGX Information
+///
+typedef struct {
+ UINT64 SgxSinitNvsData; ///< Sinit SE SVN Version saved and passed back in next boot
+} SGX_INFO;
+
+#pragma pack()
+
+///
+/// This protocol provides information about the common features available in this CPU.
+///
+struct _CPU_INFO_PROTOCOL {
+ /**
+ Revision for the protocol structure.
+ Any backwards compatible changes to this protocol will result in an update in the revision number.
+ Major changes will require publication of a new protocol
+
+ <b>Revision 1</b>:
+ - Initial version
+ **/
+ UINT8 Revision;
+ /**
+ CPU Supported Feature.
+ - BIT0: If set then processor supports TXT.
+ - BIT1: If set then processor supports virtual mode extensions.
+ - BIT2: If set then processor supports execute disable bit.
+ - BIT3: If set then processor supports DCA.
+ - BIT4: If set then processor supports X2APIC.
+ - BIT5: If set then processor supports Advanced Encryption Standard.
+ - BIT6: If set then processor supports hyperthreading.
+ - BIT7: If set then processor supports debug interface.
+ - BIT8: If set then processor supports debug interface lock.
+ - BIT9: If set then processor supports processor trace.
+ - BIT10: If Set then processor supports supports HDC.
+ **/
+ UINT64 CpuCommonFeatures;
+ CPU_INFO *CpuInfo; ///< Processor Basic Information
+ SMRAM_CPU_INFO *SmramCpuInfo; ///< SMRAM CPU Information
+ SGX_INFO *SgxInfo; ///< SGX Information
+};
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/CpuInitDataHob.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/CpuInitDataHob.h new file mode 100644 index 0000000000..cdc6c463b6 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/CpuInitDataHob.h @@ -0,0 +1,50 @@ +/** @file
+ Struct and GUID definitions for CpuInitDataHob.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_INIT_DATA_HOB_H_
+#define _CPU_INIT_DATA_HOB_H_
+
+#include <Ppi/SiPolicy.h>
+
+extern EFI_GUID gCpuInitDataHobGuid;
+
+#define MAX_PROCESSOR_THREADS 0x40
+
+///
+/// CPU Configuration Structure passed from PEI to DXE phase
+///
+typedef struct {
+ UINT32 ApHandoffManner : 2;
+ UINT32 ApIdleManner : 2;
+ UINT32 EnableDts : 2;
+ UINT32 HdcControl : 2;
+ UINT32 Hwp : 2;
+ UINT32 ConfigTdpBios : 1;
+ UINT32 RsvdBits :21;
+ UINT8 SmmbaseSwSmiNumber;
+ UINT8 Rsvd[3];
+} CPU_CONFIG_DATA;
+
+///
+/// This HOB is used to pass only the required information from PEI for DXE consumption.
+///
+typedef struct {
+ UINT32 Revision;
+ EFI_PHYSICAL_ADDRESS CpuConfigData; ///< CPU RC Config for DXE consumption
+ EFI_PHYSICAL_ADDRESS CpuGnvsPointer; ///< CPU_GLOBAL_NVS_AREA Pointer.
+ EFI_PHYSICAL_ADDRESS MpData; ///< Deprecated. Points to ACPI_CPU_DATA structure with multiprocessor data.
+ EFI_PHYSICAL_ADDRESS FvidTable; ///< FVID Table.
+ UINT32 SiliconInfo; ///< SILICON_INFO data
+} CPU_INIT_DATA_HOB;
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/CpuPrivateData.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/CpuPrivateData.h new file mode 100644 index 0000000000..13ca1f2a01 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/CpuPrivateData.h @@ -0,0 +1,27 @@ +/** @file
+ Struct definition for CpuPrivateData.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CPU_PRIVATE_DATA_H_
+#define _CPU_PRIVATE_DATA_H_
+
+#include <CpuInitDataHob.h>
+
+///
+/// CPU Private Data saved and restored for S3.
+///
+typedef struct {
+ UINT64 ProcessorTraceAddress[MAX_PROCESSOR_THREADS];
+ UINT32 S3BspMtrrTablePointer;
+} CPU_PRIVATE_DATA;
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/Library/CpuCommonLib.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/Library/CpuCommonLib.h new file mode 100644 index 0000000000..8099236d88 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/Library/CpuCommonLib.h @@ -0,0 +1,192 @@ +/** @file
+ Header file for Cpu Common Lib implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_COMMON_LIB_H_
+#define _CPU_COMMON_LIB_H_
+
+typedef UINT32 CPU_RESET_TYPE;
+
+#define NO_RESET 0
+#define WARM_RESET BIT0
+#define COLD_RESET (BIT0 | BIT1)
+
+
+/**
+ Set up flags in CR4 for XMM instruction enabling
+**/
+VOID
+EFIAPI
+XmmInit (
+ VOID
+ );
+
+/**
+ Enable "Machine Check Enable"
+**/
+VOID
+EFIAPI
+EnableMce (
+ VOID
+ );
+
+/**
+ Mtrr Synch Up Entry
+**/
+UINTN
+EFIAPI
+MpMtrrSynchUpEntry (
+ VOID
+ );
+
+/**
+ Mtrr Synch Up Exit
+**/
+VOID
+EFIAPI
+MpMtrrSynchUpExit (
+ UINTN Cr4
+ );
+
+/**
+ This procedure sends an IPI to the designated processor in
+ the requested delivery mode with the requested vector.
+
+ @param[in] ApicID - APIC ID of processor.
+ @param[in] VectorNumber - Vector number.
+ @param[in] DeliveryMode - I/O APIC Interrupt Deliver Modes
+
+ @retval EFI_INVALID_PARAMETER - Input paramters were not correct.
+ @retval EFI_NOT_READY - There was a pending interrupt
+ @retval EFI_SUCCESS - Interrupt sent successfully
+**/
+EFI_STATUS
+EFIAPI
+CpuSendIpi (
+ IN UINT32 ApicID,
+ IN UINTN VectorNumber,
+ IN UINTN DeliveryMode
+ );
+
+
+/**
+ Get APIC ID of processor
+
+ @retval APIC ID of processor
+**/
+UINT32
+GetCpuApicId (
+ VOID
+ );
+
+/**
+ Programs XAPIC registers.
+
+ @param[in] Bsp - Is this BSP?
+**/
+VOID
+ProgramXApic (
+ BOOLEAN Bsp
+ );
+
+/**
+ This function is to disable BIOS Write Protect in SMM phase.
+**/
+VOID
+EFIAPI
+CpuSmmDisableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ This function is to enable BIOS Write Protect in SMM phase.
+**/
+VOID
+EFIAPI
+CpuSmmEnableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ This function returns the maximum number of cores supported in this physical processor package.
+
+ @retval Maximum number of supported cores in the package.
+**/
+UINT8
+GetMaxSupportedCoreCount (
+ VOID
+ );
+
+/**
+ This function returns the actual factory-configured number of threads per core,
+ and actual factory-configured number of cores in this physical processor package.
+
+ @param[out] *ThreadsPerCore - variable that will store Maximum enabled threads per core
+ @param[out] *NumberOfCores - variable that will store Maximum enabled cores per die
+**/
+VOID
+GetSupportedCount (
+ OUT UINT16 *ThreadsPerCore, OPTIONAL
+ OUT UINT16 *NumberOfCores OPTIONAL
+ );
+
+
+/**
+ Check to see if the executing thread is BSP
+
+ @retval TRUE Executing thread is BSP
+ @retval FALSE Executing thread is AP
+**/
+BOOLEAN
+IsBsp (
+ VOID
+ );
+
+
+/**
+ Return TRUE if PRMRR base was already set on this core and was
+ locked
+
+ @retval TRUE PRMRR base was already set
+ @retval FALSE PRMRR base wasn't set
+**/
+BOOLEAN
+IsPrmrrAlreadySet (
+ VOID
+ );
+
+/**
+ Check if this is non-core processor - HT AP thread
+
+ @retval TRUE if this is HT AP thread
+ @retval FALSE if this is core thread
+**/
+BOOLEAN
+IsSecondaryThread (
+ VOID
+ );
+
+
+/**
+ Based on ResetType, perform warm or cold reset using PCH reset PPI.
+
+ @param[in] ResetType - CPU_RESET_TYPE to indicate which reset should be performed.
+
+ @retval EFI_SUCCESS - Function successful (system should already reset).
+ @retval EFI_UNSUPPORTED - Reset type unsupported.
+**/
+EFI_STATUS
+PerformWarmOrColdReset (
+ IN CPU_RESET_TYPE ResetType
+ );
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/PowerMgmtNvsStruct.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/PowerMgmtNvsStruct.h new file mode 100644 index 0000000000..e7f7c19279 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/IncludePrivate/PowerMgmtNvsStruct.h @@ -0,0 +1,178 @@ +/** @file
+ This file contains CPU Gnvs Struct specific to processor
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _POWER_MGMT_NVS_STRUCT_H_
+#define _POWER_MGMT_NVS_STRUCT_H_
+
+//
+// Processor Power Management GlobalNvs Revisions
+//
+#define CPU_GLOBAL_NVS_AREA_REVISION 2
+
+//
+// Structure Declarations
+//
+#pragma pack(1)
+///
+/// Config TDP level settings.
+///
+typedef struct {
+ UINT16 CtdpPowerLimit1; ///< CTDP Power Limit1
+ UINT16 CtdpPowerLimit2; ///< CTDP Power Limit2
+ UINT8 CtdpPowerLimitWindow; ///< CTDP Power Limit Time Window
+ UINT8 CtdpCtc; ///< CTDP CTC
+ UINT8 CtdpTar; ///< CTDP TAR
+ UINT8 CtdpPpc; ///< CTDP PPC
+} CTDP_LEVEL_SETTINGS;
+
+///
+/// CPU Global NVS Area definition
+///
+typedef struct {
+ /**
+ This member specifies the revision of the CPU_GLOBAL_NVS_AREA. This field is used to indicate backward
+ compatible changes to the NVS AREA. Any such changes to this PPI will result in an update in the revision number.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ **/
+ UINT8 Revision; ///< (0) CPU GlobalNvs Revision
+ //
+ // PPM Flag Values
+ //
+ UINT32 PpmFlags; ///< (1-4) PPM Flags
+ UINT8 Reserved; ///< (5) Reserved
+ //
+ // Thermal Configuration Values
+ //
+ UINT8 AutoCriticalTripPoint; ///< (6) Auto Critical Trip Point
+ UINT8 AutoPassiveTripPoint; ///< (7) Auto Passive Trip Point
+ UINT8 AutoActiveTripPoint; ///< (8) Auto Active Trip Point
+ UINT32 Cpuid; ///< (9) CPUID
+ //
+ // ConfigTDP Values
+ //
+ UINT8 ConfigurablePpc; ///< (13) Boot Mode vlues for _PPC
+ //
+ // ConfigTDP Level settngs
+ //
+ UINT8 CtdpLevelsSupported; ///< (14) ConfigTdp Number Of Levels
+ UINT8 ConfigTdpBootModeIndex; ///< (15) CTDP Boot Mode Index
+ ///
+ /// (16) CTDP Level 0 Power Limit1
+ /// (18) CTDP Level 0 Power Limit2
+ /// (20) CTDP Level 0 Power Limit1 Time Window
+ /// (21) CTDP Level 0 CTC
+ /// (22) CTDP Level 0 TAR
+ /// (23) CTDP Level 0 PPC
+ /// (24) CTDP Level 1 Power Limit1
+ /// (26) CTDP Level 1 Power Limit2
+ /// (28) CTDP Level 1 Power Limit1 Time Window
+ /// (29) CTDP Level 1 CTC
+ /// (30) CTDP Level 1 TAR
+ /// (31) CTDP Level 1 PPC
+ /// (32) CTDP Level 2 Power Limit1
+ /// (34) CTDP Level 2 Power Limit2
+ /// (36) CTDP Level 2 Power Limit1 Time Window
+ /// (37) CTDP Level 2 CTC
+ /// (38) CTDP Level 2 TAR
+ /// (39) CTDP Level 2 PPC
+ ///
+ CTDP_LEVEL_SETTINGS CtdpLevelSettings[3];
+ //
+ // Mwait Hints and Latency values for C3/C6/C7/C7S
+ //
+ UINT8 C3MwaitValue; ///< (40) Mwait Hint value for C3
+ UINT8 C6MwaitValue; ///< (41) Mwait Hint value for C6
+ UINT8 C7MwaitValue; ///< (42) Mwait Hint value for C6
+ UINT8 CDMwaitValue; ///< (43) Mwait Hint value for C7/C8/C9/C10
+ UINT16 C3Latency; ///< (44-45) Latency value for C3
+ UINT16 C6Latency; ///< (46-47) Latency Value for C6
+ UINT16 C7Latency; ///< (48-49) Latency Value for C6
+ UINT16 CDLatency; ///< (50-51) Latency Value for C7/C8/C9/C10
+ UINT16 CDIOLevel; ///< (52-53) IO Level Value for C7/C8/C9/C10
+ UINT16 CDPowerValue; ///< (54-55) Power Value for C7/C8/C9/C10
+ UINT8 MiscPowerManagementFlags; ///< (55) MiscPowerManagementFlags
+ //
+ // DTS
+ //
+ UINT8 EnableDigitalThermalSensor; ///< (57) DTS Function enable
+ UINT8 BspDigitalThermalSensorTemperature; ///< (58) Temperature of BSP
+ UINT8 ApDigitalThermalSensorTemperature; ///< (59) Temperature of AP
+ UINT8 DigitalThermalSensorSmiFunction; ///< (60) SMI function call via DTS IO Trap
+ UINT8 PackageDTSTemperature; ///< (61) Package temperature
+ UINT8 IsPackageTempMSRAvailable; ///< (62) Package Temperature MSR available
+ UINT8 Ap2DigitalThermalSensorTemperature; ///< (63) Temperature of the second AP
+ UINT8 Ap3DigitalThermalSensorTemperature; ///< (64) Temperature of the third AP
+ //
+ // BIOS Guard
+ //
+ UINT64 BiosGuardMemAddress; ///< (65-72) BIOS Guard Memory Address for Tool Interface
+ UINT8 BiosGuardMemSize; ///< (73) BIOS Guard Memory Size for Tool Interface
+ UINT16 BiosGuardIoTrapAddress; ///< (74-75) IoTrap Address for Tool Interface
+ UINT16 BiosGuardIoTrapLength; ///< (76-77) IoTrap Length for Tool Interface
+ //
+ // DTS I/O Trap
+ //
+ UINT16 DtsIoTrapAddress; ///< (78-79) DTS IO trap Address
+ UINT8 DtsIoTrapLength; ///< (80) DTS IO trap Length
+ UINT8 DtsAcpiEnable; ///< (81) DTS is in ACPI Mode Enabled
+
+ //
+ // Software Guard Extension
+ //
+ UINT8 SgxStatus; ///< (82) SE Status
+ UINT64 EpcBaseAddress; ///< (83-90) EPC Base Address
+ UINT64 EpcLength; ///< (91-98) EPC Length
+
+ //
+ // HWP
+ //
+ UINT8 HwpVersion; ///< (99) HWP Status
+ UINT16 HwpIoTrapAddress; ///< (100-101) IoTrap Address for HWP
+ UINT16 HwpIoTrapLength; ///< (102-103) IoTrap Length for HWP
+
+ UINT8 PowerState; ///< (104) Power State
+ UINT8 EnableHdcPolicy; ///< (105) Hardware Duty Cycling Policy
+
+ UINT8 HwpInterruptStatus; ///< (106) HWP Interrupt Status
+ UINT8 DtsInterruptStatus; ///< (107) DTS Interrupt Status
+} CPU_GLOBAL_NVS;
+#pragma pack()
+
+typedef struct _CPU_GLOBAL_NVS_AREA_CONFIG {
+ CPU_GLOBAL_NVS *Area;
+} CPU_GLOBAL_NVS_AREA_CONFIG;
+
+typedef struct _FVID_HEADER {
+ UINT32 Stepping; ///< Matches value returned by CPUID function 1
+ UINT16 MaxBusRatio; ///< Matches BUS_RATIO_MAX field in PERF_STS_MSR
+ UINT16 EistStates; ///< Number of states of FVID (N)
+} FVID_HEADER;
+
+typedef struct _FVID_STATE {
+ UINT32 State; ///< State Number (0 - N-1)
+ UINT16 BusRatio; ///< BUS_RATIO_SEL value to be written to PERF_CTL
+ UINT32 Power; ///< Typical power consumed by CPU in this state
+ UINT32 Limit16State; ///< State Number (0 - N-1) with limit 16 P-states
+ UINT16 Limit16BusRatio; ///< BUS_RATIO_SEL value to be written to PERF_CTL with limit 16 P-states
+ UINT32 Limit16Power; ///< Typical power consumed by CPU in this state with limit 16 P-states
+} FVID_STATE;
+
+typedef union _FVID_TABLE {
+ FVID_HEADER FvidHeader;
+ FVID_STATE FvidState;
+ UINT64 FvidData;
+} FVID_TABLE;
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.c new file mode 100644 index 0000000000..ed964d00c3 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.c @@ -0,0 +1,95 @@ +/** @file
+ Mailbox Library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+
+/**
+ Generic Mailbox function for mailbox write commands. This function will
+ poll the mailbox interface for control, issue the write request, poll
+ for completion, and verify the write was successful.
+
+ @param[in] MailboxType The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
+ @param[in] MailboxCommand Overclocking mailbox command data
+ @param[in] MailboxData Overclocking mailbox interface data
+ @param[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status values are:
+ - SUCCESS (0) Command succeeded.
+ - OC_LOCKED (1) Overclocking is locked. Service is read-only.
+ - INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
+ - MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
+ - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
+ - OC_NOT_SUPPORTED (5) Domain does not support overclocking.
+
+ @retval EFI_SUCCESS Command succeeded.
+ @retval EFI_INVALID_PARAMETER Invalid read data detected from pcode.
+ @retval EFI_UNSUPPORTED Unsupported MailboxType parameter.
+**/
+EFI_STATUS
+EFIAPI
+MailboxWrite (
+ IN UINT32 MailboxType,
+ IN UINT32 MailboxCommand,
+ IN UINT32 MailboxData,
+ OUT UINT32 *MailboxStatus
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Generic Mailbox function for mailbox read commands. This function will write
+ the read request from MailboxType, and populate the read results in the MailboxDataPtr.
+
+ @param[in] MailboxType The type of mailbox interface to read. The Overclocking mailbox is defined as MAILBOX_TYPE_OC = 2.
+ @param[in] MailboxCommand Overclocking mailbox command data
+ @param[out] *MailboxDataPtr Pointer to the overclocking mailbox interface data
+ @param[out] *MailboxStatus Pointer to the mailbox status returned from pcode. Possible mailbox status are
+ - SUCCESS (0) Command succeeded.
+ - OC_LOCKED (1) Overclocking is locked. Service is read-only.
+ - INVALID_DOMAIN (2) Invalid Domain ID provided in command data.
+ - MAX_RATIO_EXCEEDED (3) Ratio exceeds maximum overclocking limits.
+ - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds input VR's max voltage.
+ - OC_NOT_SUPPORTED (5) Domain does not support overclocking.
+
+ @retval EFI_SUCCESS Command succeeded.
+ @retval EFI_INVALID_PARAMETER Invalid read data detected from pcode.
+ @retval EFI_UNSUPPORTED Unsupported MailboxType parameter.
+**/
+EFI_STATUS
+EFIAPI
+MailboxRead (
+ IN UINT32 MailboxType,
+ IN UINT32 MailboxCommand,
+ OUT UINT32 *MailboxDataPtr,
+ OUT UINT32 *MailboxStatus
+ )
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Poll the run/busy bit of the mailbox until available or timeout expires.
+
+ @param[in] MailboxType
+
+ @retval EFI_SUCCESS Command succeeded.
+ @retval EFI_TIMEOUT Command timeout.
+**/
+EFI_STATUS
+EFIAPI
+PollMailboxReady (
+ IN UINT32 MailboxType
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf new file mode 100644 index 0000000000..0426e05802 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf @@ -0,0 +1,29 @@ +## @file
+# Component description file for Cpu Mailbox Null Lib
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseCpuMailboxLibNull
+FILE_GUID = 74F470BC-1769-4732-B9C0-EE9AB0B12411
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuMailboxLib
+
+[Packages]
+MdePkg/MdePkg.dec
+
+[Sources]
+BaseCpuMailboxLibNull.c
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPolicy.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPolicy.c new file mode 100644 index 0000000000..f871c21e6a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPolicy.c @@ -0,0 +1,286 @@ +/** @file
+ This file is PeiCpuPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "PeiCpuPolicyLibrary.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ Print CPU_CONFIG and serial out.
+
+ @param[in] CpuConfig Pointer to a CPU_CONFIG
+**/
+VOID
+CpuConfigPrint (
+ IN CONST CPU_CONFIG *CpuConfig
+ )
+{
+ DEBUG ((DEBUG_INFO, "------------------ CPU Config ------------------\n"));
+ DEBUG ((DEBUG_INFO, " CPU_CONFIG : AesEnable : 0x%x\n", CpuConfig->AesEnable));
+ DEBUG ((DEBUG_INFO, " CPU_CONFIG : EnableRsr : 0x%X\n", CpuConfig->EnableRsr));
+ DEBUG ((DEBUG_INFO, " CPU_CONFIG : EnableDts : 0x%x\n", CpuConfig->EnableDts));
+ DEBUG ((DEBUG_INFO, " CPU_CONFIG : SmmbaseSwSmiNumber : 0x%x\n", CpuConfig->SmmbaseSwSmiNumber));
+ DEBUG ((DEBUG_INFO, " CPU_CONFIG : TxtEnable : 0x%X\n", CpuConfig->TxtEnable));
+ DEBUG ((DEBUG_INFO, " CPU_CONFIG : MicrocodePatchAddress : 0x%x\n", CpuConfig->MicrocodePatchAddress));
+}
+
+
+/**
+ Print CPU_POWER_MGMT_BASIC_CONFIG and serial out.
+
+ @param[in] CpuPowerMgmtBasicConfig Pointer to a CPU_POWER_MGMT_BASIC_CONFIG
+**/
+VOID
+CpuPowerMgmtBasicConfigPrint (
+ IN CONST CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig
+ )
+{
+ DEBUG ((DEBUG_INFO, "------------------ CPU Power Mgmt Basic Config ------------------\n"));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG : OneCoreRatioLimit : 0x%X , TwoCoreRatioLimit = 0x%X , ThreeCoreRatioLimit = 0x%X , FourCoreRatioLimit = 0x%X \n", CpuPowerMgmtBasicConfig->OneCoreRatioLimit, \
+ CpuPowerMgmtBasicConfig->TwoCoreRatioLimit, \
+ CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit, \
+ CpuPowerMgmtBasicConfig->FourCoreRatioLimit, \
+ CpuPowerMgmtBasicConfig->FiveCoreRatioLimit, \
+ CpuPowerMgmtBasicConfig->SixCoreRatioLimit, \
+ CpuPowerMgmtBasicConfig->SevenCoreRatioLimit, \
+ CpuPowerMgmtBasicConfig->EightCoreRatioLimit));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: Hwp : 0x%x\n", CpuPowerMgmtBasicConfig->Hwp));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: SkipSetBootPState : 0x%x\n", CpuPowerMgmtBasicConfig->SkipSetBootPState));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: HdcControl : 0x%X\n", CpuPowerMgmtBasicConfig->HdcControl));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit2 : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit2));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TurboPowerLimitLock : 0x%x\n", CpuPowerMgmtBasicConfig->TurboPowerLimitLock));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3DutyCycle : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit3DutyCycle));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3Lock : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit3Lock));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit4Lock : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit4Lock));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccOffsetClamp : 0x%X\n", CpuPowerMgmtBasicConfig->TccOffsetClamp));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccOffsetLock : 0x%X\n", CpuPowerMgmtBasicConfig->TccOffsetLock));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TurboMode : 0x%x\n", CpuPowerMgmtBasicConfig->TurboMode));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccActivationOffset : 0x%X\n", CpuPowerMgmtBasicConfig->TccActivationOffset));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit1 : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit1));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit2Power : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit2Power));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3 : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit3));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit4 : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit4));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit1Time : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit1Time));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3Time : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit3Time));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccOffsetTimeWindowForRatl : 0x%X\n", CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl));
+}
+
+/**
+ Print CPU_POWER_MGMT_CUSTOM_CONFIG and serial out.
+
+ @param[in] CpuPowerMgmtCustomConfig Pointer to a CPU_POWER_MGMT_CUSTOM_CONFIG
+**/
+VOID
+CpuPowerMgmtCustomConfigPrint (
+ IN CONST CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig
+ )
+{
+ UINT32 Index = 0;
+ DEBUG ((DEBUG_INFO, "------------------ CPU Power Mgmt Custom Config ------------------\n"));
+ DEBUG ((DEBUG_INFO, "\n CustomRatioTable... \n"));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: VidNumber : 0x%x\n", CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: VidCpuid : 0x%x\n", CpuPowerMgmtCustomConfig->CustomRatioTable.Cpuid));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: VidMaxRatio : 0x%x\n", CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio));
+ for (Index = 0; Index < MAX_CUSTOM_RATIO_TABLE_ENTRIES; Index++) {
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: StateRatio[%d] : 0x%x\n", Index, CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatio[Index]));
+ }
+ for (Index = 0; Index < MAX_CUSTOM_CTDP_ENTRIES; Index++) {
+ DEBUG (
+ (DEBUG_INFO,
+ " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] CustomPowerLimit1 : 0x%x\n",
+ Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].CustomPowerLimit1)
+ );
+ DEBUG (
+ (DEBUG_INFO,
+ " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] CustomPowerLimit2 : 0x%x\n",
+ Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].CustomPowerLimit2)
+ );
+ DEBUG (
+ (DEBUG_INFO,
+ " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] CustomPowerLimit1Time : 0x%x\n",
+ Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].CustomPowerLimit1Time)
+ );
+ DEBUG (
+ (DEBUG_INFO,
+ " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] CustomTurboActivationRatio : 0x%x\n",
+ Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].CustomTurboActivationRatio)
+ );
+ }
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: ConfigTdpLock : 0x%x\n", CpuPowerMgmtCustomConfig->ConfigTdpLock));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: ConfigTdpBios : 0x%x\n", CpuPowerMgmtCustomConfig->ConfigTdpBios));
+}
+
+/**
+ Print CPU_TEST_CONFIG and serial out.
+
+ @param[in] CpuTestConfig Pointer to a CPU_TEST_CONFIG
+**/
+VOID
+CpuTestConfigPrint (
+ IN CONST CPU_TEST_CONFIG *CpuTestConfig
+ )
+{
+ DEBUG ((DEBUG_INFO, "------------------ CPU Test Config ------------------\n"));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MlcStreamerPrefetcher : 0x%X\n", CpuTestConfig->MlcStreamerPrefetcher));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MlcSpatialPrefetcher : 0x%X\n", CpuTestConfig->MlcSpatialPrefetcher));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MonitorMwaitEnable : 0x%X\n", CpuTestConfig->MonitorMwaitEnable));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MachineCheckEnable : 0x%X\n", CpuTestConfig->MachineCheckEnable));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: DebugInterfaceEnable : 0x%X\n", CpuTestConfig->DebugInterfaceEnable));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: DebugInterfaceLockEnable : 0x%X\n", CpuTestConfig->DebugInterfaceLockEnable));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ApIdleManner: 0x%X\n", CpuTestConfig->ApIdleManner));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ApHandoffManner: 0x%X\n", CpuTestConfig->ApHandoffManner));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcTraceOutputScheme : 0x%X\n", CpuTestConfig->ProcTraceOutputScheme));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcTraceEnable : 0x%X\n", CpuTestConfig->ProcTraceEnable));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcTraceMemSize : 0x%X\n", CpuTestConfig->ProcTraceMemSize));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ThreeStrikeCounterDisable : 0x%X\n", CpuTestConfig->ThreeStrikeCounterDisable));
+ DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: VoltageOptimization : 0x%X\n", CpuTestConfig->VoltageOptimization));
+}
+
+/**
+ Print CPU_PID_TEST_CONFIG and serial out.
+
+ @param[in] CpuPidTestConfig Pointer to a CPU_PID_TEST_CONFIG
+**/
+VOID
+CpuPidTestConfigPrint (
+ IN CONST CPU_PID_TEST_CONFIG *CpuPidTestConfig
+ )
+{
+ UINT32 Index = 0;
+ DEBUG ((DEBUG_INFO, "------------------ CPU PID Test Config ------------------\n"));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PidTuning : 0x%X\n", Index, CpuPidTestConfig->PidTuning));
+ if ( CpuPidTestConfig->PidTuning == 1) {
+ for (Index = PID_DOMAIN_KP; Index <= PID_DOMAIN_KD; Index++) {
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : Ratl[%X] : 0x%X\n", Index, CpuPidTestConfig->Ratl[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr0[%X] : 0x%X\n", Index, CpuPidTestConfig->VrTdcVr0[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr1[%X] : 0x%X\n", Index, CpuPidTestConfig->VrTdcVr1[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr2[%X] : 0x%X\n", Index, CpuPidTestConfig->VrTdcVr2[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr3[%X] : 0x%X\n", Index, CpuPidTestConfig->VrTdcVr3[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl1Msr[%X] : 0x%X\n", Index, CpuPidTestConfig->PbmPsysPl1Msr[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl1MmioPcs[%X] : 0x%X\n", Index, CpuPidTestConfig->PbmPsysPl1MmioPcs[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl2Msr[%X] : 0x%X\n", Index, CpuPidTestConfig->PbmPsysPl2Msr[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl2MmioPcs[%X] : 0x%X\n", Index, CpuPidTestConfig->PbmPsysPl2MmioPcs[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl1Msr[%X] : 0x%X\n", Index, CpuPidTestConfig->PbmPkgPl1Msr[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl1MmioPcs[%X] : 0x%X\n", Index, CpuPidTestConfig->PbmPkgPl1MmioPcs[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl2Msr[%X] : 0x%X\n", Index, CpuPidTestConfig->PbmPkgPl2Msr[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl2MmioPcs[%X] : 0x%X\n", Index, CpuPidTestConfig->PbmPkgPl2MmioPcs[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl1Msr[%X] : 0x%X\n", Index, CpuPidTestConfig->DdrPl1Msr[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl1MmioPcs[%X] : 0x%X\n", Index, CpuPidTestConfig->DdrPl1MmioPcs[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl2Msr[%X] : 0x%X\n", Index, CpuPidTestConfig->DdrPl2Msr[Index]));
+ DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl2MmioPcs[%X] : 0x%X\n", Index, CpuPidTestConfig->DdrPl2MmioPcs[Index]));
+ }
+ }
+}
+
+/**
+ Print CPU_POWER_MGMT_TEST_CONFIG and serial out.
+
+ @param[in] CpuPowerMgmtTestConfig Pointer to a CPU_POWER_MGMT_TEST_CONFIG
+**/
+VOID
+CpuPowerMgmtTestConfigPrint (
+ IN CONST CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig
+ )
+{
+ DEBUG ((DEBUG_INFO, "------------------ CPU Power Mgmt Test Config ------------------\n"));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: Eist : 0x%x\n", CpuPowerMgmtTestConfig->Eist));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: EnergyEfficientPState : 0x%x\n", CpuPowerMgmtTestConfig->EnergyEfficientPState));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: EnergyEfficientTurbo : 0x%x\n", CpuPowerMgmtTestConfig->EnergyEfficientTurbo));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: TStates : 0x%x\n", CpuPowerMgmtTestConfig->TStates));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: BiProcHot : 0x%x\n", CpuPowerMgmtTestConfig->BiProcHot));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: DisableProcHotOut : 0x%x\n", CpuPowerMgmtTestConfig->DisableProcHotOut));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ProcHotResponse : 0x%x\n", CpuPowerMgmtTestConfig->ProcHotResponse));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: DisableVrThermalAlert : 0x%x\n", CpuPowerMgmtTestConfig->DisableVrThermalAlert));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: AutoThermalReporting : 0x%x\n", CpuPowerMgmtTestConfig->AutoThermalReporting));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ThermalMonitor : 0x%x\n", CpuPowerMgmtTestConfig->ThermalMonitor));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: Cx : 0x%x\n", CpuPowerMgmtTestConfig->Cx));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PmgCstCfgCtrlLock : 0x%x\n", CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C1e : 0x%x\n", CpuPowerMgmtTestConfig->C1e));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C1Autodemotion : 0x%x\n", CpuPowerMgmtTestConfig->C1AutoDemotion));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C1Undemotion : 0x%x\n", CpuPowerMgmtTestConfig->C1UnDemotion));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C3AutoDemotion : 0x%x\n", CpuPowerMgmtTestConfig->C3AutoDemotion));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C3UnDemotion : 0x%x\n", CpuPowerMgmtTestConfig->C3UnDemotion));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PkgCState Demotion : 0x%x\n", CpuPowerMgmtTestConfig->PkgCStateDemotion));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PkgCstateUndemotion : 0x%x\n", CpuPowerMgmtTestConfig->PkgCStateUnDemotion));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CStatePreWake : 0x%x\n", CpuPowerMgmtTestConfig->CStatePreWake));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: TimedMwait : 0x%x\n", CpuPowerMgmtTestConfig->TimedMwait));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstCfgCtrIoMwaitRedirection : 0x%x\n", CpuPowerMgmtTestConfig->CstCfgCtrIoMwaitRedirection));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ProcHotLock : 0x%x\n", CpuPowerMgmtTestConfig->ProcHotLock));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ConfigTdpLevel : 0x%x\n", CpuPowerMgmtTestConfig->ConfigTdpLevel));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: RaceToHalt : 0x%x\n", CpuPowerMgmtTestConfig->RaceToHalt));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl0Irtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl1Irtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl2Irtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl3Irtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl4Irtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl5Irtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PkgCStateLimit : 0x%x\n", CpuPowerMgmtTestConfig->PkgCStateLimit));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl0TimeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl1TimeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl2TimeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl3TimeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl4TimeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl5TimeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit));
+ DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CustomPowerUnit : 0x%x\n", CpuPowerMgmtTestConfig->CustomPowerUnit));
+ DEBUG ((DEBUG_INFO, " PpmIrmSetting : 0x%x\n", CpuPowerMgmtTestConfig->PpmIrmSetting));
+}
+/**
+ Print whole CPU config blocks of SI_POLICY_PPI and serial out in PostMem.
+
+ @param[in] SiPolicyPpi The SI Policy PPI instance
+**/
+VOID
+CpuPrintPolicy (
+ IN SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+DEBUG_CODE_BEGIN();
+ EFI_STATUS Status;
+ CPU_CONFIG *CpuConfig;
+ CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig;
+ CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig;
+ CPU_TEST_CONFIG *CpuTestConfig;
+ CPU_PID_TEST_CONFIG *CpuPidTestConfig;
+ CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig;
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConfigGuid, (VOID *) &CpuPowerMgmtBasicConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomConfigGuid, (VOID *) &CpuPowerMgmtCustomConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (VOID *) &CpuTestConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPidTestConfigGuid, (VOID *) &CpuPidTestConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfigGuid, (VOID *) &CpuPowerMgmtTestConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "\n ------------------------ SiCpuPolicy Print Begin in PostMem----------------- \n"));
+ DEBUG ((DEBUG_INFO, " Revision= %x\n", SiPolicyPpi->TableHeader.Header.Revision));
+
+ CpuConfigPrint(CpuConfig);
+ CpuPowerMgmtBasicConfigPrint(CpuPowerMgmtBasicConfig);
+ CpuPowerMgmtCustomConfigPrint(CpuPowerMgmtCustomConfig);
+ CpuTestConfigPrint(CpuTestConfig);
+ CpuPidTestConfigPrint(CpuPidTestConfig);
+ CpuPowerMgmtTestConfigPrint(CpuPowerMgmtTestConfig);
+ DEBUG ((DEBUG_INFO, "\n ------------------------ SiCpuPolicy Print End in PostMem ----------------- \n\n"));
+DEBUG_CODE_END();
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c new file mode 100644 index 0000000000..49331f1471 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.c @@ -0,0 +1,430 @@ +/** @file
+ This file is PeiCpuPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "PeiCpuPolicyLibrary.h"
+#include <SaAccess.h>
+#include <IndustryStandard/Pci22.h>
+#include <Library/MmPciLib.h>
+#include <Library/SaPlatformLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PostCodeLib.h>
+
+#ifndef FSP_FLAG
+/**
+ Get the next microcode patch pointer.
+
+ @param[in, out] MicrocodeData - Input is a pointer to the last microcode patch address found,
+ and output points to the next patch address found.
+
+ @retval EFI_SUCCESS - Patch found.
+ @retval EFI_NOT_FOUND - Patch not found.
+**/
+EFI_STATUS
+EFIAPI
+RetrieveMicrocode (
+ IN OUT CPU_MICROCODE_HEADER **MicrocodeData
+ )
+{
+ UINTN MicrocodeStart;
+ UINTN MicrocodeEnd;
+ UINTN TotalSize;
+
+ if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) == 0) || (FixedPcdGet32 (PcdFlashMicrocodeFvSize) == 0)) {
+ return EFI_NOT_FOUND;
+ }
+
+ ///
+ /// Microcode binary in SEC
+ ///
+ MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) +
+ ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase))->HeaderLength +
+ sizeof (EFI_FFS_FILE_HEADER);
+
+ MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvSize);
+
+ if (*MicrocodeData == NULL) {
+ *MicrocodeData = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart;
+ } else {
+ if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) {
+ DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n"));
+ return EFI_NOT_FOUND;
+ }
+
+ TotalSize = (UINTN) ((*MicrocodeData)->TotalSize);
+ if (TotalSize == 0) {
+ TotalSize = 2048;
+ }
+
+ *MicrocodeData = (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + TotalSize);
+ if (*MicrocodeData >= (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd) || (*MicrocodeData)->TotalSize == (UINT32) -1) {
+ DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >= MicrocodeEnd \n"));
+ return EFI_NOT_FOUND;
+ }
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ Get the microcode patch pointer.
+
+ @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL if not found.
+**/
+EFI_PHYSICAL_ADDRESS
+PlatformCpuLocateMicrocodePatch (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ CPU_MICROCODE_HEADER *MicrocodeData;
+ EFI_CPUID_REGISTER Cpuid;
+ UINT32 UcodeRevision;
+ UINTN MicrocodeBufferSize;
+ VOID *MicrocodeBuffer = NULL;
+
+ AsmCpuid (
+ CPUID_VERSION_INFO,
+ &Cpuid.RegEax,
+ &Cpuid.RegEbx,
+ &Cpuid.RegEcx,
+ &Cpuid.RegEdx
+ );
+
+ UcodeRevision = GetCpuUcodeRevision ();
+ MicrocodeData = NULL;
+ while (TRUE) {
+ ///
+ /// Find the next patch address
+ ///
+ Status = RetrieveMicrocode (&MicrocodeData);
+ DEBUG ((DEBUG_INFO, "MicrocodeData = %x\n", MicrocodeData));
+
+ if (Status != EFI_SUCCESS) {
+ break;
+ } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision)) {
+ break;
+ }
+ }
+
+ if (EFI_ERROR (Status)) {
+ return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
+ }
+
+ ///
+ /// Check that microcode patch size is <= 128K max size,
+ /// then copy the patch from FV to temp buffer for faster access.
+ ///
+ MicrocodeBufferSize = (UINTN) MicrocodeData->TotalSize;
+
+ if (MicrocodeBufferSize <= MAX_MICROCODE_PATCH_SIZE) {
+ MicrocodeBuffer = AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferSize));
+ if (MicrocodeBuffer != NULL) {
+ DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n"));
+ CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize);
+
+ return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer;
+ } else {
+ DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
+ }
+ } else {
+ DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed size of 128K.\n"));
+ }
+ return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL;
+}
+#endif
+
+/**
+ Load Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadCpuConfigDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ CPU_CONFIG *CpuConfig;
+ CpuConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "CpuConfig->Header.GuidHob.Name = %g\n", &CpuConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "CpuConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuConfig->Header.GuidHob.Header.HobLength));
+
+ /********************************
+ CPU configuration
+ ********************************/
+ CpuConfig->AesEnable = CPU_FEATURE_ENABLE;
+ CpuConfig->EnableRsr = CPU_FEATURE_ENABLE;
+ CpuConfig->SmmbaseSwSmiNumber = (UINTN) PcdGet8 (PcdSmmbaseSwSmi);
+#ifndef FSP_FLAG
+ CpuConfig->MicrocodePatchAddress = PlatformCpuLocateMicrocodePatch ();
+#endif
+}
+
+
+/**
+ Load Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadCpuPowerMgmtBasicConfigDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig;
+ CPU_SKU CpuSku;
+ MSR_REGISTER TempMsr;
+
+ CpuPowerMgmtBasicConfig = ConfigBlockPointer;
+ CpuSku = GetCpuSku();
+
+ DEBUG ((DEBUG_INFO, "CpuPowerMgmtBasicConfig->Header.GuidHob.Name = %g\n", &CpuPowerMgmtBasicConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "CpuPowerMgmtBasicConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuPowerMgmtBasicConfig->Header.GuidHob.Header.HobLength));
+
+ /********************************
+ CPU Power Management Basic configuration
+ ********************************/
+ CpuPowerMgmtBasicConfig->Hwp = TRUE;
+ CpuPowerMgmtBasicConfig->HdcControl = TRUE;
+ CpuPowerMgmtBasicConfig->PowerLimit2 = TRUE;
+ CpuPowerMgmtBasicConfig->PowerLimit3Lock = TRUE;
+ ///
+ /// Initialize RATL (Runtime Average Temperature Limit) Config for SKL Y series.
+ ///
+ if (CpuSku == EnumCpuUlx) {
+ CpuPowerMgmtBasicConfig->TccActivationOffset = 10;
+ CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl = 5000; // 5 sec
+ CpuPowerMgmtBasicConfig->TccOffsetClamp = CPU_FEATURE_ENABLE;
+ }
+ CpuPowerMgmtBasicConfig->TurboMode = TRUE;
+
+ TempMsr.Qword = AsmReadMsr64 (MSR_TURBO_RATIO_LIMIT);
+ CpuPowerMgmtBasicConfig->OneCoreRatioLimit = TempMsr.Bytes.FirstByte;
+ CpuPowerMgmtBasicConfig->TwoCoreRatioLimit = TempMsr.Bytes.SecondByte;
+ CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit = TempMsr.Bytes.ThirdByte;
+ CpuPowerMgmtBasicConfig->FourCoreRatioLimit = TempMsr.Bytes.FouthByte;
+ CpuPowerMgmtBasicConfig->FiveCoreRatioLimit = TempMsr.Bytes.FifthByte;
+ CpuPowerMgmtBasicConfig->SixCoreRatioLimit = TempMsr.Bytes.SixthByte;
+ CpuPowerMgmtBasicConfig->SevenCoreRatioLimit = TempMsr.Bytes.SeventhByte;
+ CpuPowerMgmtBasicConfig->EightCoreRatioLimit = TempMsr.Bytes.EighthByte;
+}
+
+/**
+ Load Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadCpuPowerMgmtCustomConfigDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig;
+ CpuPowerMgmtCustomConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "CpuPowerMgmtCustomConfig->Header.GuidHob.Name = %g\n", &CpuPowerMgmtCustomConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "CpuPowerMgmtCustomConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuPowerMgmtCustomConfig->Header.GuidHob.Header.HobLength));
+
+ /********************************
+ CPU Power Management Custom configuration
+ ********************************/
+ CpuPowerMgmtCustomConfig->CustomRatioTable.Cpuid = (UINT16) ((GetCpuFamily() | GetCpuStepping()) & (0x0FFF));
+}
+
+/**
+ Load Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadCpuTestConfigDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ CPU_TEST_CONFIG *CpuTestConfig;
+ CPU_SKU CpuSku;
+ CpuTestConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "CpuTestConfig->Header.GuidHob.Name = %g\n", &CpuTestConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "CpuTestConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuTestConfig->Header.GuidHob.Header.HobLength));
+
+ CpuSku = GetCpuSku();
+ /********************************
+ CPU Test configuration
+ ********************************/
+ CpuTestConfig->MlcStreamerPrefetcher = CPU_FEATURE_ENABLE;
+ CpuTestConfig->MlcSpatialPrefetcher = CPU_FEATURE_ENABLE;
+ CpuTestConfig->MonitorMwaitEnable = CPU_FEATURE_ENABLE;
+ CpuTestConfig->MachineCheckEnable = CPU_FEATURE_ENABLE;
+ CpuTestConfig->DebugInterfaceLockEnable = CPU_FEATURE_ENABLE;
+ CpuTestConfig->ApIdleManner = 2; // AP Idle Manner default as Mwait Loop
+ CpuTestConfig->ApHandoffManner = 2; // AP Handoff to OS default as Mwait Loop
+ ///
+ /// Processor Trace
+ ///
+ CpuTestConfig->ProcTraceMemSize = EnumProcTraceMemDisable;
+
+ /**
+ This policy should be used to enable or disable Voltage Optimization feature.
+ Recommended defaults:
+ Enable - For Mobile SKUs(U/Y)
+ Disable - Rest of all SKUs other than Mobile.
+ **/
+ if ((CpuSku == EnumCpuUlx) || (CpuSku == EnumCpuUlt)){
+ CpuTestConfig->VoltageOptimization = CPU_FEATURE_ENABLE;
+ } else {
+ CpuTestConfig->VoltageOptimization = CPU_FEATURE_DISABLE;
+ }
+}
+
+/**
+ Load Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadCpuPidTestConfigDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ CPU_PID_TEST_CONFIG *CpuPidTestConfig;
+ CpuPidTestConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "CpuPidTestConfig->Header.GuidHob.Name = %g\n", &CpuPidTestConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "CpuPidTestConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuPidTestConfig->Header.GuidHob.Header.HobLength));
+
+ /********************************
+ CPU PID Test configuration
+ ********************************/
+}
+
+/**
+ Load Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadCpuPowerMgmtTestConfigDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig;
+ CPU_FAMILY CpuFamily;
+ CpuPowerMgmtTestConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "CpuPowerMgmtTestConfig->Header.GuidHob.Name = %g\n", &CpuPowerMgmtTestConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "CpuPowerMgmtTestConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuPowerMgmtTestConfig->Header.GuidHob.Header.HobLength));
+
+ /********************************
+ CPU Power Management Test configuration
+ ********************************/
+ CpuPowerMgmtTestConfig->Eist = TRUE;
+ CpuPowerMgmtTestConfig->EnergyEfficientPState = TRUE;
+ CpuPowerMgmtTestConfig->EnergyEfficientTurbo = TRUE;
+ CpuPowerMgmtTestConfig->BiProcHot = TRUE;
+ CpuPowerMgmtTestConfig->DisableProcHotOut = TRUE;
+ CpuPowerMgmtTestConfig->AutoThermalReporting = TRUE;
+ CpuPowerMgmtTestConfig->ThermalMonitor = TRUE;
+ CpuPowerMgmtTestConfig->Cx = TRUE;
+ CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock = TRUE;
+ CpuPowerMgmtTestConfig->C1e = TRUE;
+ CpuPowerMgmtTestConfig->C1AutoDemotion = TRUE;
+ CpuPowerMgmtTestConfig->C1UnDemotion = TRUE;
+ CpuPowerMgmtTestConfig->C3AutoDemotion = TRUE;
+ CpuPowerMgmtTestConfig->C3UnDemotion = TRUE;
+ CpuPowerMgmtTestConfig->PkgCStateDemotion = TRUE;
+ CpuPowerMgmtTestConfig->PkgCStateUnDemotion = TRUE;
+ CpuPowerMgmtTestConfig->CStatePreWake = TRUE;
+ CpuPowerMgmtTestConfig->RaceToHalt = TRUE;
+ CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl = C3_LATENCY;
+ CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl = C6_C7_SHORT_LATENCY;
+ CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl = C6_C7_LONG_LATENCY;
+ CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl = C8_LATENCY;
+ CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl = C9_LATENCY;
+ //
+ // If PS4 is disabled, program 2750us to MSR_C_STATE_LATENCY_CONTROL_5
+ //
+ CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl = C10_LATENCY;
+ CpuPowerMgmtTestConfig->PkgCStateLimit = PkgAuto;
+ CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit = TimeUnit1024ns;
+ CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit = TimeUnit1024ns;
+ CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit = TimeUnit1024ns;
+ CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit = TimeUnit1024ns;
+ CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit = TimeUnit1024ns;
+ CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit = TimeUnit1024ns;
+ CpuPowerMgmtTestConfig->CustomPowerUnit = PowerUnit125MilliWatts;
+ CpuPowerMgmtTestConfig->PpmIrmSetting = PpmIrmPairFixedPriority;
+
+ //
+ // Pkg C-state Demotion/Un Demotion
+ //
+ CpuFamily = GetCpuFamily();
+ if((CpuFamily == EnumCpuSklUltUlx) || (CpuFamily == EnumCpuSklDtHalo)){
+ CpuPowerMgmtTestConfig->PkgCStateDemotion = TRUE;
+ } else if((CpuFamily == EnumCpuKblUltUlx) || (CpuFamily == EnumCpuKblDtHalo)) {
+ CpuPowerMgmtTestConfig->PkgCStateDemotion = FALSE;
+ }
+ if((CpuFamily == EnumCpuSklUltUlx) || (CpuFamily == EnumCpuSklDtHalo)){
+ CpuPowerMgmtTestConfig->PkgCStateDemotion = TRUE;
+ } else if((CpuFamily == EnumCpuKblUltUlx) || (CpuFamily == EnumCpuKblDtHalo)) {
+ CpuPowerMgmtTestConfig->PkgCStateDemotion = FALSE;
+ }
+}
+
+static COMPONENT_BLOCK_ENTRY mCpuIpBlocks [] = {
+ {&gCpuConfigGuid, sizeof (CPU_CONFIG), CPU_CONFIG_REVISION, LoadCpuConfigDefault},
+ {&gCpuPowerMgmtBasicConfigGuid, sizeof (CPU_POWER_MGMT_BASIC_CONFIG), CPU_POWER_MGMT_BASIC_CONFIG_REVISION, LoadCpuPowerMgmtBasicConfigDefault},
+ {&gCpuPowerMgmtCustomConfigGuid, sizeof (CPU_POWER_MGMT_CUSTOM_CONFIG), CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION, LoadCpuPowerMgmtCustomConfigDefault},
+ {&gCpuTestConfigGuid, sizeof (CPU_TEST_CONFIG), CPU_TEST_CONFIG_REVISION, LoadCpuTestConfigDefault},
+ {&gCpuPidTestConfigGuid, sizeof (CPU_PID_TEST_CONFIG), CPU_PID_TEST_CONFIG_REVISION, LoadCpuPidTestConfigDefault},
+ {&gCpuPowerMgmtTestConfigGuid, sizeof (CPU_POWER_MGMT_TEST_CONFIG), CPU_POWER_MGMT_TEST_CONFIG_REVISION, LoadCpuPowerMgmtTestConfigDefault},
+};
+
+/**
+ Get CPU config block table total size.
+
+ @retval Size of CPU config block table
+**/
+UINT16
+EFIAPI
+CpuGetConfigBlockTotalSize (
+ VOID
+ )
+{
+ return GetComponentConfigBlockTotalSize (&mCpuIpBlocks[0], sizeof (mCpuIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
+}
+
+/**
+ CpuAddConfigBlocks add all Cpu config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add CPU config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+CpuAddConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ EFI_STATUS Status;
+ DEBUG((DEBUG_INFO, "CPU Post-Mem Entry \n"));
+ PostCode (0xC00);
+
+ Status = AddComponentConfigBlocks (ConfigBlockTableAddress, &mCpuIpBlocks[0], sizeof (mCpuIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));
+ DEBUG ((DEBUG_INFO, "CpuAddConfigBlocks Done \n"));
+ PostCode (0xC09);
+
+ return Status;
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf new file mode 100644 index 0000000000..24e9819e34 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLib.inf @@ -0,0 +1,67 @@ +## @file
+# Component description file for the PeiCpuPolicyLib library.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiCpuPolicyLib
+FILE_GUID = 5baafc8f-25c6-4d19-b141-585757509372
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = CpuPolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+CpuPlatformLib
+MmPciLib
+SaPlatformLib
+SiConfigBlockLib
+PostCodeLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiCpuPolicyLib.c
+PeiCpuPolicyLibrary.h
+CpuPrintPolicy.c
+
+[Ppis]
+gSiPolicyPpiGuid ## CONSUMES
+
+[FixedPcd]
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+
+[Pcd]
+gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi
+
+[Guids]
+gCpuConfigGuid ## PRODUCES
+gBiosGuardConfigGuid ## PRODUCES
+gCpuSgxConfigGuid ## PRODUCES
+gCpuPowerMgmtBasicConfigGuid ## PRODUCES
+gCpuPowerMgmtCustomConfigGuid ## PRODUCES
+gCpuTestConfigGuid ## PRODUCES
+gCpuPidTestConfigGuid ## PRODUCES
+gCpuPowerMgmtTestConfigGuid ## PRODUCES
+gCpuConfigLibPreMemConfigGuid ## PRODUCES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h new file mode 100644 index 0000000000..81301b475e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolicyLibrary.h @@ -0,0 +1,35 @@ +/** @file
+ Header file for the PeiCpuPolicyLib library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PEI_CPU_POLICY_LIBRARY_H_
+#define _PEI_CPU_POLICY_LIBRARY_H_
+
+#include <PiPei.h>
+#include <CpuAccess.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Ppi/MasterBootMode.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/CpuPolicyLib.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/SiConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Register/Cpuid.h>
+#include <Library/PcdLib.h>
+
+#define MAX_MICROCODE_PATCH_SIZE 0x20000
+
+#endif // _PEI_CPU_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/CpuPrintPolicy.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/CpuPrintPolicy.c new file mode 100644 index 0000000000..1807604405 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/CpuPrintPolicy.c @@ -0,0 +1,102 @@ +/** @file
+ This file is PeiCpuPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "PeiCpuPolicyLibrary.h"
+#include <Library/ConfigBlockLib.h>
+
+
+/**
+ Print CPU_CONFIG_LIB_PREMEM_CONFIG and serial out.
+
+ @param[in] CpuConfigLibPreMemConfig Pointer to a CPU_CONFIG_LIB_PREMEM_CONFIG
+
+**/
+VOID
+CpuConfigLibPreMemConfigPrint (
+ IN CONST CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig
+ )
+{
+ DEBUG ((DEBUG_INFO, "------------------ CPU Config Lib PreMem Config ------------------\n"));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : HyperThreading = 0x%x\n", CpuConfigLibPreMemConfig->HyperThreading));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : CpuRatioOverride = 0x%x\n", CpuConfigLibPreMemConfig->CpuRatioOverride));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : BootFrequency = 0x%x\n", CpuConfigLibPreMemConfig->BootFrequency));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : ActiveCoreCount = 0x%x\n", CpuConfigLibPreMemConfig->ActiveCoreCount));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : FClkFrequency = 0x%x\n", CpuConfigLibPreMemConfig->FClkFrequency));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : JtagC10PowerGateDisable = 0x%x\n", CpuConfigLibPreMemConfig->JtagC10PowerGateDisable));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : BistOnReset = 0x%x\n", CpuConfigLibPreMemConfig->BistOnReset));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : VmxEnable = 0x%x\n", CpuConfigLibPreMemConfig->VmxEnable));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : CpuRatio = 0x%x\n", CpuConfigLibPreMemConfig->CpuRatio));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : PeciSxReset = 0x%x\n", CpuConfigLibPreMemConfig->PeciSxReset));
+ DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : PeciC10Reset = 0x%x\n", CpuConfigLibPreMemConfig->PeciC10Reset));
+}
+
+/**
+ Print CPU_OVERCLOCKING_PREMEM_CONFIG and serial out.
+
+ @param[in] CpuOverClockingConfig Pointer to a CPU_OVERCLOCKING_CONFIG
+**/
+VOID
+CpuOverClockingPreMemConfigPrint (
+ IN CONST CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig
+ )
+{
+ DEBUG ((DEBUG_INFO, "------------------ CPU OverClocking Config ------------------\n"));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: OcSupport : 0x%X\n", CpuOverClockingPreMemConfig->OcSupport));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: OcLock : 0x%X\n", CpuOverClockingPreMemConfig->OcLock));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageMode : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageMode));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CorePllVoltageOffset : 0x%X\n", CpuOverClockingPreMemConfig->CorePllVoltageOffset));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreMaxOcRatio : 0x%X\n", CpuOverClockingPreMemConfig->CoreMaxOcRatio));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageOverride : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageOverride));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageAdaptive : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageAdaptive));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageOffset : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageOffset));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingMaxOcRatio : 0x%X\n", CpuOverClockingPreMemConfig->RingMaxOcRatio));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingMinOcRatio : 0x%X\n", CpuOverClockingPreMemConfig->RingMinOcRatio));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: Avx2RatioOffset : 0x%X\n", CpuOverClockingPreMemConfig->Avx2RatioOffset));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: BclkAdaptiveVoltage : 0x%X\n", CpuOverClockingPreMemConfig->BclkAdaptiveVoltage));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CorePllVoltageOffset : 0x%X\n", CpuOverClockingPreMemConfig->CorePllVoltageOffset));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: GtPllVoltageOffset : 0x%X\n", CpuOverClockingPreMemConfig->GtPllVoltageOffset));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingPllVoltageOffset : 0x%X\n", CpuOverClockingPreMemConfig->RingPllVoltageOffset));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: SaPllVoltageOffset : 0x%X\n", CpuOverClockingPreMemConfig->SaPllVoltageOffset));
+ DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: McPllVoltageOffset : 0x%X\n", CpuOverClockingPreMemConfig->McPllVoltageOffset));
+}
+
+
+/**
+ Print whole CPU Config blocks of SI_PREMEM_POLICY_PPI and serial out in PreMem.
+
+ @param[in] SiPreMemPolicyPpi The SI Pre-Mem Policy PPI instance
+**/
+VOID
+CpuPreMemPrintPolicy (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+DEBUG_CODE_BEGIN();
+ EFI_STATUS Status;
+ CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
+ CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverclockingPreMemConfig;
+
+ DEBUG ((DEBUG_INFO, "\n------------------------ CPU - SiPreMemPolicyPpi Print Begin in PreMem -----------------\n"));
+
+ DEBUG ((DEBUG_INFO, " Revision= %x\n", SiPreMemPolicyPpi->TableHeader.Header.Revision));
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclockingPreMemConfigGuid, (VOID *) &CpuOverclockingPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ CpuConfigLibPreMemConfigPrint(CpuConfigLibPreMemConfig);
+ CpuOverClockingPreMemConfigPrint(CpuOverclockingPreMemConfig);
+
+ DEBUG ((DEBUG_INFO, "\n------------------------ CPU - SiPreMemPolicyPpi Print End -----------------\n\n"));
+DEBUG_CODE_END();
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c new file mode 100644 index 0000000000..7d27c0b6dc --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLib.c @@ -0,0 +1,143 @@ +/** @file
+ This file is PeiCpuPolicy library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include "PeiCpuPolicyLibrary.h"
+#include <Library/MmPciLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PostCodeLib.h>
+#include <Library/SaPlatformLib.h>
+
+/**
+ Load Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+
+/**
+ Load Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadCpuConfigLibPreMemConfigDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
+ CPU_FAMILY CpuFamily;
+ CPU_SKU CpuSku;
+ BOOLEAN PegDisabled;
+ UINT64 MchBar;
+
+ CpuConfigLibPreMemConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "CpuConfigLibPreMemConfig->Header.GuidHob.Name = %g\n", &CpuConfigLibPreMemConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "CpuConfigLibPreMemConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuConfigLibPreMemConfig->Header.GuidHob.Header.HobLength));
+
+ /********************************
+ CPU Config Lib PreMem configuration
+ ********************************/
+ CpuConfigLibPreMemConfig->HyperThreading = CPU_FEATURE_ENABLE;
+ CpuConfigLibPreMemConfig->BootFrequency = 1; // Maximum non-turbo Performance
+ CpuConfigLibPreMemConfig->ActiveCoreCount = 0; // All cores active
+ CpuConfigLibPreMemConfig->VmxEnable = CPU_FEATURE_ENABLE;
+ CpuConfigLibPreMemConfig->CpuRatio = ((AsmReadMsr64 (MSR_PLATFORM_INFO) >> N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK);
+ ///
+ /// FCLK Frequency
+ ///
+ CpuFamily = GetCpuFamily();
+ CpuSku = GetCpuSku();
+ MchBar = MmioRead64 (MmPciBase (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN) + R_SA_MCHBAR) &~BIT0;
+ if (IsPchLinkDmi (CpuFamily) && (MmioRead16 (MmPciBase (SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG10_FUN_NUM) + PCI_VENDOR_ID_OFFSET) != 0xFFFF)) {
+ PegDisabled = MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET) & BIT3;
+ } else {
+ PegDisabled = 1;
+ }
+
+ ///
+ /// DT/Halo FCLK = 1GHz
+ /// Ulx/Ult FCLK = 800MHz
+ ///
+ if (((CpuSku == EnumCpuHalo) && (!PegDisabled)) || (CpuSku == EnumCpuTrad)) {
+ CpuConfigLibPreMemConfig->FClkFrequency = 1; // 1Ghz
+ } else {
+ CpuConfigLibPreMemConfig->FClkFrequency = 0; // 800MHz
+ }
+}
+
+/**
+ Load Overclocking pre-mem Config block default
+
+ @param[in] ConfigBlockPointer Pointer to config block
+**/
+VOID
+LoadCpuOverclockingPreMemConfigDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverclockingPreMemConfig;
+ CpuOverclockingPreMemConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "CpuOverclockingPreMemConfig->Header.GuidHob.Name = %g\n", &CpuOverclockingPreMemConfig->Header.GuidHob.Name));
+ DEBUG ((DEBUG_INFO, "CpuOverclockingPreMemConfig->Header.GuidHob.Header.HobLength = 0x%x\n", CpuOverclockingPreMemConfig->Header.GuidHob.Header.HobLength));
+
+ /********************************
+ CPU Overclocking PreMem configuration
+ ********************************/
+}
+
+
+static COMPONENT_BLOCK_ENTRY mCpuIpBlocksPreMem [] = {
+ {&gCpuConfigLibPreMemConfigGuid, sizeof (CPU_CONFIG_LIB_PREMEM_CONFIG), CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION, LoadCpuConfigLibPreMemConfigDefault},
+ {&gCpuOverclockingPreMemConfigGuid, sizeof (CPU_OVERCLOCKING_PREMEM_CONFIG), CPU_OVERCLOCKING_PREMEM_CONFIG_REVISION,LoadCpuOverclockingPreMemConfigDefault},
+};
+
+/**
+ Get CPU PREMEM config block table total size.
+
+ @retval Size of CPU PREMEM config block table
+**/
+UINT16
+EFIAPI
+CpuGetPreMemConfigBlockTotalSize (
+ VOID
+ )
+{
+ return GetComponentConfigBlockTotalSize (&mCpuIpBlocksPreMem[0], sizeof (mCpuIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY));
+}
+
+/**
+ CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add CPU PREMEM config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+CpuAddPreMemConfigBlocks (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ EFI_STATUS Status;
+ DEBUG((DEBUG_INFO, "CPU Pre-Mem Entry \n"));
+ PostCode (0xC00);
+
+ Status = AddComponentConfigBlocks (ConfigBlockTableAddress, &mCpuIpBlocksPreMem[0], sizeof (mCpuIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY));
+ DEBUG((DEBUG_INFO, "CpuAddPreMemConfigBlocks Done \n"));
+ PostCode (0xC0F);
+
+ return Status;
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLibPreMem.inf b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLibPreMem.inf new file mode 100644 index 0000000000..df6e20baef --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLibPreMem.inf @@ -0,0 +1,50 @@ +## @file
+# Component description file for the PeiCpuPolicyLibPreMem library.
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiCpuPolicyLibPreMem
+FILE_GUID = 5F4C2CF1-9DFE-4D99-9318-98FD31C8517D
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = CpuPolicyLibPreMem
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+CpuPlatformLib
+SiConfigBlockLib
+PostCodeLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiCpuPolicyLib.c
+PeiCpuPolicyLibrary.h
+CpuPrintPolicy.c
+
+[Ppis]
+gSiPreMemPolicyPpiGuid ## CONSUMES
+
+[Guids]
+gCpuSecurityPreMemConfigGuid ## PRODUCES
+gCpuTxtPreMemConfigGuid ## PRODUCES
+gCpuOverclockingPreMemConfigGuid ## PRODUCES
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLibrary.h new file mode 100644 index 0000000000..8c039b4591 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiCpuPolicyLibPreMem/PeiCpuPolicyLibrary.h @@ -0,0 +1,40 @@ +/** @file
+ Header file for the PeiCpuPolicyLib library.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PEI_CPU_POLICY_LIBRARY_H_
+#define _PEI_CPU_POLICY_LIBRARY_H_
+
+#include <PiPei.h>
+#include <Register/Cpuid.h>
+#include <CpuAccess.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Ppi/MasterBootMode.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/CpuPolicyLibPreMem.h>
+#include <Library/SiConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+
+//
+// TXT configuration defines
+//
+#define TXT_SINIT_MEMORY_SIZE 0x50000
+#define TXT_HEAP_MEMORY_SIZE 0xE0000
+#define TXT_LCP_PD_BASE 0x0 ///< Platform default LCP
+#define TXT_LCP_PD_SIZE 0x0 ///< Platform default LCP
+#define TXT_TGA_MEMORY_SIZE 0x0 ///< Maximum 512K of TGA memory (aperture)
+
+#endif // _PEI_CPU_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c new file mode 100644 index 0000000000..830803a909 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c @@ -0,0 +1,466 @@ +/** @file
+ CPU Platform Lib implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "CpuPlatformLibrary.h"
+#include <Library/MmPciLib.h>
+#include <SaRegs.h>
+
+#define SKIP_MICROCODE_CHECKSUM_CHECK 1
+
+/**
+ Return CPU Family ID
+
+ @retval CPU_FAMILY CPU Family ID
+**/
+CPU_FAMILY
+EFIAPI
+GetCpuFamily (
+ VOID
+ )
+{
+ EFI_CPUID_REGISTER Cpuid;
+ ///
+ /// Read the CPUID information
+ ///
+ AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
+ return ((CPU_FAMILY) (Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL));
+}
+
+/**
+ Return Cpu stepping type
+
+ @retval UINT8 Cpu stepping type
+**/
+CPU_STEPPING
+EFIAPI
+GetCpuStepping (
+ VOID
+ )
+{
+ EFI_CPUID_REGISTER Cpuid;
+ ///
+ /// Read the CPUID information
+ ///
+ AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
+ return ((CPU_STEPPING) (Cpuid.RegEax & CPUID_FULL_STEPPING));
+}
+
+/**
+ Return CPU Sku
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+EFIAPI
+GetCpuSku (
+ VOID
+ )
+{
+ UINT8 CpuType;
+ UINT16 CpuDid;
+ UINT32 CpuFamilyModel;
+ EFI_CPUID_REGISTER Cpuid;
+ BOOLEAN SkuFound;
+
+ SkuFound = TRUE;
+ CpuType = EnumCpuUnknown;
+
+ ///
+ /// Read the CPUID & DID information
+ ///
+ AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
+ CpuFamilyModel = Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL;
+ CpuDid = MmioRead16 (MmPciBase (0, 0, 0) + 2);
+
+ switch (CpuFamilyModel) {
+ case CPUID_FULL_FAMILY_MODEL_SKYLAKE_ULT_ULX:
+ switch (CpuDid) {
+ case V_SA_DEVICE_ID_SKL_MB_ULT_1: // ULT OPI
+ case V_SA_DEVICE_ID_KBL_MB_ULT_1: // KBL ULT OPI
+ CpuType = EnumCpuUlt;
+ break;
+
+ case V_SA_DEVICE_ID_SKL_MB_ULX_2: // ULX OPI
+ case V_SA_DEVICE_ID_SKL_MB_ULX_3: // ULX OPI
+ case V_SA_DEVICE_ID_KBL_MB_ULX_1: // ULX OPI
+ CpuType = EnumCpuUlx;
+ break;
+
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+ break;
+
+ case CPUID_FULL_FAMILY_MODEL_SKYLAKE_DT_HALO:
+ switch (CpuDid) {
+
+ case V_SA_DEVICE_ID_SKL_DT_1: // DT
+ case V_SA_DEVICE_ID_SKL_DT_2: // DT
+ case V_SA_DEVICE_ID_KBL_DT_1: // DT
+ case V_SA_DEVICE_ID_KBL_DT_2: // DT
+ CpuType = EnumCpuTrad;
+ break;
+
+ case V_SA_DEVICE_ID_SKL_HALO_1: // Halo
+ case V_SA_DEVICE_ID_SKL_HALO_2: // Halo
+ case V_SA_DEVICE_ID_KBL_HALO_1: // Halo
+ case V_SA_DEVICE_ID_KBL_HALO_2: // Halo
+ case V_SA_DEVICE_ID_SKL_SVR_1: // Server
+ case V_SA_DEVICE_ID_SKL_SVR_2: // Server
+ case V_SA_DEVICE_ID_KBL_SVR_1: // Server
+ case V_SA_DEVICE_ID_KBL_SVR_2: // Server
+ CpuType = EnumCpuHalo;
+ break;
+
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+ break;
+ case CPUID_FULL_FAMILY_MODEL_KABYLAKE_ULT_ULX:
+ switch (CpuDid) {
+ case V_SA_DEVICE_ID_KBL_MB_ULT_1: // KBL ULT OPI
+ case V_SA_DEVICE_ID_KBLR_MB_ULT_1: // KBL-R ULT
+ CpuType = EnumCpuUlt;
+ break;
+
+ case V_SA_DEVICE_ID_KBL_MB_ULX_1: // ULX OPI
+ CpuType = EnumCpuUlx;
+ break;
+
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+ break;
+
+ case CPUID_FULL_FAMILY_MODEL_KABYLAKE_DT_HALO:
+ switch (CpuDid) {
+
+ case V_SA_DEVICE_ID_KBL_DT_1: // DT
+ case V_SA_DEVICE_ID_KBL_DT_2: // DT
+ case V_SA_DEVICE_ID_CFL_DT: // DT
+ CpuType = EnumCpuTrad;
+ break;
+
+ case V_SA_DEVICE_ID_KBL_HALO_1: // Halo
+ case V_SA_DEVICE_ID_KBL_HALO_2: // Halo
+ case V_SA_DEVICE_ID_KBL_SVR_1: // Server
+ case V_SA_DEVICE_ID_KBL_SVR_2: // Server
+ CpuType = EnumCpuHalo;
+ break;
+
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+ break;
+
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+
+ if (!SkuFound) {
+ DEBUG ((DEBUG_ERROR, "Unsupported CPU SKU, Device ID: 0x%02X, CPUID: 0x%08X!\n", CpuDid, CpuFamilyModel));
+ ASSERT (FALSE);
+ }
+
+ return CpuType;
+}
+
+
+/**
+ Returns the processor microcode revision of the processor installed in the system.
+
+ @retval Processor Microcode Revision
+**/
+UINT32
+GetCpuUcodeRevision (
+ VOID
+ )
+{
+ AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0);
+ AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL);
+ return (UINT32) RShiftU64 (AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID), 32);
+}
+
+/**
+ Verify the DWORD type checksum
+
+ @param[in] ChecksumAddr - The start address to be checkumed
+ @param[in] ChecksumLen - The length of data to be checksumed
+
+ @retval EFI_SUCCESS - Checksum correct
+ @retval EFI_CRC_ERROR - Checksum incorrect
+**/
+EFI_STATUS
+Checksum32Verify (
+ IN UINT32 *ChecksumAddr,
+ IN UINT32 ChecksumLen
+ )
+{
+#if SKIP_MICROCODE_CHECKSUM_CHECK
+ return EFI_SUCCESS;
+#else
+ UINT32 Checksum;
+ UINT32 Index;
+
+ Checksum = 0;
+
+ for (Index = 0; Index < ChecksumLen; Index++) {
+ Checksum += ChecksumAddr[Index];
+ }
+
+ return (Checksum == 0) ? EFI_SUCCESS : EFI_CRC_ERROR;
+#endif
+}
+
+/**
+ This function checks the MCU revision to decide if BIOS needs to load
+ microcode.
+
+ @param[in] MicrocodePointer - Microcode in memory
+ @param[in] Revision - Current CPU microcode revision
+
+ @retval EFI_SUCCESS - BIOS needs to load microcode
+ @retval EFI_ABORTED - Don't need to update microcode
+**/
+EFI_STATUS
+CheckMcuRevision (
+ IN CPU_MICROCODE_HEADER *MicrocodePointer,
+ IN UINT32 Revision
+ )
+{
+ EFI_STATUS Status;
+ Status = EFI_ABORTED;
+
+ if ((MicrocodePointer->UpdateRevision & 0x80000000) ||
+ (MicrocodePointer->UpdateRevision > Revision) ||
+ (Revision == 0)) {
+ Status = EFI_SUCCESS;
+ }
+
+ return Status;
+}
+
+/**
+ Check if this microcode is correct one for processor
+
+ @param[in] Cpuid - processor CPUID
+ @param[in] MicrocodeEntryPoint - entry point of microcode
+ @param[in] Revision - revision of microcode
+
+ @retval CorrectMicrocode if this microcode is correct
+**/
+BOOLEAN
+CheckMicrocode (
+ IN UINT32 Cpuid,
+ IN CPU_MICROCODE_HEADER *MicrocodeEntryPoint,
+ IN UINT32 *Revision
+ )
+{
+ EFI_STATUS Status;
+ UINT8 ExtendedIndex;
+ MSR_IA32_PLATFORM_ID_REGISTER Msr;
+ UINT32 ExtendedTableLength;
+ UINT32 ExtendedTableCount;
+ BOOLEAN CorrectMicrocode;
+ CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable;
+ CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader;
+
+ Status = EFI_NOT_FOUND;
+ ExtendedTableLength = 0;
+ CorrectMicrocode = FALSE;
+
+ if (MicrocodeEntryPoint == NULL) {
+ return FALSE;
+ }
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
+
+ ///
+ /// Check if the microcode is for the Cpu and the version is newer
+ /// and the update can be processed on the platform
+ ///
+ if ((MicrocodeEntryPoint->HeaderVersion == 0x00000001) &&
+ !EFI_ERROR (CheckMcuRevision (MicrocodeEntryPoint, *Revision))
+ ) {
+ if ((MicrocodeEntryPoint->ProcessorId == Cpuid) && (MicrocodeEntryPoint->ProcessorFlags & (1 << (UINT8) Msr.Bits.PlatformId))) {
+ if (MicrocodeEntryPoint->DataSize == 0) {
+ Status = Checksum32Verify ((UINT32 *) MicrocodeEntryPoint, 2048 / sizeof (UINT32));
+ } else {
+ Status = Checksum32Verify (
+ (UINT32 *) MicrocodeEntryPoint,
+ (MicrocodeEntryPoint->DataSize + sizeof (CPU_MICROCODE_HEADER)) / sizeof (UINT32)
+ );
+ }
+
+ if (!EFI_ERROR (Status)) {
+ CorrectMicrocode = TRUE;
+ }
+ } else if ((MicrocodeEntryPoint->DataSize != 0)) {
+ ///
+ /// Check the Extended Signature if the entended signature exist
+ /// Only the data size != 0 the extended signature may exist
+ ///
+ ExtendedTableLength = MicrocodeEntryPoint->TotalSize - (MicrocodeEntryPoint->DataSize + sizeof (CPU_MICROCODE_HEADER));
+ if (ExtendedTableLength != 0) {
+ ///
+ /// Extended Table exist, check if the CPU in support list
+ ///
+ ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINT8 *) (MicrocodeEntryPoint) + MicrocodeEntryPoint->DataSize + 48);
+ ///
+ /// Calulate Extended Checksum
+ ///
+ if ((ExtendedTableLength % 4) == 0) {
+ Status = Checksum32Verify ((UINT32 *) ExtendedTableHeader, ExtendedTableLength / sizeof (UINT32));
+ if (!EFI_ERROR (Status)) {
+ ///
+ /// Checksum correct
+ ///
+ ExtendedTableCount = ExtendedTableHeader->ExtendedSignatureCount;
+ ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader + 1);
+ for (ExtendedIndex = 0; ExtendedIndex < ExtendedTableCount; ExtendedIndex++) {
+ ///
+ /// Verify Header
+ ///
+ if ((ExtendedTable->ProcessorSignature == Cpuid) && (ExtendedTable->ProcessorFlag & (1 << (UINT8) Msr.Bits.PlatformId))) {
+ Status = Checksum32Verify (
+ (UINT32 *) ExtendedTable,
+ sizeof (CPU_MICROCODE_EXTENDED_TABLE) / sizeof (UINT32)
+ );
+ if (!EFI_ERROR (Status)) {
+ ///
+ /// Find one
+ ///
+ CorrectMicrocode = TRUE;
+ break;
+ }
+ }
+
+ ExtendedTable++;
+ }
+ }
+ }
+ }
+ }
+ }
+
+ return CorrectMicrocode;
+}
+
+
+/**
+ Check on the processor if SGX is supported.
+
+ @dot
+ digraph G {
+ subgraph cluster_c0 {
+ node [shape = box];
+ b1[label="Read CPUID(EAX=7,ECX=0):EBX[2] \nto check SGX feature" fontsize=12 style=filled color=lightblue];
+ b2[label="Return TRUE" fontsize=12 style=filled color=lightblue];
+ b3[label="Return FALSE" fontsize=12 style=filled color=lightblue];
+
+ node [shape = ellipse];
+ e1[label="Start" fontsize=12 style=filled color=lightblue];
+ e2[label="End" fontsize=12 style=filled color=lightblue];
+
+ node [shape = diamond,style=filled,color=lightblue];
+ d1[label="Are SGX feature supported and \nPRMRR configuration enabled" fontsize=12];
+
+ label = "IsSgxSupported Flow"; fontsize=15; fontcolor=black; color=lightblue;
+ e1 -> b1
+ b1 -> d1
+ d1 -> b2 [label="Yes" fontsize=9]
+ d1 -> b3 [label="No" fontsize=9]
+ b2 -> e2
+ b3 -> e2
+
+ }
+ }
+ @enddot
+
+ @retval TRUE if SGX supported
+ @retval FALSE if SGX is not supported
+**/
+BOOLEAN
+IsSgxSupported (
+ VOID
+ )
+{
+ EFI_CPUID_REGISTER CpuidRegs;
+
+ //
+ // Processor support SGX feature by reading CPUID.(EAX=7,ECX=0):EBX[2]
+ //
+ AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, &CpuidRegs.RegEax,&CpuidRegs.RegEbx,&CpuidRegs.RegEcx,&CpuidRegs.RegEdx);
+
+ ///
+ /// SGX feature is supported only on SKL and later,
+ /// with CPUID.(EAX=7,ECX=0):EBX[2]=1
+ /// PRMRR configuration enabled, MSR IA32_MTRRCAP (FEh) [12] == 1
+ ///
+ if (((CpuidRegs.RegEbx & BIT2)) && (AsmReadMsr64 (MSR_IA32_MTRRCAP) & BIT12)) {
+ return TRUE;
+ }
+ return FALSE;
+}
+
+/**
+ Get processor generation
+
+ @retval EnumSklCpu Executing thread is Skylake
+ @retval EnumKblCpu Executing thread is Kabylake
+**/
+CPU_GENERATION
+GetCpuGeneration (
+ VOID
+ )
+{
+ EFI_CPUID_REGISTER Cpuid;
+ CPU_FAMILY CpuFamilyModel;
+ CPU_STEPPING CpuStepping;
+ CPU_GENERATION CpuGeneration;
+
+ CpuGeneration = EnumSklCpu;
+ ///
+ /// Read the CPUID information
+ ///
+ AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
+ CpuFamilyModel = (CPU_FAMILY) (Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL);
+ CpuStepping = (CPU_STEPPING) (Cpuid.RegEax & CPUID_FULL_STEPPING);
+
+ switch (CpuFamilyModel) {
+ case EnumCpuKblUltUlx:
+ case EnumCpuKblDtHalo:
+ CpuGeneration = EnumKblCpu;
+ break;
+
+ case EnumCpuSklUltUlx:
+ case EnumCpuSklDtHalo:
+ if (((CpuStepping > EnumSklMaxUltUlxStep) && (CpuStepping <= EnumKblMaxUltUlxStep)) ||
+ ((CpuStepping > EnumSklMaxDtHaloStep) && (CpuStepping <= EnumKblMaxDtHaloStep))) {
+ CpuGeneration = EnumKblCpu;
+ }
+ break;
+
+ default:
+ CpuGeneration = EnumSklCpu;
+ break;
+ }
+
+ return CpuGeneration;
+}
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h new file mode 100644 index 0000000000..d5b8ed9ae4 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h @@ -0,0 +1,34 @@ +/** @file
+ Header file for Cpu Platform Lib implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_
+#define _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/CpuLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PciLib.h>
+#include <Library/TimerLib.h>
+#include <Library/SynchronizationLib.h>
+
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <CpuAccess.h>
+#include <Library/CpuPlatformLib.h>
+
+#endif
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf new file mode 100644 index 0000000000..2a123ae708 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf @@ -0,0 +1,50 @@ +## @file
+# Component description file for CPU Platform Lib
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPlatformLib
+FILE_GUID = 11647130-6AA4-41A4-A3A8-5FA296ABD977
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPlatformLib
+
+
+[LibraryClasses]
+BaseLib
+BaseMemoryLib
+DebugLib
+IoLib
+PcdLib
+PciLib
+CpuLib
+TimerLib
+SynchronizationLib
+MmPciLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+
+[Sources]
+CpuPlatformLibrary.h
+CpuPlatformLibrary.c
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/LibraryPrivate/PeiDxeSmmCpuCommonLib/CpuCommonLib.c b/Silicon/Intel/KabylakeSiliconPkg/Cpu/LibraryPrivate/PeiDxeSmmCpuCommonLib/CpuCommonLib.c new file mode 100644 index 0000000000..100bd1464c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/LibraryPrivate/PeiDxeSmmCpuCommonLib/CpuCommonLib.c @@ -0,0 +1,562 @@ +/** @file
+ CPU Common Lib implementation.
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/CpuLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PciLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/CpuMailboxLib.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <CpuAccess.h>
+
+#include <Library/CpuCommonLib.h>
+
+#define INTERRUPT_VECTOR_NUMBER 256
+#define END_OF_TIMETABLE 0x3FF
+
+
+/**
+ Set up flags in CR4 for XMM instruction enabling
+**/
+VOID
+EFIAPI
+XmmInit (
+ VOID
+ )
+{
+ EFI_CPUID_REGISTER Cpuid;
+ UINTN Cr0;
+ UINTN Cr4;
+
+ ///
+ /// Read the CPUID information
+ ///
+ AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
+
+ ///
+ /// Check whether SSE2 is supported
+ ///
+ if (Cpuid.RegEdx & BIT26) {
+ ///
+ /// Enable XMM
+ ///
+ Cr0 = AsmReadCr0 ();
+ Cr0 |= BIT1;
+ AsmWriteCr0 (Cr0);
+
+ Cr4 = AsmReadCr4 ();
+ Cr4 |= (UINTN) (BIT9 | BIT10);
+ AsmWriteCr4 (Cr4);
+ }
+}
+
+/**
+ Enable "Machine Check Enable" bit in Cr4
+**/
+VOID
+EFIAPI
+EnableMce (
+ VOID
+ )
+{
+ UINTN Cr4;
+
+ ///
+ /// Enable MCE
+ ///
+ Cr4 = AsmReadCr4 ();
+ Cr4 |= BIT6;
+ AsmWriteCr4 (Cr4);
+}
+
+/**
+ Mtrr Synch Up Entry
+**/
+UINTN
+EFIAPI
+MpMtrrSynchUpEntry (
+ VOID
+ )
+{
+ EFI_CPUID_REGISTER Cpuid;
+ UINT64 MsrData;
+ UINTN Cr0;
+ UINTN Cr4;
+
+ ///
+ /// Read the CPUID and MSR 1Bh information
+ ///
+ AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
+ MsrData = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+
+ ///
+ /// Set CD(Bit30) bit and clear NW(Bit29) bit of CR0 followed by a WBINVD.
+ ///
+ if (!(Cpuid.RegEdx & BIT24) || (MsrData & BIT8)) {
+ AsmDisableCache ();
+ } else {
+ ///
+ /// We could bypass the wbinvd by
+ /// checking MSR 1Bh(MSR_IA32_APIC_BASE) Bit8 (1 = BSP, 0 = AP) to see if we're the BSP?
+ /// and checking CPUID if the processor support self-snooping.
+ ///
+ Cr0 = AsmReadCr0 ();
+ Cr0 &= (UINTN) ~BIT29;
+ Cr0 |= BIT30;
+ AsmWriteCr0 (Cr0);
+ }
+
+ ///
+ /// Clear PGE flag Bit 7
+ ///
+ Cr4 = AsmReadCr4 ();
+ Cr4 &= (UINTN) ~BIT7;
+ AsmWriteCr4 (Cr4);
+
+ ///
+ /// Flush all TLBs
+ ///
+ CpuFlushTlb ();
+
+ return Cr4;
+}
+
+/**
+ Mtrr Synch Up Exit
+**/
+VOID
+EFIAPI
+MpMtrrSynchUpExit (
+ UINTN Cr4
+ )
+{
+ UINTN Cr0;
+
+ ///
+ /// Flush all TLBs the second time
+ ///
+ CpuFlushTlb ();
+
+ ///
+ /// Clear both the CD and NW bits of CR0.
+ ///
+ Cr0 = AsmReadCr0 ();
+ Cr0 &= (UINTN) ~(BIT29 | BIT30);
+ AsmWriteCr0 (Cr0);
+
+ ///
+ /// Set PGE Flag in CR4 if set
+ ///
+ AsmWriteCr4 (Cr4);
+}
+
+/**
+ This procedure sends an IPI to the designated processor in
+ the requested delivery mode with the requested vector.
+
+ @param[in] ApicID - APIC ID of processor.
+ @param[in] VectorNumber - Vector number.
+ @param[in] DeliveryMode - I/O APIC Interrupt Deliver Modes
+
+ @retval EFI_INVALID_PARAMETER - Input paramters were not correct.
+ @retval EFI_NOT_READY - There was a pending interrupt
+ @retval EFI_SUCCESS - Interrupt sent successfully
+**/
+EFI_STATUS
+EFIAPI
+CpuSendIpi (
+ IN UINT32 ApicID,
+ IN UINTN VectorNumber,
+ IN UINTN DeliveryMode
+ )
+{
+ MSR_IA32_APIC_BASE_REGISTER Msr;
+ EFI_PHYSICAL_ADDRESS ApicBase;
+ UINT32 IcrLow;
+ UINT32 IcrHigh;
+ BOOLEAN XapicEnabled;
+ UINT32 TriggerMode;
+
+ ///
+ /// Check for valid input parameters.
+ ///
+ if (VectorNumber >= INTERRUPT_VECTOR_NUMBER) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (DeliveryMode >= DELIVERY_MODE_MAX) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ///
+ /// Fix the vector number for special interrupts like SMI and INIT.
+ ///
+ if (DeliveryMode == DELIVERY_MODE_SMI || DeliveryMode == DELIVERY_MODE_INIT) {
+ VectorNumber = 0x0;
+ }
+
+ ///
+ /// Initialze ICR high dword, since P6 family processor needs
+ /// the destination field to be 0x0F when it is a broadcast
+ ///
+ IcrHigh = 0x0f000000;
+ IcrLow = (UINT32) (VectorNumber | (LShiftU64 (DeliveryMode, 8)));
+
+ TriggerMode = TRIGGER_MODE_EDGE;
+
+ ///
+ /// Interrupt trigger mode
+ ///
+ if (TriggerMode == TRIGGER_MODE_LEVEL) {
+ IcrLow |= 0x8000;
+ }
+
+ ///
+ /// Interrupt pin polarity
+ ///
+ IcrLow |= 0x4000;
+
+ ///
+ /// xAPIC Enabled
+ ///
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ XapicEnabled = (BOOLEAN) ((Msr.Bits.EXTD == 1) && (Msr.Bits.EN == 1));
+
+ if (XapicEnabled) {
+ IcrHigh = (UINT32) ApicID;
+ } else {
+ IcrHigh = (UINT32) LShiftU64 (ApicID, 24);
+ }
+
+ ApicBase = Msr.Uint64 & 0xffffff000;
+
+ /* If Extended XAPIC Mode is enabled,
+ legacy xAPIC is no longer working.
+ So, previous MMIO offset must be transferred to MSR offset R/W.
+ ----------------------------------------------------------------
+ MMIO Offset MSR Offset Register Name
+ ----------------------------------------------------------------
+ 300h-310h 830h Interrupt Command Register [63:0]
+ 831h [Reserved]
+ ----------------------------------------------------------------
+ */
+ ///
+ /// To write APIC register by MSR or MMIO
+ ///
+ if (XapicEnabled) {
+ AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, (((UINT64) LShiftU64 (IcrHigh, 32)) | (UINT64) IcrLow));
+ } else {
+ *(volatile UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_ICR_HIGH_OFFSET) = (UINT32) IcrHigh;
+ *(volatile UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_ICR_LOW_OFFSET) = (UINT32) IcrLow;
+ }
+
+ MicroSecondDelay (10);
+
+ ///
+ /// To get APIC register from MSR or MMIO
+ ///
+ if (XapicEnabled) {
+ IcrLow = (UINT32) AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
+ } else {
+ IcrLow = (UINT32) *(volatile UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_ICR_LOW_OFFSET);
+ }
+
+ if (IcrLow & BIT12) {
+ return EFI_NOT_READY;
+ }
+
+ MicroSecondDelay (100);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Get APIC ID of processor
+
+ @retval APIC ID of processor
+**/
+UINT32
+GetCpuApicId (
+ VOID
+ )
+{
+ EFI_CPUID_REGISTER CpuidRegisters;
+
+ AsmCpuid (
+ CPUID_VERSION_INFO,
+ &CpuidRegisters.RegEax,
+ &CpuidRegisters.RegEbx,
+ &CpuidRegisters.RegEcx,
+ &CpuidRegisters.RegEdx
+ );
+ return (UINT32) (CpuidRegisters.RegEbx >> 24);
+}
+
+/**
+ Programs XAPIC registers.
+
+ @param[in] Bsp - Is this BSP?
+**/
+VOID
+ProgramXApic (
+ BOOLEAN Bsp
+ )
+{
+ UINT64 ApicBaseReg;
+ EFI_PHYSICAL_ADDRESS ApicBase;
+ volatile UINT32 *EntryAddress;
+ UINT32 EntryValue;
+
+ ApicBaseReg = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBase = ApicBaseReg & 0xffffff000ULL;
+
+ ///
+ /// Program the spurious vector entry
+ ///
+ EntryAddress = (UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_SPURIOUS_VECTOR_OFFSET);
+ EntryValue = *EntryAddress;
+ EntryValue &= 0xFFFFFD0F;
+ EntryValue |= 0x10F;
+ *EntryAddress = EntryValue;
+
+ ///
+ /// Program the LINT1 vector entry as extINT
+ ///
+ EntryAddress = (UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_LINT0_VECTOR_OFFSET);
+ EntryValue = *EntryAddress;
+
+ if (Bsp) {
+ EntryValue &= 0xFFFE00FF;
+ EntryValue |= 0x700;
+ } else {
+ EntryValue |= 0x10000;
+ }
+
+ *EntryAddress = EntryValue;
+
+ ///
+ /// Program the LINT1 vector entry as NMI
+ ///
+ EntryAddress = (UINT32 *) (UINTN) (ApicBase + APIC_REGISTER_LINT1_VECTOR_OFFSET);
+ EntryValue = *EntryAddress;
+ EntryValue &= 0xFFFE00FF;
+ if (Bsp) {
+ EntryValue |= 0x400;
+ } else {
+ EntryValue |= 0x10400;
+ }
+
+ *EntryAddress = EntryValue;
+}
+
+/**
+ This function is to disable BIOS Write Protect in SMM phase.
+**/
+VOID
+EFIAPI
+CpuSmmDisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT32 Data32;
+
+ ///
+ /// Read memory location FED30880h OR with 00000001h, place the result in EAX,
+ /// and write data to lower 32 bits of MSR 1FEh (sample code available)
+ ///
+ Data32 = MmioRead32 ((UINTN) (0xFED30880)) | (UINT32) (BIT0);
+ AsmWriteMsr32 (0x000001FE, Data32);
+}
+
+/**
+ This function is to enable BIOS Write Protect in SMM phase.
+**/
+VOID
+EFIAPI
+CpuSmmEnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT32 Data32;
+
+ ///
+ /// Read memory location FED30880h AND with FFFFFFFEh, place the result in EAX,
+ /// and write data to lower 32 bits of MSR 1FEh (sample code available)
+ ///
+ Data32 = MmioRead32 ((UINTN) (0xFED30880)) & (UINT32) (~BIT0);
+ AsmWriteMsr32 (0x000001FE, Data32);
+}
+
+/**
+ This function returns the maximum number of cores supported in this physical processor package.
+
+ @retval Maximum number of supported cores in the package.
+**/
+UINT8
+GetMaxSupportedCoreCount (
+ VOID
+ )
+{
+ EFI_CPUID_REGISTER Cpuid;
+ AsmCpuidEx (
+ 4,
+ 0,
+ &Cpuid.RegEax,
+ NULL,
+ NULL,
+ NULL
+ );
+ return (UINT8) (RShiftU64 (Cpuid.RegEax, 26) & 0x3f) + 1;
+}
+
+/**
+ This function returns the actual factory-configured number of threads per core,
+ and actual factory-configured number of cores in this physical processor package.
+
+ @param[out] *ThreadsPerCore - variable that will store Maximum enabled threads per core
+ @param[out] *NumberOfCores - variable that will store Maximum enabled cores per die
+**/
+VOID
+GetSupportedCount (
+ OUT UINT16 *ThreadsPerCore, OPTIONAL
+ OUT UINT16 *NumberOfCores OPTIONAL
+ )
+{
+ EFI_CPUID_REGISTER CpuidRegs;
+ UINT16 Threads;
+
+ AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, &CpuidRegs.RegEbx, NULL, NULL);
+ Threads = (UINT16) CpuidRegs.RegEbx;
+
+ if (ThreadsPerCore != NULL) {
+ *ThreadsPerCore = Threads;
+ }
+
+ if (NumberOfCores != NULL) {
+ AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, NULL, &CpuidRegs.RegEbx, NULL, NULL);
+ *NumberOfCores = (UINT16) (CpuidRegs.RegEbx / Threads);
+ }
+}
+
+
+/**
+ Check to see if the executing thread is BSP
+
+ @retval TRUE Executing thread is BSP
+ @retval FALSE Executing thread is AP
+**/
+BOOLEAN
+IsBsp (
+ VOID
+ )
+{
+ MSR_IA32_APIC_BASE_REGISTER Msr;
+
+ Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ return (BOOLEAN) (Msr.Bits.BSP == 1);
+}
+
+
+BOOLEAN
+IsPrmrrAlreadySet (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Check if this is non-core processor - HT AP thread
+
+ @retval TRUE if this is HT AP thread
+ @retval FALSE if this is core thread
+**/
+BOOLEAN
+IsSecondaryThread (
+ VOID
+ )
+{
+ UINT32 ApicID;
+ EFI_CPUID_REGISTER CpuidRegisters;
+ UINT8 CpuCount;
+ UINT8 CoreCount;
+ UINT8 CpuPerCore;
+ UINT32 Mask;
+
+ ApicID = GetCpuApicId ();
+
+ AsmCpuid (
+ CPUID_VERSION_INFO,
+ &CpuidRegisters.RegEax,
+ &CpuidRegisters.RegEbx,
+ &CpuidRegisters.RegEcx,
+ &CpuidRegisters.RegEdx
+ );
+ if ((CpuidRegisters.RegEdx & 0x10000000) == 0) {
+ return FALSE;
+ }
+
+ CpuCount = (UINT8) ((CpuidRegisters.RegEbx >> 16) & 0xff);
+ if (CpuCount == 1) {
+ return FALSE;
+ }
+
+ AsmCpuid (
+ CPUID_SIGNATURE,
+ &CpuidRegisters.RegEax,
+ &CpuidRegisters.RegEbx,
+ &CpuidRegisters.RegEcx,
+ &CpuidRegisters.RegEdx
+ );
+ if (CpuidRegisters.RegEax > 3) {
+
+ CoreCount = GetMaxSupportedCoreCount ();
+ } else {
+ CoreCount = 1;
+ }
+ ///
+ /// Assumes there is symmetry across core boundary, i.e. each core within a package has the same number of logical processors
+ ///
+ if (CpuCount == CoreCount) {
+ return FALSE;
+ }
+
+ CpuPerCore = CpuCount / CoreCount;
+
+ ///
+ /// Assume 1 Core has no more than 8 threads
+ ///
+ if (CpuPerCore == 2) {
+ Mask = 0x1;
+ } else if (CpuPerCore <= 4) {
+ Mask = 0x3;
+ } else {
+ Mask = 0x7;
+ }
+
+ if ((ApicID & Mask) == 0) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+}
+
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/LibraryPrivate/PeiDxeSmmCpuCommonLib/PeiDxeSmmCpuCommonLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Cpu/LibraryPrivate/PeiDxeSmmCpuCommonLib/PeiDxeSmmCpuCommonLib.inf new file mode 100644 index 0000000000..70d33ce354 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/LibraryPrivate/PeiDxeSmmCpuCommonLib/PeiDxeSmmCpuCommonLib.inf @@ -0,0 +1,49 @@ +## @file
+# Component description file for CPU Common Lib
+#
+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuCommonLib
+FILE_GUID = B4E0E3E8-DCE9-46FE-9670-03FDD2F08D6C
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuCommonLib
+
+
+[LibraryClasses]
+BaseLib
+BaseMemoryLib
+DebugLib
+IoLib
+PcdLib
+PciLib
+CpuLib
+TimerLib
+SynchronizationLib
+TimerLib
+CpuPlatformLib
+CpuMailboxLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+KabylakeSiliconPkg/SiPkg.dec
+KabylakeSiliconPkg/KabylakeSiliconPrivate.dec
+
+
+[Sources]
+CpuCommonLib.c
+
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