1 files changed, 54 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h
new file mode 100644
index 0000000000..b55aaa705a
--- /dev/null
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h
@@ -0,0 +1,54 @@
+/** @file
+  FlashProtection policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _FLASH_PROTECTION_CONFIG_H_
+#define _FLASH_PROTECTION_CONFIG_H_
+
+#define FLASH_PROTECTION_CONFIG_REVISION 1
+extern EFI_GUID gFlashProtectionConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+  The PCH provides a method for blocking writes and reads to specific ranges
+  in the SPI flash when the Protected Ranges are enabled.
+  PROTECTED_RANGE is used to specify if flash protection are enabled,
+  the write protection enable bit and the read protection enable bit,
+  and to specify the upper limit and lower base for each register
+  Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
+  and set the limit and base accordingly.
+**/
+typedef struct {
+  UINT32                WriteProtectionEnable     :  1;     ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+  UINT32                ReadProtectionEnable      :  1;     ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+  UINT32                RsvdBits                  :  30;    ///< Reserved
+  /**
+    The address of the upper limit of protection
+    This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
+  **/
+  UINT16                ProtectedRangeLimit;
+  /**
+    The address of the upper limit of protection
+    This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
+  **/
+  UINT16                ProtectedRangeBase;
+} PROTECTED_RANGE;
+
+typedef struct {
+  CONFIG_BLOCK_HEADER   Header;                   ///< Config Block Header
+  PROTECTED_RANGE       ProtectRange[PCH_FLASH_PROTECTED_RANGES];
+} PCH_FLASH_PROTECTION_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FLASH_PROTECTION_CONFIG_H_