diff options
Diffstat (limited to 'Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock')
31 files changed, 2742 insertions, 0 deletions
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Cio2Config.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Cio2Config.h new file mode 100644 index 0000000000..187d4cd506 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Cio2Config.h @@ -0,0 +1,72 @@ +/** @file
+ CIO2 policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _CIO2_CONFIG_H_
+#define _CIO2_CONFIG_H_
+
+#define CIO2_CONFIG_REVISION 1
+extern EFI_GUID gCio2ConfigGuid;
+
+#pragma pack (push,1)
+
+///
+/// The PCH_SKYCAM_CIO2_CONFIG block describes SkyCam CIO2 device.
+///
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ NOTE: For SKL PCH, while CIO2 is enabled,
+ RC will configure CIO2 controller as ACPI mode when PCH stepping < C0, and configure to PCI mode for C0 onwards.
+ **/
+ UINT32 DeviceEnable : 2; ///< 0: Disabled, <b>1: Enabled</b>
+
+ UINT32 SkyCamPortATermOvrEnable : 1; ///< <b>0: Disable</b>, 1: Enable - Termination override on port A
+ UINT32 SkyCamPortBTermOvrEnable : 1; ///< <b>0: Disable</b>, 1: Enable - Termination override on port B
+ UINT32 SkyCamPortCTermOvrEnable : 1; ///< <b>0: Disable</b>, 1: Enable - Termination override on port C
+ UINT32 SkyCamPortDTermOvrEnable : 1; ///< <b>0: Disable</b>, 1: Enable - Termination override on port D
+ UINT32 RsvdBits : 26;
+
+ //
+ // CIO2 FLS registers configuration.
+ //
+
+ UINT32 PortATrimEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port A Clk Trim
+ UINT32 PortBTrimEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port B Clk Trim
+ UINT32 PortCTrimEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port C Clk Trim
+ UINT32 PortDTrimEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port D Clk Trim
+ UINT32 PortACtleEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port A Ctle
+ UINT32 PortBCtleEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port B Ctle
+ UINT32 PortCDCtleEnable : 1; ///< 0: Disable, <b>1: Enable</b> - Port C/D Ctle
+ UINT32 RsvdBits0 : 25;
+
+ UINT32 PortACtleCapValue : 4; /// Port A Ctle Cap Value. Default is <b>0xE</b>
+ UINT32 PortBCtleCapValue : 4; /// Port B Ctle Cap Value. Default is <b>0xE</b>
+ UINT32 PortCDCtleCapValue : 4; /// Port C/D Ctle Cap Value. Default is <b>0xE</b>
+ UINT32 PortACtleResValue : 5; /// Port A Ctle Res Value. Default is <b>0xD</b>
+ UINT32 PortBCtleResValue : 5; /// Port B Ctle Res Value. Default is <b>0xD</b>
+ UINT32 PortCDCtleResValue : 5; /// Port C/D Ctle Res Value. Default is <b>0xD</b>
+ UINT32 RsvdBits1 : 5;
+
+ UINT32 PortAClkTrimValue : 4; /// Port A Clk Trim Value. Default is <b>0xA</b>
+ UINT32 PortBClkTrimValue : 4; /// Port B Clk Trim Value. Default is <b>0xA</b>
+ UINT32 PortCClkTrimValue : 4; /// Port C Clk Trim Value. Default is <b>0x9</b>
+ UINT32 PortDClkTrimValue : 4; /// Port D Clk Trim Value. Default is <b>0xA</b>
+ UINT32 PortADataTrimValue : 16; /// Port A Data Trim Value. Default is <b>0xBBBB</b>
+ UINT32 PortBDataTrimValue : 16; /// Port B Data Trim Value. Default is <b>0xBBBB</b>
+ UINT32 PortCDDataTrimValue : 16; /// Port C/D Data Trim Value. Default is <b>0xCCCC</b>
+
+} PCH_CIO2_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CIO2_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h new file mode 100644 index 0000000000..aba0677abc --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h @@ -0,0 +1,53 @@ +/** @file
+ Dci policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _DCI_CONFIG_H_
+#define _DCI_CONFIG_H_
+
+#define DCI_PREMEM_CONFIG_REVISION 2
+extern EFI_GUID gDciPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to Direct Connection Interface (DCI).
+
+ <b>Revision 1:</b>
+ - Inital version.
+ <b>Revision 2:</b>
+ - Deprecate DciAutoDetect
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ DCI enable (HDCIEN bit)
+ when Enabled, allow DCI to be enabled. When Disabled, the host control is not enabling DCI feature.
+ BIOS provides policy to enable or disable DCI, and user would be able to use BIOS option to change this policy.
+ The user changing the setting from disable to enable, is taken as a consent from the user to enable this DCI feature.
+ <b>0:Disabled</b>; 1:Enabled
+ **/
+ UINT32 DciEn : 1;
+ /**
+ @deprecated from revision 2.
+ <b>(Test)</b> When set to Auto detect mode, it detects CCA being connected during BIOS post time.
+ This policy only applies when DciEn is disabled.
+ NOTE: this policy should not be visible to end customer.
+ 0: Disable AUTO mode, <b>1: Enable AUTO mode</b>
+ **/
+ UINT32 DciAutoDetect : 1;
+ UINT32 RsvdBits : 30; ///< Reserved bits
+} PCH_DCI_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _DCI_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h new file mode 100644 index 0000000000..2fd5d1b171 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h @@ -0,0 +1,53 @@ +/** @file
+ DMI policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _DMI_CONFIG_H_
+#define _DMI_CONFIG_H_
+
+#define DMI_CONFIG_REVISION 2
+extern EFI_GUID gDmiConfigGuid;
+
+
+#pragma pack (push,1)
+
+
+/**
+ The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Add LegacyIoLowLatency support.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ 0: Disable; <b>1: Enable</b> ASPM on PCH side of the DMI Link.
+ While DmiAspm is enabled, DMI ASPM will be set to Intel recommended value.
+ **/
+ UINT32 DmiAspm : 1;
+ UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
+ /**
+ Set to enable low latenc of legacy IO.
+ Some systems require lower IO latency irrespective of power.
+ This is a tradeoff between power and IO latency.
+ @note: Once this is enabled, DmiAspm is forced to disabled and so do Pcie DmiAspm in SystemAgent.
+ <b>0:Disable</b>, 1:Enable
+ **/
+ UINT32 LegacyIoLowLatency : 1;
+ UINT32 Rsvdbits : 29; ///< Reserved bits
+} PCH_DMI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _DMI_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h new file mode 100644 index 0000000000..c952bf9f31 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h @@ -0,0 +1,41 @@ +/** @file
+ Espi policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _ESPI_CONFIG_H_
+#define _ESPI_CONFIG_H_
+
+#define ESPI_CONFIG_REVISION 1
+extern EFI_GUID gEspiConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to ESPI.
+
+ <b>Revision 1</b>:
+ - Initial version. Add BmeMasterSlaveEnabled support.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ eSPI Master and Slave BME settings.
+ When TRUE, then the BME bit enabled in eSPI Master and Slave.
+ 0: FALSE, <b>1: TRUE </b>
+ **/
+ UINT32 BmeMasterSlaveEnabled : 1;
+ UINT32 RsvdBits : 31; ///< Reserved bits
+} PCH_ESPI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _ESPI_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h new file mode 100644 index 0000000000..b55aaa705a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h @@ -0,0 +1,54 @@ +/** @file
+ FlashProtection policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _FLASH_PROTECTION_CONFIG_H_
+#define _FLASH_PROTECTION_CONFIG_H_
+
+#define FLASH_PROTECTION_CONFIG_REVISION 1
+extern EFI_GUID gFlashProtectionConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH provides a method for blocking writes and reads to specific ranges
+ in the SPI flash when the Protected Ranges are enabled.
+ PROTECTED_RANGE is used to specify if flash protection are enabled,
+ the write protection enable bit and the read protection enable bit,
+ and to specify the upper limit and lower base for each register
+ Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
+ and set the limit and base accordingly.
+**/
+typedef struct {
+ UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 30; ///< Reserved
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
+ **/
+ UINT16 ProtectedRangeLimit;
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
+ **/
+ UINT16 ProtectedRangeBase;
+} PROTECTED_RANGE;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES];
+} PCH_FLASH_PROTECTION_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FLASH_PROTECTION_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h new file mode 100644 index 0000000000..a0ebbbd84d --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h @@ -0,0 +1,180 @@ +/** @file
+ HDAUDIO policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _HDAUDIO_CONFIG_H_
+#define _HDAUDIO_CONFIG_H_
+
+#define HDAUDIO_CONFIG_REVISION 2
+extern EFI_GUID gHdAudioConfigGuid;
+
+#pragma pack (push,1)
+
+///
+/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of the Intel HD Audio feature.
+///
+#define PCH_HDAUDIO_AUTO 2
+
+#define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) (UINT32)((UINT16)Vid | ((UINT16)Did << 16))
+#define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) (UINT32)((UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16))
+#define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof (VerbTable) - sizeof (PCH_HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32)))
+
+///
+/// Use this macro to create HDAUDIO_VERB_TABLE and populate size automatically
+///
+#define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \
+{ \
+ { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }, \
+ { __VA_ARGS__ } \
+}
+
+/**
+ Azalia verb table header
+ Every verb table should contain this defined header and followed by azalia verb commands.
+**/
+typedef struct {
+ UINT16 VendorId; ///< Codec Vendor ID
+ UINT16 DeviceId; ///< Codec Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs following the header.
+} PCH_HDA_VERB_TABLE_HEADER;
+
+#ifdef _MSC_VER
+//
+// Disable "zero-sized array in struct/union" extension warning.
+// Used for neater verb table definitions.
+//
+#pragma warning (push)
+#pragma warning (disable: 4200)
+#endif
+typedef struct {
+ PCH_HDA_VERB_TABLE_HEADER Header;
+ UINT32 Data[];
+} HDAUDIO_VERB_TABLE;
+#ifdef _MSC_VER
+#pragma warning (pop)
+#endif
+
+enum PCH_HDAUDIO_IO_BUFFER_OWNERSHIP {
+ PchHdaIoBufOwnerHdaLink = 0, ///< HD-Audio link owns all the I/O buffers.
+ PchHdaIoBufOwnerHdaLinkI2sPort = 1, ///< HD-Audio link owns 4 and I2S port owns 4 of the I/O buffers.
+ PchHdaIoBufOwnerI2sPort = 3 ///< I2S0 and I2S1 ports own all the I/O buffers.
+};
+
+enum PCH_HDAUDIO_IO_BUFFER_VOLTAGE {
+ PchHdaIoBuf33V = 0,
+ PchHdaIoBuf18V = 1
+};
+
+enum PCH_HDAUDIO_VC_TYPE {
+ PchHdaVc0 = 0,
+ PchHdaVc1 = 1
+};
+
+enum PCH_HDAUDIO_DMIC_TYPE {
+ PchHdaDmicDisabled = 0,
+ PchHdaDmic2chArray = 1,
+ PchHdaDmic4chArray = 2,
+ PchHdaDmic1chArray = 3
+};
+
+typedef enum {
+ PchHdaLinkFreq6MHz = 0,
+ PchHdaLinkFreq12MHz = 1,
+ PchHdaLinkFreq24MHz = 2,
+ PchHdaLinkFreq48MHz = 3,
+ PchHdaLinkFreq96MHz = 4,
+ PchHdaLinkFreqInvalid
+} PCH_HDAUDIO_LINK_FREQUENCY;
+
+typedef enum {
+ PchHdaIDispMode2T = 0,
+ PchHdaIDispMode1T = 1
+} PCH_HDAUDIO_IDISP_TMODE;
+
+/**
+ This structure contains the policies which are related to HD Audio device (cAVS).
+
+ <b>Revision 1:</b>
+ - Inital version.
+ <b>Revision 2:</b>
+ - Deprecate DspPpModuleMask: Pre/Post-processing modules (3rd Party IP) support moved to Platform Package.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ This member describes whether or not Intel HD Audio (Azalia) should be enabled.
+ If enabled (in Auto mode) and no codec exists the reference code will automatically disable
+ the HD Audio device.
+ 0: Disable, 1: Enable, <b>2: Auto (enabled if codec detected and initialized, disabled otherwise)</b>
+ **/
+ UINT32 Enable : 2;
+ UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
+ UINT32 Pme : 1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable
+ UINT32 IoBufferOwnership : 2; ///< I/O Buffer Ownership Select: <b>0: HD-A Link</b>; 1: Shared, HD-A Link and I2S Port; 3: I2S Ports
+ UINT32 IoBufferVoltage : 1; ///< I/O Buffer Voltage Mode Select: <b>0: 3.3V</b>; 1: 1.8V
+ UINT32 VcType : 1; ///< Virtual Channel Type Select: <b>0: VC0</b>, 1: VC1
+ UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>2: 24MHz</b>, 1: 12MHz, 0: 6MHz
+ UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HDAUDIO_LINK_FREQUENCY enum): <b>4: 96MHz</b>, 3: 48MHz
+ UINT32 IDispLinkTmode : 1; ///< iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): <b>0: 2T</b>, 1: 1T
+ /**
+ Universal Audio Architecture compliance for DSP enabled system:
+ <b>0: Not-UAA Compliant (Intel SST driver supported only)</b>,
+ 1: UAA Compliant (HDA Inbox driver or SST driver supported)
+ **/
+ UINT32 DspUaaCompliance : 1;
+ UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconnection, <b>0: Not disconnected, enumerable</b>; 1: Disconnected SDI, not enumerable
+ UINT32 RsvdBits0 : 13; ///< Reserved bits 1
+ /**
+ Bitmask of supported DSP endpoint configuration exposed via NHLT ACPI table:
+ **/
+ UINT32 DspEndpointDmic : 2; ///< DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum): 0: Disable; 1: 2ch array; <b>2: 4ch array</b>; 3: 1ch array
+ UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: <b>0: Disable</b>; 1: Enable
+ UINT32 DspEndpointI2s : 1; ///< I2S enablement: <b>0: Disable</b>; 1: Enable
+ UINT32 RsvdBits1 : 28; ///< Reserved bits 2
+ /**
+ Bitmask of supported DSP features:
+ [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6] - BT Intel A2DP
+ [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel WoV, 1: Windows Voice Activation
+ Default is <b>zero</b>.
+ **/
+ UINT32 DspFeatureMask;
+ /**
+ @deprecated from revision 2.
+ Bitmask of supported DSP Pre/Post-Processing Modules.
+ Specific pre/post-processing module bit position must be coherent with the ACPI implementation:
+ \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing Module Support.
+ DspPpModuleMask is passed to ACPI as 'ADPM' NVS variable
+ Default is <b>zero</b>.
+ **/
+ UINT32 DspPpModuleMask;
+ UINT16 ResetWaitTimer; ///< <b>(Test)</b> The delay timer after Azalia reset, the value is number of microseconds. Default is <b>600</b>.
+ UINT8 Rsvd0; ///< Reserved bytes, align to multiple 4
+ /**
+ Number of the verb table entry defined in VerbTablePtr.
+ Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
+ **/
+ UINT8 VerbTableEntryNum;
+ /**
+ Pointer to a verb table array.
+ This pointer points to 32bits address, and is only eligible and consumed in post mem phase.
+ Each entry points to a verb table which contains HDAUDIO_VERB_TABLE structure and verb command blocks.
+ The prototype of this is:
+ HDAUDIO_VERB_TABLE **VerbTablePtr;
+ **/
+ UINT32 VerbTablePtr;
+} PCH_HDAUDIO_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HDAUDIO_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HpetConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HpetConfig.h new file mode 100644 index 0000000000..30928e5d08 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HpetConfig.h @@ -0,0 +1,47 @@ +/** @file
+ HPET policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _HPET_CONFIG_H_
+#define _HPET_CONFIG_H_
+
+#define HPET_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gHpetPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_HPET_CONFIG block passes the bus/device/function value for HPET.
+ The address resource range of HPET must be reserved in E820 and ACPI as
+ system resource.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Determines if enable HPET timer. 0: Disable; <b>1: Enable</b>.
+ The HPET timer address decode is always enabled.
+ This policy is used to configure the HPET timer count, and also the _STA of HPET device in ACPI.
+ While enabled, the HPET timer is started, else the HPET timer is halted.
+ **/
+ UINT32 Enable : 1;
+ UINT32 BdfValid : 1; ///< Whether the BDF value is valid. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits0 : 6; ///< Reserved bits
+ UINT32 BusNumber : 8; ///< Bus Number HPETn used as Requestor / Completer ID. Default is <b>0xF0</b>.
+ UINT32 DeviceNumber : 5; ///< Device Number HPETn used as Requestor / Completer ID. Default is <b>0x1F</b>.
+ UINT32 FunctionNumber : 3; ///< Function Number HPETn used as Requestor / Completer ID. Default is <b>0x00</b>.
+ UINT32 RsvdBits1 : 8; ///< Reserved bits
+ UINT32 Base; ///< The HPET base address. Default is <b>0xFED00000</b>.
+} PCH_HPET_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HPET_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h new file mode 100644 index 0000000000..e4973fc25e --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h @@ -0,0 +1,45 @@ +/** @file
+ HSIO policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _HSIO_CONFIG_H_
+#define _HSIO_CONFIG_H_
+
+#define HSIO_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gHsioPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ /**
+ <b>(Test)</b>
+ 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI message from being sent
+ <b>1- Enable</b> ChipsetInit HECI message
+ **/
+ UINT32 ChipsetInitMessage : 1;
+ /**
+ <b>(Test)</b>
+ <b>0- Disable</b>
+ 1- Enable When eanbled, this is used to bypass the reset after ChipsetInit HECI message.
+ **/
+ UINT32 BypassPhySyncReset : 1;
+ UINT32 RsvdBits : 30;
+} PCH_HSIO_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HSIO_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h new file mode 100644 index 0000000000..cf7bd6251a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h @@ -0,0 +1,76 @@ +/** @file
+ HSIO pcie policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _HSIO_PCIE_CONFIG_H_
+#define _HSIO_PCIE_CONFIG_H_
+
+#define HSIO_PCIE_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gHsioPciePreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane
+**/
+typedef struct {
+ //
+ // HSIO Rx Eq
+ // Refer to the EDS for recommended values.
+ // Note that these setting are per-lane and not per-port
+ //
+ UINT32 HsioRxSetCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 Set CTLE Value
+ UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set CTLE Value
+ UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value
+ UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value
+ UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value
+ UINT32 RsvdBits0 : 4; ///< Reserved Bits
+
+ UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting
+ UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting
+ UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting
+ UINT32 RsvdBits1 : 11; ///< Reserved Bits
+} PCH_HSIO_PCIE_LANE_CONFIG;
+
+/**
+ The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Add PciePllSsc support.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of HSIO for PCIe lanes.
+ ///
+ PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS];
+ /**
+ Specifies the Pcie Pll Spread Spectrum Percentage
+ The value of this policy is in 1/10th percent units.
+ Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
+ A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
+ The default is <b>0xFF: AUTO - No BIOS override</b>.
+ **/
+ UINT8 PciePllSsc;
+ UINT8 Reserved[3];
+} PCH_HSIO_PCIE_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HSIO_PCIE_LANE_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h new file mode 100644 index 0000000000..53c1a01a17 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h @@ -0,0 +1,71 @@ +/** @file
+ Hsio Sata policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _HSIO_SATA_CONFIG_H_
+#define _HSIO_SATA_CONFIG_H_
+
+#define HSIO_SATA_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gHsioSataPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane
+**/
+typedef struct {
+ //
+ // HSIO Rx Eq
+ //
+ UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
+ UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value
+ UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
+ UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
+ UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
+ UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
+ //
+ // HSIO Tx Eq
+ //
+ UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+ UINT32 RsvdBits0 : 4; ///< Reserved bits
+
+ UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment
+ UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment
+ UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+
+ UINT32 HsioTxGen2DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+ UINT32 RsvdBits1 : 4; ///< Reserved bits
+
+ UINT32 HsioTxGen3DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ UINT32 RsvdBits2 : 25; ///< Reserved bits
+} PCH_HSIO_SATA_PORT_LANE;
+
+///
+/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.
+///
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of HSIO for SATA lanes.
+ ///
+ PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS];
+} PCH_HSIO_SATA_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HSIO_SATA_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.h new file mode 100644 index 0000000000..3b8e247a31 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig.h @@ -0,0 +1,63 @@ +/** @file
+ Interrupt policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _INTERRUPT_CONFIG_H_
+#define _INTERRUPT_CONFIG_H_
+
+#define INTERRUPT_CONFIG_REVISION 1
+extern EFI_GUID gInterruptConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// --------------------- Interrupts Config ------------------------------
+//
+typedef enum {
+ PchNoInt, ///< No Interrupt Pin
+ PchIntA,
+ PchIntB,
+ PchIntC,
+ PchIntD
+} PCH_INT_PIN;
+
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} PCH_DEVICE_INTERRUPT_CONFIG;
+
+#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
+#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC registers in ITSS
+
+///
+/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.
+///
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT8 NumOfDevIntConfig; ///< Number of entries in DevIntConfig table
+ UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
+ PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
+ UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; ///< Array which stores interrupt routing for 8259 controller
+ UINT8 GpioIrqRoute; ///< Interrupt routing for GPIO. Default is <b>14</b>.
+ UINT8 SciIrqSelect; ///< Interrupt select for SCI. Default is <b>9</b>.
+ UINT8 TcoIrqSelect; ///< Interrupt select for TCO. Default is <b>9</b>.
+ UINT8 TcoIrqEnable; ///< Enable IRQ generation for TCO. <b>0: Disable</b>; 1: Enable.
+} PCH_INTERRUPT_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _INTERRUPT_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h new file mode 100644 index 0000000000..c96e3a3a04 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h @@ -0,0 +1,61 @@ +/** @file
+ IoApic policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _IOAPIC_CONFIG_H_
+#define _IOAPIC_CONFIG_H_
+
+#define IOAPIC_CONFIG_REVISION 1
+extern EFI_GUID gIoApicConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_IOAPIC_CONFIG block describes the expected configuration of the PCH
+ IO APIC, it's optional and PCH code would ignore it if the BdfValid bit is
+ not TRUE. Bus:device:function fields will be programmed to the register
+ P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpose:
+ As the Requester ID when initiating Interrupt Messages to the processor.
+ As the Completer ID when responding to the reads targeting the IOxAPI's
+ Memory-Mapped I/O registers.
+ This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can
+ program this field to provide a unique Bus:Device:Function number for the
+ internal IOxAPIC.
+ The address resource range of IOAPIC must be reserved in E820 and ACPI as
+ system resource.
+**/
+typedef struct {
+ /**
+ Revision 1: Init version
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 BdfValid : 1; ///< Set to 1 if BDF value is valid, PCH code will not program these fields if this bit is not TRUE. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits0 : 7; ///< Reserved bits
+ UINT32 BusNumber : 8; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0xF0</b>.
+ UINT32 DeviceNumber : 5; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0x1F</b>.
+ UINT32 FunctionNumber : 3; ///< Bus/Device/Function used as Requestor / Completer ID. Default is <b>0x00</b>.
+ UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; <b>1: Enable</b> IOAPIC Entry 24-119
+ /**
+ Enable 8254 Static Clock Gating during early POST time. <b>0: Disable</b>, 1: Enable
+ Set 8254CGE=1 in POST time might fail to boot legacy OS which using 8254 timer.
+ Make sure it won't break legacy OS boot before enabling this.
+ **/
+ UINT32 Early8254ClockGatingEnable : 1;
+ UINT32 RsvdBits1 : 6; ///< Reserved bits
+ UINT8 IoApicId; ///< This member determines IOAPIC ID. Default is <b>0x02</b>.
+ UINT8 ApicRangeSelect; ///< Define address bits 19:12 for the IOxAPIC range. Default is <b>0</b>
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCH_IOAPIC_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _IOAPIC_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h new file mode 100644 index 0000000000..6a4f6c9ee0 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h @@ -0,0 +1,48 @@ +/** @file
+ ISH policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _ISH_CONFIG_H_
+#define _ISH_CONFIG_H_
+
+#define ISH_CONFIG_REVISION 1
+extern EFI_GUID gIshConfigGuid;
+
+#pragma pack (push,1)
+
+///
+/// The PCH_ISH_CONFIG block describes Integrated Sensor Hub device.
+///
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 Enable : 1; ///< ISH Controler 0: Disable; <b>1: Enable</b>.
+ UINT32 SpiGpioAssign : 1; ///< ISH SPI GPIO pins assigned: <b>0: False</b> 1: True
+ UINT32 Uart0GpioAssign : 1; ///< ISH UART0 GPIO pins assigned: <b>0: False</b> 1: True
+ UINT32 Uart1GpioAssign : 1; ///< ISH UART1 GPIO pins assigned: <b>0: False</b> 1: True
+ UINT32 I2c0GpioAssign : 1; ///< ISH I2C0 GPIO pins assigned: <b>0: False</b> 1: True
+ UINT32 I2c1GpioAssign : 1; ///< ISH I2C1 GPIO pins assigned: <b>0: False</b> 1: True
+ UINT32 I2c2GpioAssign : 1; ///< ISH I2C2 GPIO pins assigned: <b>0: False</b> 1: True
+ UINT32 Gp0GpioAssign : 1; ///< ISH GP_0 GPIO pin assigned: <b>0: False</b> 1: True
+ UINT32 Gp1GpioAssign : 1; ///< ISH GP_1 GPIO pin assigned: <b>0: False</b> 1: True
+ UINT32 Gp2GpioAssign : 1; ///< ISH GP_2 GPIO pin assigned: <b>0: False</b> 1: True
+ UINT32 Gp3GpioAssign : 1; ///< ISH GP_3 GPIO pin assigned: <b>0: False</b> 1: True
+ UINT32 Gp4GpioAssign : 1; ///< ISH GP_4 GPIO pin assigned: <b>0: False</b> 1: True
+ UINT32 Gp5GpioAssign : 1; ///< ISH GP_5 GPIO pin assigned: <b>0: False</b> 1: True
+ UINT32 Gp6GpioAssign : 1; ///< ISH GP_6 GPIO pin assigned: <b>0: False</b> 1: True
+ UINT32 Gp7GpioAssign : 1; ///< ISH GP_7 GPIO pin assigned: <b>0: False</b> 1: True
+ UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: <b>0: False</b> 1: True
+ UINT32 RsvdBits0 : 16; ///< Reserved Bits
+} PCH_ISH_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _ISH_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h new file mode 100644 index 0000000000..980f3ac709 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h @@ -0,0 +1,44 @@ +/** @file
+ Lan policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _LAN_CONFIG_H_
+#define _LAN_CONFIG_H_
+
+#define LAN_CONFIG_REVISION 1
+extern EFI_GUID gLanConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ PCH intergrated LAN controller configuration settings.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Determines if enable PCH internal LAN, 0: Disable; <b>1: Enable</b>.
+ When Enable is changed (from disabled to enabled or from enabled to disabled),
+ it needs to set LAN Disable regsiter, which might be locked by FDSWL register.
+ So it's recommendated to issue a global reset when changing the status for PCH Internal LAN.
+ **/
+ UINT32 Enable : 1;
+ UINT32 LtrEnable : 1; ///< <b>0: Disable</b>; 1: Enable LTR capabilty of PCH internal LAN.
+ UINT32 K1OffEnable : 1; ///< Use CLKREQ for GbE power management; 1: Enabled, <b>0: Disabled</b>;
+ UINT32 RsvdBits0 : 4; ///< Reserved bits
+ UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported; 1: Enabled, <b>0: Disabled</b>;
+ UINT32 ClkReqNumber : 4; ///< CLKREQ# used by GbE. Valid if ClkReqSupported is TRUE.
+ UINT32 RsvdBits1 : 20; ///< Reserved bits
+} PCH_LAN_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LAN_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h new file mode 100644 index 0000000000..f083b3b50c --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h @@ -0,0 +1,67 @@ +/** @file
+ Lock down policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _LOCK_DOWN_CONFIG_H_
+#define _LOCK_DOWN_CONFIG_H_
+
+#define LOCK_DOWN_CONFIG_REVISION 1
+extern EFI_GUID gLockDownConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH
+ for security requirement.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ <b>(Test)</b> Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 GlobalSmi : 1;
+ /**
+ <b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register
+ Top Swap bit and the General Control and Status Registers Boot BIOS Straps. 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 BiosInterface : 1;
+ /**
+ <b>(Test)</b> Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
+ and lower 128-byte bank of RTC RAM. 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RtcLock : 1;
+ /**
+ Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5])
+ for the BIOS region protection. When it is enabled, the BIOS Region can only be
+ modified from SMM after EndOfDxe protocol is installed.
+ Note: When BiosLock is enabled, platform code also needs to update to take care
+ of BIOS modification (including SetVariable) in DXE or runtime phase after
+ EndOfDxe protocol is installed. 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 BiosLock : 1;
+ /**
+ Enable InSMM.STS (EISS) in SPI
+ If this bit is set, then WPD must be a '1' and InSMM.STS must be '1' also
+ in order to write to BIOS regions of SPI Flash. If this bit is clear,
+ then the InSMM.STS is a don't care.
+ The BIOS must set the EISS bit while BIOS Guard support is enabled.
+ In recovery path, platform can temporary disable EISS for SPI programming in
+ PEI phase or early DXE phase.
+ 0: Clear EISS bit; <b>1: Set EISS bit</b>.
+ **/
+ UINT32 SpiEiss : 1;
+ UINT32 RsvdBits0 : 27; ///< Reserved bits
+} PCH_LOCK_DOWN_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LOCK_DOWN_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h new file mode 100644 index 0000000000..be1613a5c2 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h @@ -0,0 +1,39 @@ +/** @file
+ Lpc policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _LPC_CONFIG_H_
+#define _LPC_CONFIG_H_
+
+#define LPC_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gLpcPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to LPC.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Enhance the port 8xh decoding.
+ Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
+ @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 EnhancePort8xhDecoding : 1;
+ UINT32 RsvdBits : 31; ///< Reserved bits
+} PCH_LPC_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LPC_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h new file mode 100644 index 0000000000..60b9828ebf --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h @@ -0,0 +1,50 @@ +/** @file
+ P2sb policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _P2SB_CONFIG_H_
+#define _P2SB_CONFIG_H_
+
+#define P2SB_CONFIG_REVISION 2
+extern EFI_GUID gP2sbConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to P2SB device.
+ <b>Revision 1:</b>
+ - Init version
+ <b>Revision 2:</b>
+ - Deprecate PsfUnlock and Add SbAccessUnlock to not lock SideBand register access.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ <b>(Test)</b>
+ This unlock the SBI lock bit to allow SBI after post time. <b>0: Disable</b>; 1: Enable.
+ NOTE: Do not set this policy "SbiUnlock" unless necessary.
+ **/
+ UINT32 SbiUnlock : 1;
+ UINT32 PsfUnlock : 1; //@deprecated
+ /**
+ <b>(Test)</b>
+ The SideBand registers will be locked before 3rd party code execution.
+ This policy unlock the SideBand space. <b>0: Disable</b>; 1: Enable.
+ NOTE: Do not set this policy "SbAccessUnlock" unless necessary.
+ **/
+ UINT32 SbAccessUnlock : 1;
+ UINT32 RsvdBits : 29;
+} PCH_P2SB_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _P2SB_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h new file mode 100644 index 0000000000..c946e9a116 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h @@ -0,0 +1,60 @@ +/** @file
+ PCH General policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_GENERAL_CONFIG_H_
+#define _PCH_GENERAL_CONFIG_H_
+
+#define PCH_GENERAL_CONFIG_REVISION 1
+#define PCH_GENERAL_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gPchGeneralConfigGuid;
+extern EFI_GUID gPchGeneralPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+enum PCH_RESERVED_PAGE_ROUTE {
+ PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
+ PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe.
+};
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Subsystem Vendor ID and Subsystem ID of the PCH devices.
+ This fields will be ignored if the value of SubSystemVendorId and SubSystemId
+ are both 0.
+ **/
+ UINT16 SubSystemVendorId; ///< Default Subsystem Vendor ID of the PCH devices. Default is <b>0x8086</b>
+ UINT16 SubSystemId; ///< Default Subsystem ID of the PCH devices. Default is <b>0x7270</b>
+ /**
+ This member describes whether or not the Compatibility Revision ID (CRID) feature
+ of PCH should be enabled. <b>0: Disable</b>; 1: Enable
+ **/
+ UINT32 Crid : 1;
+ UINT32 RsvdBits0 : 31; ///< Reserved bits
+} PCH_GENERAL_CONFIG;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT16 AcpiBase; ///< Power management I/O base address. Default is <b>0x1800</b>.
+ UINT8 RsvdBytes[2];
+ /**
+ Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI.
+ **/
+ UINT32 Port80Route : 1;
+ UINT32 RsvdBits0 : 31; ///< Reserved bits
+} PCH_GENERAL_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_GENERAL_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h new file mode 100644 index 0000000000..873386afe7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h @@ -0,0 +1,435 @@ +/** @file
+ Pcie root port policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PCH_PCIE_CONFIG_H_
+#define _PCH_PCIE_CONFIG_H_
+
+#define PCIE_RP_CONFIG_REVISION 4
+#define PCIE_RP_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gPcieRpConfigGuid;
+extern EFI_GUID gPcieRpPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_PCIE_SWEQ_COEFFS_MAX 5
+
+typedef enum {
+ PchPcieOverrideDisabled = 0,
+ PchPcieL1L2Override = 0x01,
+ PchPcieL1SubstatesOverride = 0x02,
+ PchPcieL1L2AndL1SubstatesOverride = 0x03,
+ PchPcieLtrOverride = 0x04
+} PCH_PCIE_OVERRIDE_CONFIG;
+
+/**
+ PCIe device table entry entry
+
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ To take effect table consisting of such entries must be instelled as PPI
+ on gPchPcieDeviceTablePpiGuid.
+ Last entry VendorId must be 0.
+**/
+typedef struct {
+ UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
+ UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
+ UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
+ UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
+ UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
+ UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
+ ///< Bit 1 must be set in OverrideConfig for this field to take effect
+ UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
+ /**
+ The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
+ This field can be zero if only the L1 Substate value is going to be override.
+ **/
+ UINT16 L1SubstatesCapOffset;
+ /**
+ L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
+ Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
+ Only bit [3:0] are applicable. Other bits are ignored.
+ **/
+ UINT8 L1SubstatesCapMask;
+ /**
+ L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sCommonModeRestoreTime;
+ /**
+ L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnScale;
+ /**
+ L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnValue;
+
+ /**
+ SnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 SnoopLatency;
+ /**
+ NonSnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 NonSnoopLatency;
+
+ /**
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ UINT8 ForceLtrOverride;
+ UINT8 Reserved[3];
+} PCH_PCIE_DEVICE_OVERRIDE;
+
+enum PCH_PCIE_SPEED {
+ PchPcieAuto,
+ PchPcieGen1,
+ PchPcieGen2,
+ PchPcieGen3
+};
+
+///
+/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
+///
+typedef enum {
+ PchPcieAspmDisabled,
+ PchPcieAspmL0s,
+ PchPcieAspmL1,
+ PchPcieAspmL0sL1,
+ PchPcieAspmAutoConfig,
+ PchPcieAspmMax
+} PCH_PCIE_ASPM_CONTROL;
+
+/**
+ Refer to PCH EDS for the PCH implementation values corresponding
+ to below PCI-E spec defined ranges
+**/
+typedef enum {
+ PchPcieL1SubstatesDisabled,
+ PchPcieL1SubstatesL1_1,
+ PchPcieL1SubstatesL1_2,
+ PchPcieL1SubstatesL1_1_2,
+ PchPcieL1SubstatesMax
+} PCH_PCIE_L1SUBSTATES_CONTROL;
+
+enum PCH_PCIE_MAX_PAYLOAD {
+ PchPcieMaxPayload128 = 0,
+ PchPcieMaxPayload256,
+ PchPcieMaxPayloadMax
+};
+
+enum PCH_PCIE_COMPLETION_TIMEOUT {
+ PchPcieCompletionTO_Default,
+ PchPcieCompletionTO_50_100us,
+ PchPcieCompletionTO_1_10ms,
+ PchPcieCompletionTO_16_55ms,
+ PchPcieCompletionTO_65_210ms,
+ PchPcieCompletionTO_260_900ms,
+ PchPcieCompletionTO_1_3P5s,
+ PchPcieCompletionTO_4_13s,
+ PchPcieCompletionTO_17_64s,
+ PchPcieCompletionTO_Disabled
+};
+
+typedef enum {
+ PchPcieEqDefault = 0, ///< Use reference code default (software margining)
+ PchPcieEqHardware = 1, ///< Hardware equalization (experimental), note this requires PCH-LP C0 or PCH-H D0 or newer
+ PchPcieEqSoftware = 2, ///< Use software margining flow
+ PchPcieEqStaticCoeff = 4 ///< Fixed equalization (requires Coefficient settings per lane)
+} PCH_PCIE_EQ_METHOD;
+
+/**
+ Represent lane specific PCIe Gen3 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM;
+
+/**
+ The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
+**/
+typedef struct {
+ UINT32 Enable : 1; ///< @deprecated.
+ UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
+ UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
+ UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
+ UINT32 RsvdBits0 : 5; ///< Reserved bits.
+ UINT32 ClkReqSupported : 1; ///< Indicate whether dedicated CLKREQ# is supported by the port.
+ /**
+ The ClkReq Signal mapped to this root port. Default is zero. Valid if ClkReqSupported is TRUE.
+ This Number should not exceed the Maximum Available ClkReq Signals for LP and H.
+ **/
+ UINT32 ClkReqNumber : 4;
+ /**
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+ Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
+ to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
+ In particular this helps to avoid issues with open-ended PCIe slots.
+ This is only applicable to non hot-plug ports.
+ <b>0: Disable</b>; 1: Enable.
+ **/
+ UINT32 ClkReqDetect : 1;
+ //
+ // Error handlings
+ //
+ UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
+ /**
+ Max Payload Size supported, Default <b>128B</b>, see enum PCH_PCIE_MAX_PAYLOAD
+ Changes Max Payload Size Supported field in Device Capabilities of the root port.
+ **/
+ UINT32 MaxPayload : 2;
+ UINT32 EnableHotplugSmi : 1; ///< Indicate whether the Hotplug Smi for Rootport is enabled, for TBT rootport we need to disable hotplug smi. 0: Disable; <b>1: Enable </b>.
+ UINT32 RsvdBits1 : 3; ///< Reserved fields for future expansion w/o protocol change
+
+ UINT32 DeviceResetPadActiveHigh : 1; ///< Indicated whether PERST# is active <b>0: Low</b>; 1: High, See: DeviceResetPad
+ /**
+ Determines each PCIE Port speed capability.
+ <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED)
+ **/
+ UINT8 PcieSpeed;
+ /**
+ PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD).
+ <b>0: Default</b>; 2: Software Search; 4: Fixed Coefficients
+ **/
+ UINT8 Gen3EqPh3Method;
+
+ UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
+ UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
+ /**
+ The PCH pin assigned to device PERST# signal if available, zero otherwise.
+ This entry is used mainly in Gen3 software equalization flow. It is necessary for some devices
+ (mainly some graphic adapters) to successfully complete the software equalization flow.
+ See also DeviceResetPadActiveHigh
+ **/
+ UINT32 DeviceResetPad;
+ UINT32 Rsvd1; ///< Reserved bytes
+ //
+ // Power Management
+ //
+ UINT8 Aspm; ///< The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
+ UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
+ UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
+ UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
+ UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
+ UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
+ UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
+ UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+ UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
+ UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+ UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+ UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+ UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
+ UINT32 SlotPowerLimitValue : 12; ///< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
+ //
+ // Gen3 Equalization settings
+ //
+ UINT32 Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>5</b>.
+ UINT32 Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ /**
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ UINT32 ForceLtrOverride : 1;
+ UINT32 EnableCpm : 1; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
+ UINT32 RsvdBits3 : 8; ///< Reserved Bits
+ /**
+ The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
+ before assuming there is no device and potentially disabling the port.
+ It's assumed that the link will exit detect state before root port initialization (sufficient time
+ elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
+ if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
+ In case of non-common clock enabled the default timout is 15ms.
+ <b>Default: 0</b>
+ **/
+ UINT16 DetectTimeoutMs;
+ UINT16 Rsvd2; ///< Reserved bytes
+ UINT32 Rsvd3; ///< Reserved bytes
+} PCH_PCIE_ROOT_PORT_CONFIG;
+
+/**
+ The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
+ <b>Revision 1</b>: Init version
+ <b>Revision 2</b>: Deprecate the PCIE RP enable in post mem.
+ <b>Revision 3</b>: Added DetectTimeoutMs parameter per port. The common DetectTimeoutMs is obsolete.
+ <b>Revision 4</b>: Added EnableHotplugSmi parameter per port.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of each PCH PCIe root port.
+ ///
+ PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
+ ///
+ /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
+ /// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
+ ///
+ PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS];
+ ///
+ /// List of coefficients used during equalization (applicable to both software and hardware EQ)
+ ///
+ PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX];
+ PCH_PCIE_EQ_PARAM Rsvd0[3];
+ ///
+ /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 EnablePort8xhDecode : 1;
+ ///
+ /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
+ ///
+ UINT32 PchPciePort8xhDecodePortIndex : 5;
+ ///
+ /// This member describes whether the PCI Express Clock Gating for each root port
+ /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 DisableRootPortClockGating : 1;
+ ///
+ /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 EnablePeerMemoryWrite : 1;
+ /**
+ This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable
+ or leaving untouched.
+ - <b>0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility.</b>
+ - To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are
+ presented for maximum power savings where possible.
+ - To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device
+ functionality.
+ - 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability.
+ **/
+ UINT32 AllowNoLtrIccPllShutdown : 1;
+ /**
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ <b>0: Disable</b>, 1: Enable
+ **/
+ UINT32 ComplianceTestMode : 1;
+ /**
+ RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
+ A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
+ BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
+ - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
+ This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
+ - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
+ That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
+ NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage
+ NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
+ be used when each one of root ports 1, 9, 17:
+ - is configured as PCIe and has correctly configured ClkReq signal, or
+ - does not own any mPhy lanes (they are configured as SATA or USB)
+ **/
+ UINT32 RpFunctionSwap : 1;
+
+ UINT32 RsvdBits0 : 21;
+ /**
+ @deprecated since revision 3, substituted by per-port timeout parameter
+ The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
+ before assuming there is no device and potentially disabling the port.
+ It's assumed that the link will exit detect state before root port initialization (sufficient time
+ elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
+ if device power-up sequence is controlled by BIOS or a specific device requires more time to detect.
+ I case of non-common clock enabled the default timeout is 15ms.
+ <b>Default: 0</b>
+ **/
+ UINT16 DetectTimeoutMs;
+ UINT16 Rsvd1; ///< Reserved bytes
+ /**
+ PCIe device override table
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ This is a pointer points to a 32bit address. And it's only used in PostMem phase.
+ Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.
+ Last entry VendorId must be 0.
+ The prototype of this policy is:
+ PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
+ **/
+ UINT32 PcieDeviceOverrideTablePtr;
+
+} PCH_PCIE_CONFIG;
+
+/**
+ The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
+ Revision 1: Init version
+ Add RpEnable in premem phase.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Root Port enabling mask.
+ Bit0 presents RP1, Bit1 presents RP2, and so on.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RpEnabledMask;
+} PCH_PCIE_RP_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_PCIE_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h new file mode 100644 index 0000000000..f483987c97 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h @@ -0,0 +1,215 @@ +/** @file
+ Power Management policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PM_CONFIG_H_
+#define _PM_CONFIG_H_
+
+#define PM_CONFIG_REVISION 4
+extern EFI_GUID gPmConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure allows to customize PCH wake up capability from S5 or DeepSx by WOL, LAN, PCIE wake events.
+**/
+typedef struct {
+ /**
+ Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register.
+ When set to 1, this bit blocks wake events from PME_B0_STS in S5, regardless of the state of PME_B0_EN.
+ When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. <b>0: Disable</b>; 1: Enable.
+ **/
+ UINT32 PmeB0S5Dis : 1;
+ UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enable Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0: Disable; <b>1: Enable</b>.
+ UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to wake from deep Sx. <b>0: Disable</b>; 1: Enable.
+ UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from Sx, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
+ UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from DeepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <b>0: Disable</b>; 1: Enable.
+ UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wake from deep Sx. 0: Disable; <b>1: Enable</b>.
+ UINT32 RsvdBits0 : 26;
+} PCH_WAKE_CONFIG;
+
+typedef enum {
+ PchDeepSxPolDisable,
+ PchDpS5BatteryEn,
+ PchDpS5AlwaysEn,
+ PchDpS4S5BatteryEn,
+ PchDpS4S5AlwaysEn,
+ PchDpS3S4S5BatteryEn,
+ PchDpS3S4S5AlwaysEn
+} PCH_DEEP_SX_CONFIG;
+
+typedef enum {
+ PchSlpS360us,
+ PchSlpS31ms,
+ PchSlpS350ms,
+ PchSlpS32s
+} PCH_SLP_S3_MIN_ASSERT;
+
+typedef enum {
+ PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing and Reset Signal Timings table
+ PchSlpS41s,
+ PchSlpS42s,
+ PchSlpS43s,
+ PchSlpS44s
+} PCH_SLP_S4_MIN_ASSERT;
+
+typedef enum {
+ PchSlpSus0ms,
+ PchSlpSus500ms,
+ PchSlpSus1s,
+ PchSlpSus4s
+} PCH_SLP_SUS_MIN_ASSERT;
+
+typedef enum {
+ PchSlpA0ms,
+ PchSlpA4s,
+ PchSlpA98ms,
+ PchSlpA2s
+} PCH_SLP_A_MIN_ASSERT;
+
+/**
+ The PCH_PM_CONFIG block describes expected miscellaneous power management settings.
+ The PowerResetStatusClear field would clear the Power/Reset status bits, please
+ set the bits if you want PCH Init driver to clear it, if you want to check the
+ status later then clear the bits.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Deprecate CapsuleResetType and the capsule update always uses warmreset cycle.
+ <b>Revision 3</b>:
+ - Added SlpS0VmEnable.
+ <b>Revision 4</b>
+ - Deprecate PciePllSsc and moved to PCH_HSIO_PCIE_PREMEM_CONFIG
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ PCH_WAKE_CONFIG WakeConfig; ///< Specify Wake Policy
+ UINT32 PchDeepSxPol : 4; ///< Deep Sx Policy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is <b>PchDeepSxPolDisable</b>.
+ UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Minimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value. Default is <b>PchSlpS350ms</b>.
+ UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Minimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value. Default is <b>PchSlpS44s</b>.
+ UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS Minimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each value. Default is <b>PchSlpSus4s</b>.
+ UINT32 PchSlpAMinAssert : 4; ///< SLP_A Minimum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. Default is <b>PchSlpA2s</b>.
+ UINT32 RsvdBits0 : 12;
+ /**
+ This member describes whether or not the LPC ClockRun feature of PCH should
+ be enabled. <b>0: Disable</b>; 1: Enable
+ **/
+ UINT32 LpcClockRun : 1;
+ UINT32 SlpStrchSusUp : 1; ///< <b>0: Disable</b>; 1: Enable SLP_X Stretching After SUS Well Power Up
+ /**
+ Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; <b>1: Enable</b>.
+ Configure On DC PHY Power Diable according to policy SlpLanLowDc.
+ When this is enabled, SLP_LAN# will be driven low when ACPRESENT is low.
+ This indicates that LAN PHY should be powered off on battery mode.
+ This will override the DC_PP_DIS setting by WolEnableOverride.
+ **/
+ UINT32 SlpLanLowDc : 1;
+ /**
+ PCH power button override period.
+ 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s
+ <b>Default is 0: 4s</b>
+ **/
+ UINT32 PwrBtnOverridePeriod : 3;
+ /**
+ <b>(Test)</b>
+ Disable/Enable PCH to CPU enery report feature. <b>0: Disable</b>; 1: Enable.
+ Enery Report is must have feature. Wihtout Energy Report, the performance report
+ by workloads/benchmarks will be unrealistic because PCH's energy is not being accounted
+ in power/performance management algorithm.
+ If for some reason PCH energy report is too high, which forces CPU to try to reduce
+ its power by throttling, then it could try to disable Energy Report to do first debug.
+ This might be due to energy scaling factors are not correct or the LPM settings are not
+ kicking in.
+ **/
+ UINT32 DisableEnergyReport : 1;
+ /**
+ When set to Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
+ When set to Enable, PCH will not pull down AC_PRESENT.
+ This setting is ignored when DeepSx is not supported.
+ Default is <b>0:Disable</b>
+ **/
+ UINT32 DisableDsxAcPresentPulldown : 1;
+ /**
+ <b>(Test)</b>
+ When set to true, this bit disallows host reads to PMC XRAM.
+ BIOS must set this bit (to disable and lock the feature) prior to passing control to OS
+ 0:Disable, <b>1:Enable</b>
+ **/
+ UINT32 PmcReadDisable : 1;
+ /**
+ @deprecated This determines the type of reset issued during the capsule update process by UpdateCapsule().
+ Always Warm reset.
+ **/
+ UINT32 CapsuleResetType : 1;
+ /**
+ Power button native mode disable.
+ While FALSE, the PMC's power button logic will act upon the input value from the GPIO unit, as normal.
+ While TRUE, this will result in the PMC logic constantly seeing the power button as de-asserted.
+ <b>Default is FALSE.</b>
+ **/
+ UINT32 DisableNativePowerButton : 1;
+ /**
+ Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
+ When set to one SLP_S0# will be asserted in idle state.
+ When set to zero SLP_S0# will not toggle and is always drivern high.
+ 0:Disable, <b>1:Enable</b>
+
+ @warning: In SKL PCH VCCPRIM_CORE must NOT be reduced based on SLP_S0# being asserted.
+ If a platform is using SLP_S0 to lower PCH voltage the below policy must be disabled.
+ **/
+ UINT32 SlpS0Enable : 1;
+ UINT32 MeWakeSts : 1; ///< Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
+ UINT32 WolOvrWkSts : 1; ///< Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0: Disable; <b>1: Enable</b>.
+ /**
+ Set true to enable TCO timer.
+ When FALSE, it disables PCH ACPI timer, and stops TCO timer.
+ @note: This will have significant power impact when it's enabled.
+ If TCO timer is disabled, uCode ACPI timer emulation must be enabled,
+ and WDAT table must not be exposed to the OS.
+ <b>0: Disable</b>, 1: Enable
+ **/
+ UINT32 EnableTcoTimer : 1;
+ /**
+ Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 SlpS0VmEnable : 1;
+ UINT32 RsvdBits1 : 16;
+ /**
+ Reset Power Cycle Duration could be customized in the unit of second. Please refer to EDS
+ for all support settings. PCH HW default is 4 seconds, and range is 1~4 seconds, where
+ <b>0 is default</b>, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds.
+ And make sure the setting correct, which never less than the following register.
+ - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH
+ - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH
+ - PWRM_CFG.SLP_A_MIN_ASST_WDTH
+ - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH
+ **/
+ UINT8 PchPwrCycDur;
+ /**
+ @deprecated since revision 4
+ Specifies the Pcie Pll Spread Spectrum Percentage
+ The value of this policy is in 1/10th percent units.
+ Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.
+ A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%
+ The default is <b>0xFF: AUTO - No BIOS override</b>.
+ **/
+ UINT8 PciePllSsc;
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+
+} PCH_PM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PM_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Port61Config.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Port61Config.h new file mode 100644 index 0000000000..d8b9cf6145 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/Port61Config.h @@ -0,0 +1,34 @@ +/** @file
+ Port 61h policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _PORT_61_CONFIG_H_
+#define _PORT_61_CONFIG_H_
+
+#define PORT_61_CONFIG_REVISION 1
+extern EFI_GUID gPort61ConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure is used for the emulation feature for Port61h read. The port is trapped
+ and the SMI handler will toggle bit4 according to the handler's internal state.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b> the emulation
+ UINT32 RsvdBits0 : 31; ///< Reserved bits
+} PCH_PORT61H_SMM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PORT_61_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h new file mode 100644 index 0000000000..0dc76e0c23 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h @@ -0,0 +1,193 @@ +/** @file
+ Sata policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SATA_CONFIG_H_
+#define _SATA_CONFIG_H_
+
+#define SATA_CONFIG_REVISION 4
+extern EFI_GUID gSataConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ PchSataModeAhci,
+ PchSataModeRaid,
+ PchSataModeMax
+} PCH_SATA_MODE;
+
+enum {
+ PchSataOromDelay2sec,
+ PchSataOromDelay4sec,
+ PchSataOromDelay6sec,
+ PchSataOromDelay8sec
+} PCH_SATA_OROM_DELAY;
+
+typedef enum {
+ PchSataSpeedDefault,
+ PchSataSpeedGen1,
+ PchSataSpeedGen2,
+ PchSataSpeedGen3
+} PCH_SATA_SPEED;
+
+/**
+ This structure configures the features, property, and capability for each SATA port.
+**/
+typedef struct {
+ /**
+ Enable SATA port.
+ It is highly recommended to disable unused ports for power savings
+ **/
+ UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>
+ UINT32 HotPlug : 1; ///< <b>0: Disable</b>; 1: Enable
+ UINT32 InterlockSw : 1; ///< <b>0: Disable</b>; 1: Enable
+ UINT32 External : 1; ///< <b>0: Disable</b>; 1: Enable
+ UINT32 SpinUp : 1; ///< <b>0: Disable</b>; 1: Enable the COMRESET initialization Sequence to the device
+ UINT32 SolidStateDrive : 1; ///< <b>0: HDD</b>; 1: SSD
+ UINT32 DevSlp : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP on the port
+ UINT32 EnableDitoConfig : 1; ///< <b>0: Disable</b>; 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)
+ UINT32 DmVal : 4; ///< DITO multiplier. Default is <b>15</b>.
+ UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout (DITO), Default is <b>625</b>.
+ /**
+ Support zero power ODD <b>0: Disable</b>, 1: Enable.
+ This is also used to disable ModPHY dynamic power gate.
+ **/
+ UINT32 ZpOdd : 1;
+ UINT32 RsvdBits0 : 9; ///< Reserved fields for future expansion w/o protocol change
+} PCH_SATA_PORT_CONFIG;
+
+/**
+ Rapid Storage Technology settings.
+**/
+typedef struct {
+ UINT32 RaidAlternateId : 1; ///< @deprecated
+ UINT32 Raid0 : 1; ///< 0: Disable; <b>1: Enable</b> RAID0
+ UINT32 Raid1 : 1; ///< 0: Disable; <b>1: Enable</b> RAID1
+ UINT32 Raid10 : 1; ///< 0: Disable; <b>1: Enable</b> RAID10
+ UINT32 Raid5 : 1; ///< 0: Disable; <b>1: Enable</b> RAID5
+ UINT32 Irrt : 1; ///< 0: Disable; <b>1: Enable</b> Intel Rapid Recovery Technology
+ UINT32 OromUiBanner : 1; ///< 0: Disable; <b>1: Enable</b> OROM UI and BANNER
+ UINT32 OromUiDelay : 2; ///< <b>00b: 2 secs</b>; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY)
+ UINT32 HddUnlock : 1; ///< 0: Disable; <b>1: Enable</b>. Indicates that the HDD password unlock in the OS is enabled
+ UINT32 LedLocate : 1; ///< 0: Disable; <b>1: Enable</b>. Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
+ UINT32 IrrtOnly : 1; ///< 0: Disable; <b>1: Enable</b>. Allow only IRRT drives to span internal and external ports
+ UINT32 SmartStorage : 1; ///< 0: Disable; <b>1: Enable</b> RST Smart Storage caching Bit
+ UINT32 LegacyOrom : 1; ///< <b>0: Disable</b>; 1: Enable RST Legacy OROM
+ /**
+ This option allows to configure SATA controller device ID while in RAID mode
+ Choosing Client will allow RST driver loading, RSTe driver will not be able to load
+ Choosing Alternate will not allow RST inbox driver loading in Windows
+ Choosing Server will allow RSTe driver loading, RST driver will not load
+ <b>0: Client</b>; 1: Alternate; 2: Server
+ **/
+ UINT32 RaidDeviceId : 2;
+ UINT32 OptaneMemory : 1; ///< 0: Disable; <b>1: Enable</b> RST Optane(TM) Memory
+ UINT32 RsvdBits0 : 15; ///< Reserved Bits
+} PCH_SATA_RST_CONFIG;
+
+/**
+ This structure describes the details of Intel RST for PCIe Storage remapping
+ Note: In order to use this feature, Intel RST Driver is required
+**/
+typedef struct {
+ /**
+ This member describes whether or not the Intel RST for PCIe Storage remapping should be enabled. <b>0: Disable</b>; 1: Enable.
+ Note 1: If Sata Controller is disabled, PCIe Storage Remapping should be disabled as well
+ Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI controllers Class Code is configured as RAID
+ **/
+ UINT32 Enable : 1;
+ /**
+ Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <b>0 = autodetect</b>)
+ The supported ports for PCIe Storage remapping is different depend on the platform and cycle router, the assignments are as below:
+ SKL PCH-LP RST PCIe Storage Cycle Router Assignment:
+ i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8
+ ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12
+
+ SKL PCH-H RST PCIe Storage Cycle Router Assignment:
+ i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12
+ ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16
+ iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20
+ **/
+ UINT32 RstPcieStoragePort : 5;
+ UINT32 RsvdBits0 : 2; ///< Reserved bit
+ /**
+ PCIe Storage Device Reset Delay in milliseconds (ms), which it guarantees such delay gap is fulfilled
+ before PCIe Storage Device configuration space is accessed after an reset caused by the link disable and enable step.
+ Default value is <b>100ms</b>.
+ **/
+ UINT32 DeviceResetDelay : 8;
+ UINT32 RsvdBits1 : 16; ///< Reserved bits
+
+ UINT32 Rsvd0[2]; ///< Reserved bytes
+} PCH_RST_PCIE_STORAGE_CONFIG;
+
+/**
+ The PCH_SATA_CONFIG block describes the expected configuration of the SATA controllers.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Added LegacyOrom in RST_SATA_RST_CONFIG to force RST Legacy Orom useage
+ <b>Revision 3</b>
+ - Added RaidDeviceId in PCH_SATA_RST_CONFIG to allow choice of RAID device id
+ <b>Revision 4</b>
+ - Added OptaneMemory in PCH_SATA_RST_CONFIG to enable RST optane memory
+**/
+typedef struct {
+ /**
+ This member specifies the revision of the SATA Configuration structure.
+ Any backwards compatible changes to this structure will result in an update in the revision number.
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>.
+ ///
+ UINT32 Enable : 1;
+ UINT32 TestMode : 1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes
+ UINT32 SalpSupport : 1; ///< 0: Disable; <b>1: Enable</b> Aggressive Link Power Management
+ UINT32 PwrOptEnable : 1; ///< 0: Disable; <b>1: Enable</b> SATA Power Optimizer on PCH side.
+ /**
+ EsataSpeedLimit
+ When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
+ Please be noted, this setting could be cleared by HBA reset, which might be issued
+ by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver after POST.
+ To support the Speed Limitation when POST, the EFI AHCI driver should preserve the
+ setting before and after initialization. For support it after POST, it's dependent on
+ driver's behavior.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT32 EsataSpeedLimit : 1;
+ UINT32 RsvdBits0 : 27; ///< Reserved bits
+
+ /**
+ Determines the system will be configured to which SATA mode (PCH_SATA_MODE). Default is <b>PchSataModeAhci</b>.
+ **/
+ PCH_SATA_MODE SataMode;
+ /**
+ Indicates the maximum speed the SATA controller can support
+ <b>0h: PchSataSpeedDefault</b>; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); 3h: 6 Gb/s (Gen 1)
+ **/
+ PCH_SATA_SPEED SpeedLimit;
+ /**
+ This member configures the features, property, and capability for each SATA port.
+ **/
+ PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];
+ PCH_SATA_RST_CONFIG Rst; ///< Setting applicable to Rapid Storage Technology
+ /**
+ This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
+ **/
+ PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORAGE_CR];
+} PCH_SATA_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SATA_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h new file mode 100644 index 0000000000..05a2f5dbfa --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h @@ -0,0 +1,61 @@ +/** @file
+ Scs policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SCS_CONFIG_H_
+#define _SCS_CONFIG_H_
+
+#define SCS_CONFIG_REVISION 1
+extern EFI_GUID gScsConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ PchScsSdDisabled = 0,
+ PchScsSdcardMode = 2
+} PCH_SCS_DEV_SD_MODE;
+
+typedef enum {
+ DriverStrength33Ohm = 0,
+ DriverStrength40Ohm,
+ DriverStrength50Ohm
+} PCH_SCS_EMMC_DRIVER_STRENGTH;
+
+///
+/// The PCH_SCS_CONFIG block describes Storage and Communication Subsystem (SCS) settings for PCH.
+///
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ UINT32 ScsEmmcEnabled : 2; ///< Determine if eMMC is enabled - 0: Disabled, <b>1: Enabled</b>.
+ UINT32 ScsEmmcHs400Enabled : 1; ///< Determine eMMC HS400 Mode if ScsEmmcEnabled - <b>0: Disabled</b>, 1: Enabled
+ /**
+ Determine if HS400 Training is required, set to FALSE if Hs400 Data is valid. <b>0: Disabled</b>, 1: Enabled.
+ First Boot or CMOS clear, system boot with Default settings, set tuning required.
+ Subsequent Boots, Get Variable 'Hs400TuningData'
+ - if failed to get variable, set tuning required
+ - if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and Hs400TxDataDll from variable. Set tuning not required.
+ - if driver strength value changes (ScsEmmcHs400DriverStrength) re-tuning is required.
+ **/
+ UINT32 ScsEmmcHs400TuningRequired : 1;
+ UINT32 ScsEmmcHs400DllDataValid : 1; ///< Set if HS400 Tuning Data Valid
+ UINT32 ScsEmmcHs400RxStrobeDll1 : 7; ///< Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode)
+ UINT32 ScsEmmcHs400TxDataDll : 7; ///< Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode)
+ UINT32 ScsEmmcHs400DriverStrength : 3; ///< I/O driver strength: 0 - 33 Ohm, <b>1 - 40 Ohm</b>, 2 - 50 Ohm
+ UINT32 ScsSdSwitch : 3; ///< Determine the operating mode of SDHC. Refer to PCH_SCS_DEV_SD_MODE for each value - 0: Disabled, <b>2: SDCard</b>.
+ UINT32 RsvdBits : 7;
+ UINT32 Rsvd0; ///< Reserved bytes
+} PCH_SCS_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SCS_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h new file mode 100644 index 0000000000..5caa24310a --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.h @@ -0,0 +1,56 @@ +/** @file
+ Serial IO policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SERIAL_IO_CONFIG_H_
+#define _SERIAL_IO_CONFIG_H_
+
+#define SERIAL_IO_CONFIG_REVISION 1
+extern EFI_GUID gSerialIoConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
+ to Acpi devices or Pci controllers, and also set the interrupt type to Acpi or Pci
+ through Policy. It also provides to configure the I2c0 and I2c1 voltage
+ to 1.8v or 3.3v by platform setting.
+ Please refer to PeiDxeSmmPchSerialIoLib.h for definition of device numbers and enum values for the below fields
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ 0: Disabled; 1: ACPI Mode; <b>2: PCI Mode</b>; 3: Hidden mode, 4: Legacy UART mode, 5: Skip Init
+ @note: Considering the PcdSerialIoUartDebugEnable and PcdSerialIoUartNumber for all SerialIo UARTx,
+ the PCD is more meaningful to represent the board design. It means, if PcdSerialIoUartDebugEnable is not 0,
+ the board is designed to use the SerialIo UART for debug message and the PcdSerialIoUartNumber is dedicated
+ to be Debug UART usage. Therefore, it should grayout the option from setup menu since no other options
+ available for this UART controller on this board, and also override the policy default accordingly.
+ While PcdSerialIoUartDebugEnable is 0, then it's allowed to configure the UART controller by policy.
+ @note: While DevMode is set to 5 (Skip Init), BIOS will not initialize this controller. GPIO and PSF configuration is skipped.
+ Platform is resonsible for configuring this controller. If platform initializes the Serial IO controller in
+ Hidden Mode, it MUST follow the predefined BAR address for the controller.
+ **/
+ UINT8 DevMode[PCH_SERIALIO_MAX_CONTROLLERS];
+ UINT8 Gpio; ///< 0: Disabled; <b>1: Enabled</b>.
+ UINT8 I2cVoltage[PCH_SERIALIO_MAX_I2C_CONTROLLERS]; ///< Selects the IO voltage for I2C controllers. It can be 1.8v or 3.3v. <b>0: PchSerialIoIs33V</b>; 1: PchSerialIoIs18V.
+ UINT8 SpiCsPolarity[PCH_SERIALIO_MAX_SPI_CONTROLLERS]; ///< Selects SPI ChipSelect signal polarity, <b>0=active low</b>.
+ UINT8 UartHwFlowCtrl[PCH_SERIALIO_MAX_UART_CONTROLLERS]; ///< Enables UART hardware flow control, CTS and RTS lines, <b>0:disabled</b>, 1:enabled
+ UINT8 Rsvd0[1]; ///< Bytes reserved for reuse when new fields are added to struct
+ UINT32 DebugUartNumber : 2; ///< UART number for debug purpose. 0:UART0, 1: UART1, <b>2:UART2</b>
+ UINT32 EnableDebugUartAfterPost : 1; ///< Enable debug UART controller after post. 0: diabled, <b>1: enabled</b>
+ UINT32 RsvdBits0 : 29;
+} PCH_SERIAL_IO_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h new file mode 100644 index 0000000000..b64579cd92 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig.h @@ -0,0 +1,48 @@ +/** @file
+ Serial IRQ policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SERIAL_IRQ_CONFIG_H_
+#define _SERIAL_IRQ_CONFIG_H_
+
+#define SERIAL_IRQ_CONFIG_REVISION 1
+extern EFI_GUID gSerialIrqConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ PchQuietMode,
+ PchContinuousMode
+} PCH_SIRQ_MODE;
+///
+/// Refer to PCH EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode
+///
+typedef enum {
+ PchSfpw4Clk,
+ PchSfpw6Clk,
+ PchSfpw8Clk
+} PCH_START_FRAME_PULSE;
+
+///
+/// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of the PCH for Serial IRQ.
+///
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 SirqEnable : 1; ///< Determines if enable Serial IRQ. 0: Disable; <b>1: Enable</b>.
+ UINT32 SirqMode : 2; ///< Serial IRQ Mode Select. Refer to PCH_SIRQ_MODE for each value. <b>0: quiet mode</b> 1: continuous mode.
+ UINT32 StartFramePulse : 3; ///< Start Frame Pulse Width. Refer to PCH_START_FRAME_PULSE for each value. Default is <b>PchSfpw4Clk</b>.
+ UINT32 RsvdBits0 : 26; ///< Reserved bits
+} PCH_LPC_SIRQ_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IRQ_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h new file mode 100644 index 0000000000..78ac72aa87 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h @@ -0,0 +1,56 @@ +/** @file
+ Smbus policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SMBUS_CONFIG_H_
+#define _SMBUS_CONFIG_H_
+
+#define SMBUS_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gSmbusPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
+
+///
+/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
+///
+typedef struct {
+ /**
+ Revision 1: Init version
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ This member describes whether or not the SMBus controller of PCH should be enabled.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 Enable : 1;
+ UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
+ UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
+ ///
+ /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
+ /// For security recommendations, SPD write disable bit must be set.
+ ///
+ UINT32 SpdWriteDisable : 1;
+ UINT32 RsvdBits0 : 28; ///< Reserved bits
+ UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
+ UINT8 Rsvd0; ///< Reserved bytes
+ UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
+ /**
+ Array of addresses reserved for non-ARP-capable SMBus devices.
+ **/
+ UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
+} PCH_SMBUS_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SMBUS_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SpiConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SpiConfig.h new file mode 100644 index 0000000000..688fa314cb --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/SpiConfig.h @@ -0,0 +1,38 @@ +/** @file
+ Spi policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _SPI_CONFIG_H_
+#define _SPI_CONFIG_H_
+
+#define SPI_CONFIG_REVISION 1
+extern EFI_GUID gSpiConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to SPI.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Force to show SPI controller.
+ <b>0: FALSE</b>, 1: TRUE
+ NOTE: For Windows OS, it MUST BE false. It's optional for other OSs.
+ **/
+ UINT32 ShowSpiController : 1;
+ UINT32 RsvdBits : 31; ///< Reserved bits
+} PCH_SPI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SPI_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h new file mode 100644 index 0000000000..8963da6ee7 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h @@ -0,0 +1,176 @@ +/** @file
+ Thermal policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _THERMAL_CONFIG_H_
+#define _THERMAL_CONFIG_H_
+
+#define THERMAL_CONFIG_REVISION 1
+extern EFI_GUID gThermalConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure lists PCH supported throttling register setting for custimization.
+ When the SuggestedSetting is enabled, the customized values are ignored.
+**/
+typedef struct {
+ UINT32 T0Level : 9; ///< Custimized T0Level value. If SuggestedSetting is used, this setting is ignored.
+ UINT32 T1Level : 9; ///< Custimized T1Level value. If SuggestedSetting is used, this setting is ignored.
+ UINT32 T2Level : 9; ///< Custimized T2Level value. If SuggestedSetting is used, this setting is ignored.
+ UINT32 TTEnable : 1; ///< Enable the thermal throttle function. If SuggestedSetting is used, this settings is ignored.
+ /**
+ When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state.
+ If SuggestedSetting is used, this setting is ignored.
+ **/
+ UINT32 TTState13Enable : 1;
+ /**
+ When set to 1, this entire register (TL) is locked and remains locked until the next platform reset.
+ If SuggestedSetting is used, this setting is ignored.
+ **/
+ UINT32 TTLock : 1;
+ UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values.
+ /**
+ ULT processors support thermal management and cross thermal throttling between the processor package
+ and LP PCH. The PMSYNC message from PCH to CPU includes specific bit fields to update the PCH
+ thermal status to the processor which is factored into the processor throttling.
+ Enable/Disable PCH Cross Throttling; 0: Disabled, 1: <b>Enabled</b>.
+ **/
+ UINT32 PchCrossThrottling : 1;
+ UINT32 Rsvd0; ///< Reserved bytes
+} THERMAL_THROTTLE_LEVELS;
+
+/**
+ This structure allows to customize DMI HW Autonomous Width Control for Thermal and Mechanical spec design.
+ When the SuggestedSetting is enabled, the customized values are ignored.
+**/
+typedef struct {
+ UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous Width Enable
+ UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
+ UINT32 RsvdBits0 : 6; ///< Reserved bits
+ UINT32 TS0TW : 2; ///< Thermal Sensor 0 Target Width
+ UINT32 TS1TW : 2; ///< Thermal Sensor 1 Target Width
+ UINT32 TS2TW : 2; ///< Thermal Sensor 2 Target Width
+ UINT32 TS3TW : 2; ///< Thermal Sensor 3 Target Width
+ UINT32 RsvdBits1 : 16; ///< Reserved bits
+} DMI_HW_WIDTH_CONTROL;
+
+/**
+ This structure lists PCH supported SATA thermal throttling register setting for custimization.
+ The settings is programmed through SATA Index/Data registers.
+ When the SuggestedSetting is enabled, the customized values are ignored.
+**/
+typedef struct {
+ UINT32 P0T1M : 2; ///< Port 0 T1 Multipler
+ UINT32 P0T2M : 2; ///< Port 0 T2 Multipler
+ UINT32 P0T3M : 2; ///< Port 0 T3 Multipler
+ UINT32 P0TDisp : 2; ///< Port 0 Tdispatch
+
+ UINT32 P1T1M : 2; ///< Port 1 T1 Multipler
+ UINT32 P1T2M : 2; ///< Port 1 T2 Multipler
+ UINT32 P1T3M : 2; ///< Port 1 T3 Multipler
+ UINT32 P1TDisp : 2; ///< Port 1 Tdispatch
+
+ UINT32 P0Tinact : 2; ///< Port 0 Tinactive
+ UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Tdispatch
+ UINT32 P1Tinact : 2; ///< Port 1 Tinactive
+ UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Tdispatch
+ UINT32 SuggestedSetting : 1; ///< 0: Disable; <b>1: Enable</b> suggested representative values
+ UINT32 RsvdBits0 : 9; ///< Reserved bits
+} SATA_THERMAL_THROTTLE;
+
+/**
+ This structure configures PCH memory throttling thermal sensor GPIO PIN settings
+**/
+typedef struct {
+ /**
+ GPIO PM_SYNC enable, 0:Diabled, 1:<b>Enabled</b>
+ When enabled, RC will overrides the selected GPIO native mode.
+ For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1
+ For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2
+ For SKL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, CPU_GP_3 is GPP_B4.
+ **/
+ UINT32 PmsyncEnable : 1;
+ UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 state, 0:Disabled, 1:<b>Enabled</b>
+ UINT32 PinSelection : 1; ///< GPIO Pin assignment selection, <b>0: default</b>, 1: secondary
+ UINT32 RsvdBits0 : 29;
+} TS_GPIO_PIN_SETTING;
+
+enum PCH_PMSYNC_GPIO_X_SELECTION {
+ TsGpioC,
+ TsGpioD,
+ MaxTsGpioPin
+};
+
+/**
+ This structure supports an external memory thermal sensor (TS-on-DIMM or TS-on-Board).
+**/
+typedef struct {
+ /**
+ This will enable PCH memory throttling.
+ While this policy is enabled, must also enable EnableExtts in SA policy.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT32 Enable : 1;
+ UINT32 RsvdBits0 : 31;
+ /**
+ GPIO_C and GPIO_D selection for memory throttling.
+ It's strongly recommended to choose GPIO_C and GPIO_D for memory throttling feature,
+ and route EXTTS# accordingly.
+ **/
+ TS_GPIO_PIN_SETTING TsGpioPinSetting[2];
+} PCH_MEMORY_THROTTLING;
+
+/**
+ The PCH_THERMAL_CONFIG block describes the expected configuration of the PCH for Thermal.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ This field reports the status of Thermal Device. When it reports ThermalDevice
+ is disabled, the PCI configuration space of thermal device will be hidden by
+ setting TCFD and PCR[PSF2] TRH PCIEN[8] prior to end of POST.
+ **/
+ UINT32 ThermalDeviceEnable : 2; ///< 0: Disabled, <b>1: Enabled in PCI mode</b>, 2: Enabled in ACPI mode
+ UINT32 TsmicLock : 1; ///< This locks down "SMI Enable on Alert Thermal Sensor Trip". 0: Disabled, 1: <b>Enabled</b>.
+ UINT32 RsvdBits0 : 29;
+ /**
+ This field decides the settings of Thermal throttling. When the Suggested Setting
+ is enabled, PCH RC will use the suggested representative values.
+ **/
+ THERMAL_THROTTLE_LEVELS TTLevels;
+ /**
+ This field decides the settings of DMI throttling. When the Suggested Setting
+ is enabled, PCH RC will use the suggested representative values.
+ **/
+ DMI_HW_WIDTH_CONTROL DmiHaAWC;
+ /**
+ This field decides the settings of Sata thermal throttling. When the Suggested Setting
+ is enabled, PCH RC will use the suggested representative values.
+ **/
+ SATA_THERMAL_THROTTLE SataTT;
+ /**
+ Memory Thermal Management settings
+ **/
+ PCH_MEMORY_THROTTLING MemoryThrottling;
+ /**
+ This field decides the temperature, default is <b>zero</b>.
+ - 0x00 is the hottest
+ - 0x1FF is the lowest temperature
+ **/
+ UINT16 PchHotLevel;
+ UINT8 Rsvd0[6];
+} PCH_THERMAL_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _THERMAL_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/TraceHubConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/TraceHubConfig.h new file mode 100644 index 0000000000..5455c40514 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/TraceHubConfig.h @@ -0,0 +1,35 @@ +/** @file
+ Trace Hub policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _TRACEHUB_CONFIG_H_
+#define _TRACEHUB_CONFIG_H_
+
+#define TRACEHUB_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gTraceHubPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+///
+/// The PCH_TRACE_HUB_CONFIG block describes TraceHub settings for PCH.
+///
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 EnableMode : 2; ///< 0 = Disable <b> 2 = Host Debugger enabled </b>
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ UINT32 MemReg0Size; ///< Default is <b>0 (none)</b>.
+ UINT32 MemReg1Size; ///< Default is <b>0 (none)</b>.
+} PCH_TRACE_HUB_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _TRACEHUB_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/UsbConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/UsbConfig.h new file mode 100644 index 0000000000..c2cef0aa43 --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/UsbConfig.h @@ -0,0 +1,233 @@ +/** @file
+ USB policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _USB_CONFIG_H_
+#define _USB_CONFIG_H_
+
+#define USB_CONFIG_REVISION 2
+extern EFI_GUID gUsbConfigGuid;
+
+#pragma pack (push,1)
+
+///
+/// Overcurrent pins, the values match the setting of PCH EDS, please refer to PCH EDS for more details
+///
+typedef enum {
+ PchUsbOverCurrentPin0 = 0,
+ PchUsbOverCurrentPin1,
+ PchUsbOverCurrentPin2,
+ PchUsbOverCurrentPin3,
+ PchUsbOverCurrentPin4,
+ PchUsbOverCurrentPin5,
+ PchUsbOverCurrentPin6,
+ PchUsbOverCurrentPin7,
+ PchUsbOverCurrentPinSkip,
+ PchUsbOverCurrentPinMax
+} PCH_USB_OVERCURRENT_PIN;
+
+///
+/// The location of the USB connectors. This information is use to decide eye diagram tuning value for Usb 2.0 motherboard trace.
+///
+enum PCH_USB_PORT_LOCATION{
+ PchUsbPortLocationBackPanel = 0,
+ PchUsbPortLocationFrontPanel,
+ PchUsbPortLocationDock,
+ PchUsbPortLocationMiniPciE,
+ PchUsbPortLocationFlex,
+ PchUsbPortLocationInternalTopology,
+ PchUsbPortLocationSkip,
+ PchUsbPortLocationMax
+};
+
+
+/**
+ This structure configures per USB2 AFE settings.
+ It allows to setup the port parameters.
+**/
+typedef struct {
+/** Per Port HS Preemphasis Bias (PERPORTPETXISET)
+ 000b - 0mV
+ 001b - 11.25mV
+ 010b - 16.9mV
+ 011b - 28.15mV
+ 100b - 28.15mV
+ 101b - 39.35mV
+ 110b - 45mV
+ 111b - 56.3mV
+**/
+ UINT8 Petxiset;
+/** Per Port HS Transmitter Bias (PERPORTTXISET)
+ 000b - 0mV
+ 001b - 11.25mV
+ 010b - 16.9mV
+ 011b - 28.15mV
+ 100b - 28.15mV
+ 101b - 39.35mV
+ 110b - 45mV
+ 111b - 56.3mV
+**/
+ UINT8 Txiset;
+/**
+ Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)
+ 00b - Emphasis OFF
+ 01b - De-emphasis ON
+ 10b - Pre-emphasis ON
+ 11b - Pre-emphasis & De-emphasis ON
+**/
+ UINT8 Predeemp;
+/**
+ Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)
+ 1b - half-bit pre-emphasis
+ 0b - full-bit pre-emphasis
+**/
+ UINT8 Pehalfbit;
+} PCH_USB20_AFE;
+
+/**
+ This structure configures per USB2 port physical settings.
+ It allows to setup the port location and port length, and configures the port strength accordingly.
+**/
+typedef struct {
+ UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
+ UINT32 RsvdBits0 : 31; ///< Reserved bits
+ /**
+ These members describe the specific over current pin number of USB 2.0 Port N.
+ It is SW's responsibility to ensure that a given port's bit map is set only for
+ one OC pin Description. USB2 and USB3 on the same combo Port must use the same
+ OC pin (see: PCH_USB_OVERCURRENT_PIN).
+ **/
+ UINT8 OverCurrentPin;
+ UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4.
+ PCH_USB20_AFE Afe; ///< USB2 AFE settings
+ UINT32 Rsvd1[1]; ///< Reserved bytes
+} PCH_USB20_PORT_CONFIG;
+
+/**
+ This structure describes whether the USB3 Port N of PCH is enabled by platform modules.
+**/
+typedef struct {
+ UINT32 Enable : 1; ///< 0: Disable; <b>1: Enable</b>.
+ UINT32 RsvdBits0 : 31; ///< Reserved bits
+ /**
+ These members describe the specific over current pin number of USB 3.0 Port N.
+ It is SW's responsibility to ensure that a given port's bit map is set only for
+ one OC pin Description. USB2 and USB3 on the same combo Port must use the same
+ OC pin (see: PCH_USB_OVERCURRENT_PIN).
+ **/
+ UINT8 OverCurrentPin;
+ UINT8 Rsvd0[3]; ///< Reserved bytes, align to multiple 4
+
+ UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment, <b>0: Disable</b>; 1: Enable.
+ /**
+ USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2deemph3p5)
+ HSIO_TX_DWORD5[21:16]
+ <b>Default = 29h</b> (approximately -3.5dB De-Emphasis)
+ **/
+ UINT32 HsioTxDeEmph : 6;
+
+ UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, <b>0: Disable</b>; 1: Enable.
+ /**
+ USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)
+ HSIO_TX_DWORD8[21:16]
+ <b>Default = 00h</b>
+ **/
+ UINT32 HsioTxDownscaleAmp : 6;
+
+ UINT32 RsvdBits1 : 18; ///< Reserved bits
+ UINT32 Rsvd1[1]; ///< Reserved bytes
+} PCH_USB30_PORT_CONFIG;
+
+#define PCH_XHCI_MODE_OFF 0
+#define PCH_XHCI_MODE_ON 1
+
+/**
+ These members describe some settings which are related to the SSIC ports.
+**/
+typedef struct {
+ /**
+ 0: Disable; <b>1: Enable</b> SSIC support.
+ **/
+ UINT32 Enable : 1;
+ UINT32 RsvdBits1 : 31;
+} PCH_XHCI_SSIC_PORT;
+/**
+ These members describe some settings which are related to the SSIC ports.
+**/
+typedef struct {
+ PCH_XHCI_SSIC_PORT SsicPort[PCH_XHCI_MAX_SSIC_PORT_COUNT];
+} PCH_SSIC_CONFIG;
+
+/**
+ The PCH_XDCI_CONFIG block describes the configurations
+ of the xDCI Usb Device controller.
+**/
+typedef struct {
+ /**
+ This member describes whether or not the xDCI controller should be enabled.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 Enable : 1;
+ UINT32 RsvdBits0 : 31; ///< Reserved bits
+} PCH_XDCI_CONFIG;
+
+
+/**
+ This member describes the expected configuration of the PCH USB controllers,
+ Platform modules may need to refer Setup options, schematic, BIOS specification
+ to update this field.
+ The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated by referring
+ the schematic.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Added DelayPdoProgramming policy option.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ This policy will disable XHCI compliance mode on all ports. Complicance Mode should be default enabled.
+ For the platform that support USB Type-C, it can disable Compliance Mode, and enable Compliance Mode when testing.
+ <b>0:Disable</b> , 1: Enable
+ **/
+ UINT32 DisableComplianceMode : 1;
+ /**
+ This policy option if set will move Port Disable Override register programming to ReadyToBoot event during DXE phase.
+ If not enabled it will program Port Disable Override register in PEI phase during PCH initialization
+ <b>0: Program in PEI phase </b>, 1: Program in DXE phase
+ **/
+ UINT32 DelayPdoProgramming : 1;
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ /**
+ These members describe whether the USB2 Port N of PCH is enabled by platform modules.
+ Panel and Dock are used to describe the layout of USB port. Panel is only available for Desktop PCH.
+ Dock is only available for Mobile LPT.
+ **/
+ PCH_USB20_PORT_CONFIG PortUsb20[PCH_MAX_USB2_PORTS];
+ /**
+ These members describe whether the USB3 Port N of PCH is enabled by platform modules.
+ **/
+ PCH_USB30_PORT_CONFIG PortUsb30[PCH_MAX_USB3_PORTS];
+ /**
+ This member describes whether or not the xDCI controller should be enabled.
+ **/
+ PCH_XDCI_CONFIG XdciConfig;
+ /**
+ These members describe some settings which are related to the SSIC ports.
+ **/
+ PCH_SSIC_CONFIG SsicConfig;
+} PCH_USB_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _USB_CONFIG_H_
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.h new file mode 100644 index 0000000000..610c1092fb --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.h @@ -0,0 +1,38 @@ +/** @file
+ WatchDog policy
+
+Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef _WATCH_DOG_CONFIG_H_
+#define _WATCH_DOG_CONFIG_H_
+
+#define WATCH_DOG_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gWatchDogPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This policy clears status bits and disable watchdog, then lock the
+ WDT registers.
+ while WDT is designed to be disabled and locked by Policy,
+ bios should not enable WDT by WDT PPI. In such case, bios shows the
+ warning message but not disable and lock WDT register to make sure
+ WDT event trigger correctly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 31;
+} PCH_WDT_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _WATCH_DOG_CONFIG_H_
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