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-rw-r--r--Silicon/Intel/LewisburgPkg/Include/Ppi/PchPcieDeviceTable.h130
-rw-r--r--Silicon/Intel/LewisburgPkg/Include/Ppi/PchPolicy.h25
-rw-r--r--Silicon/Intel/LewisburgPkg/Include/Ppi/PchReset.h99
-rw-r--r--Silicon/Intel/LewisburgPkg/Include/Ppi/Spi.h31
4 files changed, 285 insertions, 0 deletions
diff --git a/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPcieDeviceTable.h b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPcieDeviceTable.h
new file mode 100644
index 0000000000..36451c4962
--- /dev/null
+++ b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPcieDeviceTable.h
@@ -0,0 +1,130 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef PCH_PCIE_DEVICE_TABLE_H_
+#define PCH_PCIE_DEVICE_TABLE_H_
+
+
+//
+// PCIe device table PPI GUID.
+//
+extern EFI_GUID gPchPcieDeviceTablePpiGuid;
+
+typedef enum {
+ PchPcieOverrideDisabled = 0,
+ PchPcieL1L2Override = 0x01,
+ PchPcieL1SubstatesOverride = 0x02,
+ PchPcieL1L2AndL1SubstatesOverride = 0x03,
+ PchPcieLtrOverride = 0x04
+} PCH_PCIE_OVERRIDE_CONFIG;
+
+/**
+ PCIe device table entry entry
+
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ To take effect table consisting of such entries must be instelled as PPI
+ on gPchPcieDeviceTablePpiGuid.
+ Last entry VendorId must be 0.
+**/
+typedef struct {
+ UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
+ UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
+ UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
+ UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
+ UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
+ UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
+ ///< Bit 1 must be set in OverrideConfig for this field to take effect
+ UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
+ /**
+ The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
+ This field can be zero if only the L1 Substate value is going to be override.
+ **/
+ UINT16 L1SubstatesCapOffset;
+ /**
+ L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
+ Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
+ Only bit [3:0] are applicable. Other bits are ignored.
+ **/
+ UINT8 L1SubstatesCapMask;
+ /**
+ L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sCommonModeRestoreTime;
+ /**
+ L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnScale;
+ /**
+ L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnValue;
+
+ /**
+ SnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 SnoopLatency;
+ /**
+ NonSnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 NonSnoopLatency;
+
+ UINT32 Reserved;
+} PCH_PCIE_DEVICE_OVERRIDE;
+
+#endif // PCH_PCIE_DEVICE_TABLE_H_
+
diff --git a/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPolicy.h b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPolicy.h
new file mode 100644
index 0000000000..e994763e5e
--- /dev/null
+++ b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchPolicy.h
@@ -0,0 +1,25 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_POLICY_PPI_H_
+#define _PCH_POLICY_PPI_H_
+
+#include <PchAccess.h>
+#include <PchPolicyCommon.h>
+
+extern EFI_GUID gPchPlatformPolicyPpiGuid;
+
+
+typedef struct _PCH_POLICY PCH_POLICY_PPI;
+
+#endif // PCH_POLICY_PPI_H_
diff --git a/Silicon/Intel/LewisburgPkg/Include/Ppi/PchReset.h b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchReset.h
new file mode 100644
index 0000000000..f7d3481f77
--- /dev/null
+++ b/Silicon/Intel/LewisburgPkg/Include/Ppi/PchReset.h
@@ -0,0 +1,99 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_RESET_PPI_H_
+#define _PCH_RESET_PPI_H_
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gPchResetPpiGuid;
+extern EFI_GUID gPchResetCallbackPpiGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_RESET_PPI PCH_RESET_PPI;
+typedef struct _PCH_RESET_CALLBACK_PPI PCH_RESET_CALLBACK_PPI;
+
+//
+// Related Definitions
+//
+//
+// PCH Reset Types
+//
+typedef enum {
+ ColdReset,
+ WarmReset,
+ ShutdownReset,
+ PowerCycleReset,
+ GlobalReset,
+ GlobalResetWithEc,
+ PchResetTypeMax
+} PCH_RESET_TYPE;
+
+//
+// Member functions
+//
+/**
+ Execute Pch Reset from the host controller.
+
+ @param[in] This Pointer to the PCH_RESET_PPI instance.
+ @param[in] PchResetType Pch Reset Types which includes ColdReset, WarmReset, ShutdownReset,
+ PowerCycleReset, GlobalReset, GlobalResetWithEc
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER If ResetType is invalid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_RESET_PPI_API) (
+ IN PCH_RESET_PPI *This,
+ IN PCH_RESET_TYPE PchResetType
+ );
+
+/**
+ Execute call back function for Pch Reset.
+
+ @param[in] PchResetType Pch Reset Types which includes PowerCycle, Globalreset.
+
+ @retval EFI_SUCCESS The callback function has been done successfully
+ @retval EFI_NOT_FOUND Failed to find Pch Reset Callback ppi. Or, none of
+ callback ppi is installed.
+ @retval Others Do not do any reset from PCH
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_RESET_CALLBACK) (
+ IN PCH_RESET_TYPE PchResetType
+ );
+
+/**
+ Interface structure to execute Pch Reset from the host controller.
+**/
+struct _PCH_RESET_PPI {
+ PCH_RESET_PPI_API Reset;
+};
+
+/**
+ This ppi is used to execute PCH Reset from the host controller.
+ The PCH Reset protocol and PCH Reset PPI implement the Intel (R) PCH Reset Interface
+ for DXE and PEI environments, respectively. If other drivers need to run their
+ callback function right before issuing the reset, they can install PCH Reset
+ Callback Protocol/PPI before PCH Reset DXE/PEI driver to achieve that.
+**/
+struct _PCH_RESET_CALLBACK_PPI {
+ PCH_RESET_CALLBACK ResetCallback;
+};
+
+#endif
diff --git a/Silicon/Intel/LewisburgPkg/Include/Ppi/Spi.h b/Silicon/Intel/LewisburgPkg/Include/Ppi/Spi.h
new file mode 100644
index 0000000000..44d043cf0e
--- /dev/null
+++ b/Silicon/Intel/LewisburgPkg/Include/Ppi/Spi.h
@@ -0,0 +1,31 @@
+/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PCH_SPI_PPI_H_
+#define _PCH_SPI_PPI_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gPeiSpiPpiGuid;
+
+/**
+ Reuse the PCH_SPI_PROTOCOL definitions
+ This is possible becaues the PPI implementation does not rely on a PeiService pointer,
+ as it uses EDKII Glue Lib to do IO accesses
+**/
+typedef EFI_SPI_PROTOCOL PCH_SPI_PPI;
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 10:14:38 +0000