diff options
Diffstat (limited to 'Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PchSklGpioData.c')
| -rw-r--r-- | Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PchSklGpioData.c | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PchSklGpioData.c b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PchSklGpioData.c new file mode 100644 index 0000000000..62d93d6c86 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiDxeSmmGpioLib/PchSklGpioData.c @@ -0,0 +1,65 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "GpioLibrary.h" + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchGpioGroupInfo[] = { + {PID_GPIOCOM0, R_PCH_H_PCR_GPIO_GPP_A_PAD_OWN, R_PCH_PCR_GPIO_GPP_A_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_A_GPI_IS, R_PCH_PCR_GPIO_GPP_A_GPI_IE, R_PCH_PCR_GPIO_GPP_A_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_A_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_A_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET, V_PCH_GPIO_GPP_A_PAD_MAX}, //SKX PCH-Server GPP_A + {PID_GPIOCOM0, R_PCH_H_PCR_GPIO_GPP_B_PAD_OWN, R_PCH_PCR_GPIO_GPP_B_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_B_GPI_IS, R_PCH_PCR_GPIO_GPP_B_GPI_IE, R_PCH_PCR_GPIO_GPP_B_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_B_GPI_GPE_EN, R_PCH_PCR_GPIO_GPP_B_SMI_STS, R_PCH_PCR_GPIO_GPP_B_SMI_EN, R_PCH_PCR_GPIO_GPP_B_NMI_STS, R_PCH_PCR_GPIO_GPP_B_NMI_EN, R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_B_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET, V_PCH_GPIO_GPP_B_PAD_MAX}, //SKX PCH-Server GPP_B + {PID_GPIOCOM1, R_PCH_H_PCR_GPIO_GPP_C_PAD_OWN, R_PCH_PCR_GPIO_GPP_C_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_C_GPI_IS, R_PCH_PCR_GPIO_GPP_C_GPI_IE, R_PCH_PCR_GPIO_GPP_C_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_C_GPI_GPE_EN, R_PCH_PCR_GPIO_GPP_C_SMI_STS, R_PCH_PCR_GPIO_GPP_C_SMI_EN, R_PCH_PCR_GPIO_GPP_C_NMI_STS, R_PCH_PCR_GPIO_GPP_C_NMI_EN, R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_C_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET, V_PCH_GPIO_GPP_C_PAD_MAX}, //SKX PCH-Server GPP_C + {PID_GPIOCOM1, R_PCH_H_PCR_GPIO_GPP_D_PAD_OWN, R_PCH_PCR_GPIO_GPP_D_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_D_GPI_IS, R_PCH_PCR_GPIO_GPP_D_GPI_IE, R_PCH_PCR_GPIO_GPP_D_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_D_GPI_GPE_EN, R_PCH_PCR_GPIO_GPP_D_SMI_STS, R_PCH_PCR_GPIO_GPP_D_SMI_EN, R_PCH_PCR_GPIO_GPP_D_NMI_STS, R_PCH_PCR_GPIO_GPP_D_NMI_EN, R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_D_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET, V_PCH_GPIO_GPP_D_PAD_MAX}, //SKX PCH-Server GPP_D + {PID_GPIOCOM1, R_PCH_H_PCR_GPIO_GPP_E_PAD_OWN, R_PCH_PCR_GPIO_GPP_E_HOSTSW_OWN, R_PCH_PCR_GPIO_GPP_E_GPI_IS, R_PCH_PCR_GPIO_GPP_E_GPI_IE, R_PCH_PCR_GPIO_GPP_E_GPI_GPE_STS, R_PCH_PCR_GPIO_GPP_E_GPI_GPE_EN, R_PCH_PCR_GPIO_GPP_E_SMI_STS, R_PCH_PCR_GPIO_GPP_E_SMI_EN, R_PCH_PCR_GPIO_GPP_E_NMI_STS, R_PCH_PCR_GPIO_GPP_E_NMI_EN, R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_E_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_E_PAD_MAX}, //SKX PCH-Server GPP_E + {PID_GPIOCOM0, R_PCH_H_PCR_GPIO_GPP_F_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_F_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_F_GPI_IS, R_PCH_H_PCR_GPIO_GPP_F_GPI_IE, R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_F_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_F_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_F_PADCFG_OFFSET, V_PCH_GPIO_GPP_F_PAD_MAX}, //SKX PCH-Server GPP_F + {PID_GPIOCOM5, R_PCH_H_PCR_GPIO_GPP_G_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_G_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_G_GPI_IS, R_PCH_H_PCR_GPIO_GPP_G_GPI_IE, R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_G_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_G_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_G_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_G_PAD_MAX}, //SKX PCH-Server GPP_G + {PID_GPIOCOM5, R_PCH_H_PCR_GPIO_GPP_H_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_H_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_H_GPI_IS, R_PCH_H_PCR_GPIO_GPP_H_GPI_IE, R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_H_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_H_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_H_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_H_PAD_MAX}, //SKX PCH-Server GPP_H + {PID_GPIOCOM3, R_PCH_H_PCR_GPIO_GPP_I_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_I_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_I_GPI_IS, R_PCH_H_PCR_GPIO_GPP_I_GPI_IE, R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_I_GPI_GPE_EN, R_PCH_H_PCR_GPIO_GPP_I_SMI_STS,R_PCH_H_PCR_GPIO_GPP_I_SMI_EN, R_PCH_H_PCR_GPIO_GPP_I_NMI_STS,R_PCH_H_PCR_GPIO_GPP_I_NMI_EN, R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_I_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_I_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_I_PAD_MAX}, //SKX PCH-Server GPP_I + {PID_GPIOCOM4, R_PCH_H_PCR_GPIO_GPP_J_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_J_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_J_GPI_IS, R_PCH_H_PCR_GPIO_GPP_J_GPI_IE, R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_J_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_J_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_J_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_J_PAD_MAX}, //SKX PCH-Server GPP_J + {PID_GPIOCOM4, R_PCH_H_PCR_GPIO_GPP_K_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_K_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_K_GPI_IS, R_PCH_H_PCR_GPIO_GPP_K_GPI_IE, R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_K_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_K_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_K_PAD_MAX}, //SKX PCH-Server GPP_K + {PID_GPIOCOM5, R_PCH_H_PCR_GPIO_GPP_L_PAD_OWN, R_PCH_H_PCR_GPIO_GPP_L_HOSTSW_OWN, R_PCH_H_PCR_GPIO_GPP_L_GPI_IS, R_PCH_H_PCR_GPIO_GPP_L_GPI_IE, R_PCH_H_PCR_GPIO_GPP_K_GPI_GPE_STS, R_PCH_H_PCR_GPIO_GPP_L_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPP_L_PADCFGLOCKTX, R_PCH_H_PCR_GPIO_GPP_L_PADCFG_OFFSET, V_PCH_H_GPIO_GPP_L_PAD_MAX}, //SKX PCH-Server GPP_L + {PID_GPIOCOM2, R_PCH_H_PCR_GPIO_GPD_PAD_OWN, R_PCH_PCR_GPIO_GPD_HOSTSW_OWN, R_PCH_PCR_GPIO_GPD_GPI_IS, R_PCH_PCR_GPIO_GPD_GPI_IE, R_PCH_PCR_GPIO_GPD_GPI_GPE_STS, R_PCH_PCR_GPIO_GPD_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_PCH_H_PCR_GPIO_GPD_PADCFGLOCK, R_PCH_H_PCR_GPIO_GPD_PADCFGLOCKTX, R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET, V_PCH_GPIO_GPD_PAD_MAX} //SKX PCH-Server GPD +}; + + +// +// SATA reset port to GPIO pin mapping +// SATAGP_x -> GPIO pin y +// + +GPIO_PAD_NATIVE_FUNCTION mPchHSataPortResetToGpioMap[PCH_H_AHCI_MAX_PORTS] = +{ + {GPIO_SKL_H_GPP_E0, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_E1, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_E2, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F0, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F1, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F2, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F3, GpioPadModeNative2}, + {GPIO_SKL_H_GPP_F4, GpioPadModeNative2} +}; + +// +// SATADevSlpPin to GPIO pin mapping +// SATA_DEVSLP_x -> GPIO pin y +// + +GPIO_PAD_NATIVE_FUNCTION mPchHSataDevSlpPinToGpioMap[PCH_H_AHCI_MAX_PORTS] = +{ + {GPIO_SKL_H_GPP_E4, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_E5, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_E6, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F5, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F6, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F7, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F8, GpioPadModeNative1}, + {GPIO_SKL_H_GPP_F9, GpioPadModeNative1} +}; |