diff options
Diffstat (limited to 'Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib')
5 files changed, 1623 insertions, 0 deletions
diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PchPrintPolicy.c b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PchPrintPolicy.c new file mode 100644 index 0000000000..a555ff9c6e --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PchPrintPolicy.c @@ -0,0 +1,736 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPchPolicyLibrary.h" + +/** + Print PCH_USB_CONFIG and serial out. + + @param[in] UsbConfig Pointer to a PCH_USB_CONFIG that provides the platform setting + +**/ +VOID +PchPrintUsbConfig ( + IN CONST PCH_USB_CONFIG *UsbConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH USB Config ------------------\n")); + DEBUG ((DEBUG_INFO, " UsbPrecondition= %x\n", UsbConfig->UsbPrecondition)); + DEBUG ((DEBUG_INFO, " DisableComplianceMode= %x\n", UsbConfig->DisableComplianceMode)); + + for (i = 0; i < GetPchUsbMaxPhysicalPortNum (); i++) { + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Enabled= %x\n", i, UsbConfig->PortUsb20[i].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].OverCurrentPin= OC%x\n", i, UsbConfig->PortUsb20[i].OverCurrentPin)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Petxiset= %x\n", i, UsbConfig->PortUsb20[i].Afe.Petxiset)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Txiset= %x\n", i, UsbConfig->PortUsb20[i].Afe.Txiset)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Predeemp= %x\n", i, UsbConfig->PortUsb20[i].Afe.Predeemp)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Pehalfbit= %x\n", i, UsbConfig->PortUsb20[i].Afe.Pehalfbit)); + } + + for (i = 0; i < GetPchXhciMaxUsb3PortNum (); i++) { + DEBUG ((DEBUG_INFO, " PortUsb30[%d] Enabled= %x\n", i, UsbConfig->PortUsb30[i].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].OverCurrentPin= OC%x\n", i, UsbConfig->PortUsb30[i].OverCurrentPin)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmph = %x\n", i, UsbConfig->PortUsb30[i].HsioTxDeEmph)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmphEnable = %x\n", i, UsbConfig->PortUsb30[i].HsioTxDeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmp = %x\n", i, UsbConfig->PortUsb30[i].HsioTxDownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmpEnable = %x\n", i, UsbConfig->PortUsb30[i].HsioTxDownscaleAmpEnable)); + } + + DEBUG ((DEBUG_INFO, " XdciConfig.Enable= %x\n", UsbConfig->XdciConfig.Enable)); + + for (i = 0; i < PCH_XHCI_MAX_SSIC_PORT_COUNT; i++) { + DEBUG ((DEBUG_INFO, " SsicPort[%d].Enable = %x\n", i, UsbConfig->SsicConfig.SsicPort[i].Enable)); + } + +} + +/** + Print PCH_PCIE_CONFIG and serial out. + + @param[in] PcieConfig Pointer to a PCH_PCIE_CONFIG that provides the platform setting + @param[in] HsioPcieConfig Pointer to a PCH_HSIO_PCIE_CONFIG that provides the platform setting + +**/ +VOID +PchPrintPcieConfig ( + IN CONST PCH_PCIE_CONFIG *PcieConfig, + IN CONST PCH_HSIO_PCIE_CONFIG *HsioPcieConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH PCIE Config ------------------\n")); + for (i = 0; i < GetPchMaxPciePortNum (); i++) { + DEBUG ((DEBUG_INFO, " RootPort[%d] Enabled= %x\n", i, PcieConfig->RootPort[i].Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HotPlug= %x\n", i, PcieConfig->RootPort[i].HotPlug)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PmSci= %x\n", i, PcieConfig->RootPort[i].PmSci)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ExtSync= %x\n", i, PcieConfig->RootPort[i].ExtSync)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqSupported= %x\n", i, PcieConfig->RootPort[i].ClkReqSupported)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqNumber= %x\n", i, PcieConfig->RootPort[i].ClkReqNumber)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqDetect= %x\n", i, PcieConfig->RootPort[i].ClkReqDetect)); + DEBUG ((DEBUG_INFO, " RootPort[%d] UnsupportedRequestReport= %x\n", i, PcieConfig->RootPort[i].UnsupportedRequestReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] FatalErrorReport= %x\n", i, PcieConfig->RootPort[i].FatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NoFatalErrorReport= %x\n", i, PcieConfig->RootPort[i].NoFatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CorrectableErrorReport= %x\n", i, PcieConfig->RootPort[i].CorrectableErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnFatalError= %x\n", i, PcieConfig->RootPort[i].SystemErrorOnFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnNonFatalError= %x\n", i, PcieConfig->RootPort[i].SystemErrorOnNonFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnCorrectableError= %x\n", i, PcieConfig->RootPort[i].SystemErrorOnCorrectableError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] MaxPayload= %x\n", i, PcieConfig->RootPort[i].MaxPayload)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AcsEnabled= %x\n", i, PcieConfig->RootPort[i].AcsEnabled)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AdvancedErrorReporting= %x\n", i, PcieConfig->RootPort[i].AdvancedErrorReporting)); + DEBUG ((DEBUG_INFO, " RootPort[%d] TransmitterHalfSwing= %x\n", i, PcieConfig->RootPort[i].TransmitterHalfSwing)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PcieSpeed= %x\n", i, PcieConfig->RootPort[i].PcieSpeed)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3EqPh3Method= %x\n", i, PcieConfig->RootPort[i].Gen3EqPh3Method)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PhysicalSlotNumber= %x\n", i, PcieConfig->RootPort[i].PhysicalSlotNumber)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CompletionTimeout= %x\n", i, PcieConfig->RootPort[i].CompletionTimeout)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Aspm= %x\n", i, PcieConfig->RootPort[i].Aspm)); + DEBUG ((DEBUG_INFO, " RootPort[%d] L1Substates= %x\n", i, PcieConfig->RootPort[i].L1Substates)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrEnable= %x\n", i, PcieConfig->RootPort[i].LtrEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrConfigLock= %x\n", i, PcieConfig->RootPort[i].LtrConfigLock)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxSnoopLatency= %x\n", i, PcieConfig->RootPort[i].LtrMaxSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxNoSnoopLatency= %x\n", i, PcieConfig->RootPort[i].LtrMaxNoSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMode= %x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMultiplier= %x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideMultiplier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideValue= %x\n", i, PcieConfig->RootPort[i].SnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMode= %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMultiplier= %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideMultiplier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideValue= %x\n", i, PcieConfig->RootPort[i].NonSnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitScale= %x\n", i, PcieConfig->RootPort[i].SlotPowerLimitScale)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitValue= %x\n", i, PcieConfig->RootPort[i].SlotPowerLimitValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Uptp= %x\n", i, PcieConfig->RootPort[i].Uptp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Dptp= %x\n", i, PcieConfig->RootPort[i].Dptp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtleEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioRxSetCtleEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtle= %x\n", i, HsioPcieConfig->Lane[i].HsioRxSetCtle)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmpEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen1DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmp= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen1DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmpEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmp= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmpEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen3DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmp= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen3DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmphEnable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen1DeEmphEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmph= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen1DeEmph)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5Enable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph3p5Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph3p5)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0Enable= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph6p0Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0= %x\n", i, HsioPcieConfig->Lane[i].HsioTxGen2DeEmph6p0)); + + } + DEBUG ((DEBUG_INFO, " EnablePort8xhDecode= %x\n", PcieConfig->EnablePort8xhDecode)); + DEBUG ((DEBUG_INFO, " PchPciePort8xhDecodePortIndex= %x\n", PcieConfig->PchPciePort8xhDecodePortIndex)); + DEBUG ((DEBUG_INFO, " DisableRootPortClockGating= %x\n", PcieConfig->DisableRootPortClockGating)); + DEBUG ((DEBUG_INFO, " EnablePeerMemoryWrite= %x\n", PcieConfig->EnablePeerMemoryWrite)); + DEBUG ((DEBUG_INFO, " AllowNoLtrIccPllShutdown= %x\n", PcieConfig->AllowNoLtrIccPllShutdown)); + DEBUG ((DEBUG_INFO, " ComplianceTestMode= %x\n", PcieConfig->ComplianceTestMode)); + DEBUG ((DEBUG_INFO, " RpFunctionSwap= %x\n", PcieConfig->RpFunctionSwap)); +} + +/** + Print PCH_PCIE_CONFIG2 and serial out. + + @param[in] PcieConfig2 Pointer to a PCH_PCIE_CONFIG2 that provides the platform setting + +**/ +VOID +PchPrintPcieConfig2 ( + IN CONST PCH_PCIE_CONFIG2 *PcieConfig2 + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ PCH PCIE Config2 -----------------\n")); + for (Index = 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + DEBUG ((DEBUG_INFO, " SwEqCoeffCm[%d] = %x\n", Index, PcieConfig2->SwEqCoeffList[Index].Cm)); + DEBUG ((DEBUG_INFO, " SwEqCoeffCp[%d] = %x\n", Index, PcieConfig2->SwEqCoeffList[Index].Cp)); + } +} + +/** + Print PCH_SATA_CONFIG and serial out. + + @param[in] SataConfig Pointer to a PCH_SATA_CONFIG that provides the platform setting + @param[in] HsioSataConfig Pointer to a PCH_HSIO_SATA_CONFIG that provides the platform setting + +**/ +VOID +PchPrintSataConfig ( + IN CONST PCH_SATA_CONFIG *SataConfig, + IN VOID *HsioSataConfigPtr, + IN UINT8 SataControllerNo + ) +{ + UINT32 i; + + UINT32 MaxSataPortNum; + PCH_HSIO_SATA_CONFIG *HsioSataConfig; + + HsioSataConfig = HsioSataConfigPtr; + + if (SataControllerNo == PCH_SATA_FIRST_CONTROLLER) { + DEBUG ((DEBUG_INFO, "------------------- PCH Primary SATA Config ------------------\n")); + MaxSataPortNum = GetPchMaxSataPortNum (); + } else { + DEBUG ((DEBUG_INFO, "------------------ PCH Secondary SATA Config ------------------\n")); + MaxSataPortNum = GetPchMaxsSataPortNum (); + } + DEBUG ((DEBUG_INFO, " Enable= %x\n", SataConfig->Enable)); + DEBUG ((DEBUG_INFO, " SataMode= %x\n", SataConfig->SataMode)); + + + for (i = 0; i < MaxSataPortNum; i++) { + DEBUG ((DEBUG_INFO, " PortSettings[%d] Enabled= %x\n", i, SataConfig->PortSettings[i].Enable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HotPlug= %x\n", i, SataConfig->PortSettings[i].HotPlug)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] InterlockSw= %x\n", i, SataConfig->PortSettings[i].InterlockSw)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] External= %x\n", i, SataConfig->PortSettings[i].External)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SpinUp= %x\n", i, SataConfig->PortSettings[i].SpinUp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SolidStateDrive= %x\n", i, SataConfig->PortSettings[i].SolidStateDrive)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DevSlp= %x\n", i, SataConfig->PortSettings[i].DevSlp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] EnableDitoConfig= %x\n", i, SataConfig->PortSettings[i].EnableDitoConfig)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DmVal= %x\n", i, SataConfig->PortSettings[i].DmVal)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DitoVal= %x\n", i, SataConfig->PortSettings[i].DitoVal)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] ZpOdd= %x\n", i, SataConfig->PortSettings[i].ZpOdd)); + + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMagEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen1EqBoostMagEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMag= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen1EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMagEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen2EqBoostMagEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMag= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen2EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMagEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen3EqBoostMagEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMag= %x\n", i, HsioSataConfig->PortLane[i].HsioRxGen3EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmpEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen1DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmp= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen1DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmpEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen2DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmp= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen2DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmpEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen3DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmp= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen3DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmphEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen1DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmph= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen1DeEmph)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmphEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen2DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmph= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen2DeEmph)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmphEnable= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen3DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmph= %x\n", i, HsioSataConfig->PortLane[i].HsioTxGen3DeEmph)); + } + + DEBUG ((DEBUG_INFO, " RaidAlternateId= %x\n", SataConfig->Rst.RaidAlternateId)); + DEBUG ((DEBUG_INFO, " Raid0= %x\n", SataConfig->Rst.Raid0)); + DEBUG ((DEBUG_INFO, " Raid1= %x\n", SataConfig->Rst.Raid1)); + DEBUG ((DEBUG_INFO, " Raid10= %x\n", SataConfig->Rst.Raid10)); + DEBUG ((DEBUG_INFO, " Raid5= %x\n", SataConfig->Rst.Raid5)); + DEBUG ((DEBUG_INFO, " Irrt= %x\n", SataConfig->Rst.Irrt)); + DEBUG ((DEBUG_INFO, " OromUiBanner= %x\n", SataConfig->Rst.OromUiBanner)); + DEBUG ((DEBUG_INFO, " OromUiDelay= %x\n", SataConfig->Rst.OromUiDelay)); + DEBUG ((DEBUG_INFO, " HddUnlock= %x\n", SataConfig->Rst.HddUnlock)); + DEBUG ((DEBUG_INFO, " LedLocate= %x\n", SataConfig->Rst.LedLocate)); + DEBUG ((DEBUG_INFO, " IrrtOnly= %x\n", SataConfig->Rst.IrrtOnly)); + DEBUG ((DEBUG_INFO, " SmartStorage= %x\n", SataConfig->Rst.SmartStorage)); + + DEBUG ((DEBUG_INFO, " SpeedSupport= %x\n", SataConfig->SpeedLimit)); + DEBUG ((DEBUG_INFO, " eSATASpeedLimit= %x\n", SataConfig->eSATASpeedLimit)); + DEBUG ((DEBUG_INFO, " TestMode= %x\n", SataConfig->TestMode)); + DEBUG ((DEBUG_INFO, " SalpSupport= %x\n", SataConfig->SalpSupport)); + DEBUG ((DEBUG_INFO, " PwrOptEnable= %x\n", SataConfig->PwrOptEnable)); + + for (i = 0; i < PCH_MAX_RST_PCIE_STORAGE_CR; i++) { + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].Enable = %x\n", i, SataConfig->RstPcieStorageRemap[i].Enable)); + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].RstPcieStoragePort = %x\n", i, SataConfig->RstPcieStorageRemap[i].RstPcieStoragePort)); + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].DeviceResetDelay = %x\n", i, SataConfig->RstPcieStorageRemap[i].DeviceResetDelay)); + } +} + +/** + Print PCH_IOAPIC_CONFIG and serial out. + + @param[in] IoApicConfig Pointer to a PCH_IOAPIC_CONFIG that provides the platform setting + +**/ +VOID +PchPrintIoApicConfig ( + IN CONST PCH_IOAPIC_CONFIG *IoApicConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH IOAPIC Config ------------------\n")); + DEBUG ((DEBUG_INFO, " BdfValid= %x\n", IoApicConfig->BdfValid)); + DEBUG ((DEBUG_INFO, " BusNumber= %x\n", IoApicConfig->BusNumber)); + DEBUG ((DEBUG_INFO, " DeviceNumber= %x\n", IoApicConfig->DeviceNumber)); + DEBUG ((DEBUG_INFO, " FunctionNumber= %x\n", IoApicConfig->FunctionNumber)); + DEBUG ((DEBUG_INFO, " IoApicId= %x\n", IoApicConfig->IoApicId)); + DEBUG ((DEBUG_INFO, " ApicRangeSelect= %x\n", IoApicConfig->ApicRangeSelect)); + DEBUG ((DEBUG_INFO, " IoApicEntry24_119= %x\n", IoApicConfig->IoApicEntry24_119)); +} + +/** + Print PCH_HPET_CONFIG and serial out. + + @param[in] HpetConfig Pointer to a PCH_HPET_CONFIG that provides the platform setting + +**/ +VOID +PchPrintHpetConfig ( + IN CONST PCH_HPET_CONFIG *HpetConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH HPET Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable %x\n", HpetConfig->Enable)); + DEBUG ((DEBUG_INFO, " BdfValid %x\n", HpetConfig->BdfValid)); + DEBUG ((DEBUG_INFO, " BusNumber %x\n", HpetConfig->BusNumber)); + DEBUG ((DEBUG_INFO, " DeviceNumber %x\n", HpetConfig->DeviceNumber)); + DEBUG ((DEBUG_INFO, " FunctionNumber %x\n", HpetConfig->FunctionNumber)); + DEBUG ((DEBUG_INFO, " Base %x\n", HpetConfig->Base)); +} + +/** + Print PCH_LOCK_DOWN_CONFIG and serial out. + + @param[in] LockDownConfig Pointer to a PCH_LOCK_DOWN_CONFIG that provides the platform setting + +**/ +VOID +PchPrintLockDownConfig ( + IN CONST PCH_LOCK_DOWN_CONFIG *LockDownConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH Lock Down Config ------------------\n")); + DEBUG ((DEBUG_INFO, " GlobalSmi= %x\n", LockDownConfig->GlobalSmi)); + DEBUG ((DEBUG_INFO, " BiosInterface= %x\n", LockDownConfig->BiosInterface)); + DEBUG ((DEBUG_INFO, " RtcLock= %x\n", LockDownConfig->RtcLock)); + DEBUG ((DEBUG_INFO, " BiosLock= %x\n", LockDownConfig->BiosLock)); + DEBUG ((DEBUG_INFO, " SpiEiss= %x\n", LockDownConfig->SpiEiss)); +} + +/** + Print PCH_SMBUS_CONFIG and serial out. + + @param[in] SmbusConfig Pointer to a PCH_SMBUS_CONFIG that provides the platform setting + +**/ +VOID +PchPrintSmbusConfig ( + IN CONST PCH_SMBUS_CONFIG *SmbusConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH SMBUS Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable= %x\n", SmbusConfig->Enable)); + DEBUG ((DEBUG_INFO, " ArpEnable= %x\n", SmbusConfig->ArpEnable)); + DEBUG ((DEBUG_INFO, " DynamicPowerGating= %x\n", SmbusConfig->DynamicPowerGating)); + DEBUG ((DEBUG_INFO, " SmbusIoBase= %x\n", SmbusConfig->SmbusIoBase)); + DEBUG ((DEBUG_INFO, " NumRsvdSmbusAddresses= %x\n", SmbusConfig->NumRsvdSmbusAddresses)); + DEBUG ((DEBUG_INFO, " RsvdSmbusAddressTable= {")); + for (i = 0; i < SmbusConfig->NumRsvdSmbusAddresses; ++i) { + DEBUG ((DEBUG_INFO, " %02xh", SmbusConfig->RsvdSmbusAddressTable[i])); + } + DEBUG ((DEBUG_INFO, " }\n")); +} + +/** + Print PCH_HDAUDIO_CONFIG and serial out. + + @param[in] HdaConfig Pointer to a PCH_HDAUDIO_CONFIG that provides the platform setting + +**/ +VOID +PchPrintHdAudioConfig ( + IN CONST PCH_HDAUDIO_CONFIG *HdaConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH HD-Audio Config ------------------\n")); + DEBUG ((DEBUG_INFO, " HDA Enable = %x\n", HdaConfig->Enable)); + DEBUG ((DEBUG_INFO, " DSP Enable = %x\n", HdaConfig->DspEnable)); + DEBUG ((DEBUG_INFO, " DSP UAA Compliance = %x\n", HdaConfig->DspUaaCompliance)); + DEBUG ((DEBUG_INFO, " iDisp Codec Disconnect = %x\n", HdaConfig->IDispCodecDisconnect)); + DEBUG ((DEBUG_INFO, " Pme = %x\n", HdaConfig->Pme)); + DEBUG ((DEBUG_INFO, " I/O Buffer Ownership = %x\n", HdaConfig->IoBufferOwnership)); + DEBUG ((DEBUG_INFO, " I/O Buffer Voltage = %x\n", HdaConfig->IoBufferVoltage)); + DEBUG ((DEBUG_INFO, " VC Type = %x\n", HdaConfig->VcType)); + DEBUG ((DEBUG_INFO, " HD-A Link Frequency = %x\n", HdaConfig->HdAudioLinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link Frequency = %x\n", HdaConfig->IDispLinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link T-Mode = %x\n", HdaConfig->IDispLinkTmode)); + DEBUG ((DEBUG_INFO, " DSP Endpoint DMIC = %x\n", HdaConfig->DspEndpointDmic)); + DEBUG ((DEBUG_INFO, " DSP Endpoint I2S = %x\n", HdaConfig->DspEndpointI2s)); + DEBUG ((DEBUG_INFO, " DSP Endpoint BT = %x\n", HdaConfig->DspEndpointBluetooth)); + DEBUG ((DEBUG_INFO, " DSP Feature Mask = %x\n", HdaConfig->DspFeatureMask)); + DEBUG ((DEBUG_INFO, " DSP PP Module Mask = %x\n", HdaConfig->DspPpModuleMask)); + DEBUG ((DEBUG_INFO, " ResetWaitTimer = %x\n", HdaConfig->ResetWaitTimer)); +} + +/** + Print PCH_PM_CONFIG and serial out. + + @param[in] PmConfig Pointer to a PCH_PM_CONFIG that provides the platform setting + +**/ +VOID +PchPrintPmConfig ( + IN CONST PCH_PM_CONFIG *PmConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH PM Config ------------------\n")); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeWakeSts = %x\n", PmConfig->PowerResetStatusClear.MeWakeSts)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeHrstColdSts = %x\n", PmConfig->PowerResetStatusClear.MeHrstColdSts)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeHrstWarmSts = %x\n", PmConfig->PowerResetStatusClear.MeHrstWarmSts)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear MeHostPowerDn = %x\n", PmConfig->PowerResetStatusClear.MeHostPowerDn)); + DEBUG ((DEBUG_INFO, " PowerResetStatusClear WolOvrWkSts = %x\n", PmConfig->PowerResetStatusClear.WolOvrWkSts)); + + DEBUG ((DEBUG_INFO, " WakeConfig PmeB0S5Dis = %x\n", PmConfig->WakeConfig.PmeB0S5Dis)); + DEBUG ((DEBUG_INFO, " WakeConfig WolEnableOverride = %x\n", PmConfig->WakeConfig.WolEnableOverride)); + DEBUG ((DEBUG_INFO, " WakeConfig LanWakeFromDeepSx = %x\n", PmConfig->WakeConfig.LanWakeFromDeepSx)); + DEBUG ((DEBUG_INFO, " WakeConfig PcieWakeFromDeepSx = %x\n", PmConfig->WakeConfig.PcieWakeFromDeepSx)); + DEBUG ((DEBUG_INFO, " WakeConfig WoWlanEnable = %x\n", PmConfig->WakeConfig.WoWlanEnable)); + DEBUG ((DEBUG_INFO, " WakeConfig WoWlanDeepSxEnable = %x\n", PmConfig->WakeConfig.WoWlanDeepSxEnable)); + + DEBUG ((DEBUG_INFO, " PchDeepSxPol = %x\n", PmConfig->PchDeepSxPol)); + DEBUG ((DEBUG_INFO, " PchSlpS3MinAssert = %x\n", PmConfig->PchSlpS3MinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpS4MinAssert = %x\n", PmConfig->PchSlpS4MinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpSusMinAssert = %x\n", PmConfig->PchSlpSusMinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpAMinAssert = %x\n", PmConfig->PchSlpAMinAssert)); + DEBUG ((DEBUG_INFO, " PciClockRun = %x\n", PmConfig->PciClockRun)); + DEBUG ((DEBUG_INFO, " SlpStrchSusUp = %x\n", PmConfig->SlpStrchSusUp)); + DEBUG ((DEBUG_INFO, " SlpLanLowDc = %x\n", PmConfig->SlpLanLowDc)); + DEBUG ((DEBUG_INFO, " PwrBtnOverridePeriod = %x\n", PmConfig->PwrBtnOverridePeriod)); + DEBUG ((DEBUG_INFO, " DisableEnergyReport = %x\n", PmConfig->DisableEnergyReport)); + DEBUG ((DEBUG_INFO, " DisableDsxAcPresentPulldown = %x\n", PmConfig->DisableDsxAcPresentPulldown)); + DEBUG ((DEBUG_INFO, " PmcReadDisable = %x\n", PmConfig->PmcReadDisable)); + DEBUG ((DEBUG_INFO, " PchPwrCycDur = %x\n", PmConfig->PchPwrCycDur)); + DEBUG ((DEBUG_INFO, " PciePllSsc = %x\n", PmConfig->PciePllSsc)); + DEBUG ((DEBUG_INFO, " CapsuleResetType = %x\n", PmConfig->CapsuleResetType)); + DEBUG ((DEBUG_INFO, " DisableNativePowerButton = %x\n", PmConfig->DisableNativePowerButton)); + DEBUG ((DEBUG_INFO, " SlpS0Enabled = %x\n", PmConfig->SlpS0Enable)); +} + +/** + Print PCH_DMI_CONFIG and serial out. + + @param[in] DmiConfig Pointer to a PCH_DMI_CONFIG that provides the platform setting + +**/ +VOID +PchPrintDmiConfig ( + IN CONST PCH_DMI_CONFIG *DmiConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH DMI Config ------------------\n")); + DEBUG ((DEBUG_INFO, " DmiAspm= %x\n", DmiConfig->DmiAspm)); + DEBUG ((DEBUG_INFO, " PwrOptEnable= %x\n", DmiConfig->PwrOptEnable)); + +} + +/** + Print PCH_LPC_SIRQ_CONFIG and serial out. + + @param[in] SerialIrqConfig Pointer to a PCH_LPC_SIRQ_CONFIG that provides the platform setting + +**/ +VOID +PchPrintSerialIrqConfig ( + IN CONST PCH_LPC_SIRQ_CONFIG *SerialIrqConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LPC SIRQ Config ------------------\n")); + DEBUG ((DEBUG_INFO, " SirqEnable= %x\n", SerialIrqConfig->SirqEnable)); + DEBUG ((DEBUG_INFO, " SirqMode= %x\n", SerialIrqConfig->SirqMode)); + DEBUG ((DEBUG_INFO, " StartFramePulse= %x\n", SerialIrqConfig->StartFramePulse)); +} + +/** + Print PCH_THERMAL_CONFIG and serial out. + + @param[in] ThermalConfig Pointer to a PCH_THERMAL_CONFIG that provides the platform setting + +**/ +VOID +PchPrintThermalConfig ( + IN CONST PCH_THERMAL_CONFIG *ThermalConfig + ) +{ + UINTN i; + + DEBUG ((DEBUG_INFO, "------------------ PCH Thermal Config ------------------\n")); + DEBUG ((DEBUG_INFO, " TsmicLock= %x\n", ThermalConfig->TsmicLock)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels T0Level %x centigrade degree\n", ThermalConfig->ThermalThrottling.TTLevels.T0Level)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels T1Level %x centigrade degree\n", ThermalConfig->ThermalThrottling.TTLevels.T1Level)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels T2Level %x centigrade degree\n", ThermalConfig->ThermalThrottling.TTLevels.T2Level)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels TTEnable %x\n", ThermalConfig->ThermalThrottling.TTLevels.TTEnable)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels TTState13Enable %x\n", ThermalConfig->ThermalThrottling.TTLevels.TTState13Enable)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels TTLock %x\n", ThermalConfig->ThermalThrottling.TTLevels.TTLock)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels SuggestedSetting %x\n", ThermalConfig->ThermalThrottling.TTLevels.SuggestedSetting)); + DEBUG ((DEBUG_INFO, " ThermalThrottling TTLevels PchCrossThrottling %x\n", ThermalConfig->ThermalThrottling.TTLevels.PchCrossThrottling)); + + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC DmiTsawEn %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.DmiTsawEn)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS0TW %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.TS0TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS1TW %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.TS1TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS2TW %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.TS2TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC TS3TW %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.TS3TW)); + DEBUG ((DEBUG_INFO, " ThermalThrottling DmiHaAWC SuggestedSetting %x\n", ThermalConfig->ThermalThrottling.DmiHaAWC.SuggestedSetting)); + + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0T1M %x\n", ThermalConfig->ThermalThrottling.SataTT.P0T1M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0T2M %x\n", ThermalConfig->ThermalThrottling.SataTT.P0T2M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0T3M %x\n", ThermalConfig->ThermalThrottling.SataTT.P0T3M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0TDisp %x\n", ThermalConfig->ThermalThrottling.SataTT.P0TDisp)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0Tinact %x\n", ThermalConfig->ThermalThrottling.SataTT.P0Tinact)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P0TDispFinit %x\n", ThermalConfig->ThermalThrottling.SataTT.P0TDispFinit)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1T1M %x\n", ThermalConfig->ThermalThrottling.SataTT.P1T1M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1T2M %x\n", ThermalConfig->ThermalThrottling.SataTT.P1T2M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1T3M %x\n", ThermalConfig->ThermalThrottling.SataTT.P1T3M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1TDisp %x\n", ThermalConfig->ThermalThrottling.SataTT.P1TDisp)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1Tinact %x\n", ThermalConfig->ThermalThrottling.SataTT.P1Tinact)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT P1TDispFinit %x\n", ThermalConfig->ThermalThrottling.SataTT.P1TDispFinit)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SataTT SuggestedSetting %x\n", ThermalConfig->ThermalThrottling.SataTT.SuggestedSetting)); + + DEBUG ((DEBUG_INFO, " MemoryThrottling Enable= %x\n", ThermalConfig->MemoryThrottling.Enable)); + for (i = 0; i < MaxTsGpioPin; i++) { + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PmsyncEnable= %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[i].PmsyncEnable)); + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting C0TransmitEnable= %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[i].C0TransmitEnable)); + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PinSelection= %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[i].PinSelection)); + } + DEBUG ((DEBUG_INFO, " PchHotLevel = %x\n", ThermalConfig->PchHotLevel)); + DEBUG ((DEBUG_INFO, " ThermalDeviceEnable %x\n", ThermalConfig->ThermalDeviceEnable)); +} + +/** + Print PCH_GENERAL_CONFIG and serial out. + + @param[in] PchConfig Pointer to a PCH_GENERAL_CONFIG that provides the platform setting + +**/ +VOID +PchPrintGeneralConfig ( + IN CONST PCH_GENERAL_CONFIG *PchConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH General Config ------------------\n")); + DEBUG ((DEBUG_INFO, " SubSystemVendorId= %x\n", PchConfig->SubSystemVendorId)); + DEBUG ((DEBUG_INFO, " SubSystemId= %x\n", PchConfig->SubSystemId)); + DEBUG ((DEBUG_INFO, " Crid= %x\n", PchConfig->Crid)); +} + +/** + Print PCH_LAN_CONFIG and serial out. + + @param[in] LanConfig Pointer to a PCH_LAN_CONFIG that provides the platform setting + +**/ +VOID +PchPrintLanConfig ( + IN CONST PCH_LAN_CONFIG *LanConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LAN Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Enable= %x\n", LanConfig->Enable)); + DEBUG ((DEBUG_INFO, " K1OffEnable= %x\n", LanConfig->K1OffEnable)); + DEBUG ((DEBUG_INFO, " ClkReqSupported= %d\n", LanConfig->ClkReqSupported)); + DEBUG ((DEBUG_INFO, " ClkReqNumber= %d\n", LanConfig->ClkReqNumber)); +} + + +/** + Print PCH_INTERRUPT_CONFIG and serial out + + @param[in] InterruptConfig Pointer to Interrupt Configuration structure + +**/ +VOID +PchPrintInterruptConfig ( + IN CONST PCH_INTERRUPT_CONFIG *InterruptConfig + ) +{ + UINTN i; + // + // Print interrupt information + // + DEBUG ((DEBUG_INFO, "------------------ PCH Interrupt Config ------------------\n")); + DEBUG ((DEBUG_INFO, " Interrupt assignment:\n")); + DEBUG ((DEBUG_INFO, " Dxx:Fx INTx IRQ\n")); + for (i = 0; i < InterruptConfig->NumOfDevIntConfig; i++) { + DEBUG ((DEBUG_INFO, " D%02d:F%d %d %03d\n", + InterruptConfig->DevIntConfig[i].Device, + InterruptConfig->DevIntConfig[i].Function, + InterruptConfig->DevIntConfig[i].IntX, + InterruptConfig->DevIntConfig[i].Irq)); + } + DEBUG ((DEBUG_INFO, " Legacy PIC interrupt routing:\n")); + DEBUG ((DEBUG_INFO, " PIRQx IRQx\n")); + for (i = 0; i < PCH_MAX_PXRC_CONFIG; i++) { + DEBUG ((DEBUG_INFO, " PIRQ%c -> IRQ%d\n", i + 65, InterruptConfig->PxRcConfig[i])); + } + DEBUG ((DEBUG_INFO, " Other interrupt configuration:\n")); + DEBUG ((DEBUG_INFO, " GpioIrqRoute= %d\n", InterruptConfig->GpioIrqRoute)); + DEBUG ((DEBUG_INFO, " SciIrqSelect= %d\n", InterruptConfig->SciIrqSelect)); + DEBUG ((DEBUG_INFO, " TcoIrqEnable= %d\n", InterruptConfig->TcoIrqEnable)); + DEBUG ((DEBUG_INFO, " TcoIrqSelect= %d\n", InterruptConfig->TcoIrqSelect)); +} + + +/** + Print PCH_FLASH_PROTECTION_CONFIG and serial out. + + @param[in] FlashProtectConfig Pointer to a PCH_FLASH_PROTECTION_CONFIG that provides the platform setting + +**/ +VOID +PchPrintFlashProtectionConfig ( + IN CONST PCH_FLASH_PROTECTION_CONFIG *FlashProtectConfig + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------ PCH Flash Protection Config ------------------\n")); + for (i = 0; i < PCH_FLASH_PROTECTED_RANGES; ++i) { + DEBUG ((DEBUG_INFO, " WriteProtectionEnable[%d]= %x\n", i, FlashProtectConfig->ProtectRange[i].WriteProtectionEnable)); + DEBUG ((DEBUG_INFO, " ReadProtectionEnable[%d]= %x\n", i, FlashProtectConfig->ProtectRange[i].ReadProtectionEnable)); + DEBUG ((DEBUG_INFO, " ProtectedRangeLimit[%d]= %x\n", i, FlashProtectConfig->ProtectRange[i].ProtectedRangeLimit)); + DEBUG ((DEBUG_INFO, " ProtectedRangeBase[%d]= %x\n", i, FlashProtectConfig->ProtectRange[i].ProtectedRangeBase)); + } +} + +/** + Print PCH_WDT_CONFIG and serial out. + + @param[in] WdtConfig Pointer to a PCH_WDT_CONFIG that provides the platform setting + +**/ +VOID +PchPrintWdtConfig ( + IN CONST PCH_WDT_CONFIG *WdtConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH WDT Config ------------------\n")); + DEBUG ((DEBUG_INFO, "DisableAndLock= %x\n", WdtConfig->DisableAndLock)); +} + +/** + Print PCH_P2SB_CONFIG and serial out. + + @param[in] P2sbConfig Pointer to a PCH_P2SB_CONFIG that provides the platform setting + +**/ +VOID +PchPrintP2sbConfig ( + IN CONST PCH_P2SB_CONFIG *P2sbConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH P2SB Config ------------------\n")); + DEBUG ((DEBUG_INFO, "SbiUnlock= %x\n", P2sbConfig->SbiUnlock)); + DEBUG ((DEBUG_INFO, "PsfUnlock= %x\n", P2sbConfig->PsfUnlock)); +} + +/** + Print PCH_DCI_CONFIG and serial out. + + @param[in] DciConfig Pointer to a PCH_DCI_CONFIG that provides the platform setting + +**/ +VOID +PchPrintDciConfig ( + IN CONST PCH_DCI_CONFIG *DciConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH DCI Config ------------------\n")); + DEBUG ((DEBUG_INFO, "DciEn= %x\n", DciConfig->DciEn)); + DEBUG ((DEBUG_INFO, "DciAutoDetect= %x\n", DciConfig->DciAutoDetect)); +} + +/** + Print PCH_LPC_CONFIG and serial out. + + @param[in] LpcConfig Pointer to a PCH_LPC_CONFIG that provides the platform setting + +**/ +VOID +PchPrintLpcConfig ( + IN CONST PCH_LPC_CONFIG *LpcConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LPC Config ------------------\n")); + DEBUG ((DEBUG_INFO, "EnhancePort8xhDecoding= %x\n", LpcConfig->EnhancePort8xhDecoding)); +} + +/** + Print PCH_SPI_CONFIG and serial out. + + @param[in] SpiConfig Pointer to a PCH_SPI_CONFIG that provides the platform setting + +**/ +VOID +PchPrintSpiConfig ( + IN CONST PCH_SPI_CONFIG *SpiConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH SPI Config ------------------\n")); + DEBUG ((DEBUG_INFO, "ShowSpiController= %x\n", SpiConfig->ShowSpiController)); +} + +/** + Print whole PCH_POLICY_PPI and serial out. + + @param[in] PchPolicyPpi The RC Policy PPI instance + +**/ +VOID +PchPrintPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ) +{ +DEBUG_CODE_BEGIN(); + DEBUG ((DEBUG_INFO, "------------------------ PCH Print Platform Protocol Start ------------------------\n")); + DEBUG ((DEBUG_INFO, " Revision= %x\n", PchPolicyPpi->Revision)); + DEBUG ((DEBUG_INFO, " Port80Route= %x\n", PchPolicyPpi->Port80Route)); + DEBUG ((DEBUG_INFO, " AcpiBase= %x\n", PchPolicyPpi->AcpiBase)); + + PchPrintGeneralConfig (&PchPolicyPpi->PchConfig); + + PchPrintPcieConfig (&PchPolicyPpi->PcieConfig, &PchPolicyPpi->HsioPcieConfig); + + PchPrintPcieConfig2 (&PchPolicyPpi->PcieConfig2); + + PchPrintSataConfig (&PchPolicyPpi->SataConfig, &PchPolicyPpi->HsioSataConfig, PCH_SATA_FIRST_CONTROLLER); + PchPrintSataConfig (&PchPolicyPpi->sSataConfig, &PchPolicyPpi->HsiosSataConfig, PCH_SATA_SECOND_CONTROLLER); + PchPrintUsbConfig (&PchPolicyPpi->UsbConfig); + + PchPrintIoApicConfig (&PchPolicyPpi->IoApicConfig); + + PchPrintHpetConfig (&PchPolicyPpi->HpetConfig); + + PchPrintHdAudioConfig (&PchPolicyPpi->HdAudioConfig); + + PchPrintLanConfig (&PchPolicyPpi->LanConfig); + + PchPrintSmbusConfig (&PchPolicyPpi->SmbusConfig); + + PchPrintLockDownConfig (&PchPolicyPpi->LockDownConfig); + + PchPrintThermalConfig (&PchPolicyPpi->ThermalConfig); + + PchPrintPmConfig (&PchPolicyPpi->PmConfig); + + PchPrintDmiConfig (&PchPolicyPpi->DmiConfig); + + PchPrintSerialIrqConfig (&PchPolicyPpi->SerialIrqConfig); + + + PchPrintFlashProtectionConfig (&PchPolicyPpi->FlashProtectConfig); + + PchPrintWdtConfig (&PchPolicyPpi->WdtConfig); + + PchPrintP2sbConfig (&PchPolicyPpi->P2sbConfig); + + PchPrintDciConfig (&PchPolicyPpi->DciConfig); + + PchPrintLpcConfig (&PchPolicyPpi->LpcConfig); + + PchPrintSpiConfig (&PchPolicyPpi->SpiConfig); + + DEBUG ((DEBUG_INFO, "------------------------ PCH Print Platform Protocol End --------------------------\n")); +DEBUG_CODE_END(); +} + diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.c new file mode 100644 index 0000000000..f5ec0d5fb1 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.c @@ -0,0 +1,587 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPchPolicyLibrary.h" +#include <Library/PchPmcLib.h> + +/** + mDevIntConfig[] table contains data on INTx and IRQ for each device. + IRQ value for devices which use ITSS INTx->PIRQx mapping need to be set in a way + that for each multifunctional Dxx:Fy same interrupt pins must map to the same IRQ. + Those IRQ values will be used to update ITSS.PIRx register. + In APIC relationship between PIRQs and IRQs is: + PIRQA -> IRQ16 + PIRQB -> IRQ17 + PIRQC -> IRQ18 + PIRQD -> IRQ19 + PIRQE -> IRQ20 + PIRQF -> IRQ21 + PIRQG -> IRQ22 + PIRQH -> IRQ23 + + Devices which use INTx->PIRQy mapping are: cAVS(in PCI mode), SMBus, GbE, TraceHub, PCIe, + SATA, HECI, IDE-R, KT Redirection, xHCI, Thermal Subsystem, Camera IO Host Controller + + PCI Express Root Ports mapping should be programmed only with values as in below table (D27/28/29) + otherwise _PRT methods in ACPI for RootPorts would require additional patching as + PCIe Endpoint Device Interrupt is further subjected to INTx to PIRQy Mapping + + Configured IRQ values are not used if an OS chooses to be in PIC instead of APIC mode +**/ +GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mDevIntConfig[] = { +// {31, 0, PchNoInt, 0}, // LPC/eSPI Interface, doesn't use interrupts +// {31, 1, PchNoInt, 0}, // P2SB, doesn't use interrupts +// {31, 2, PchNoInt, 0}, // PMC , doesn't use interrupts + {31, 3, PchIntA, 16}, // cAVS(Audio, Voice, Speach), INTA is default, programmed in PciCfgSpace 3Dh + {31, 4, PchIntA, 16}, // SMBus Controller, no default value, programmed in PciCfgSpace 3Dh +// {31, 5, PchNoInt, 0}, // SPI , doesn't use interrupts + {31, 6, PchIntA, 16}, // GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh + {31, 7, PchIntA, 16}, // TraceHub, INTA is default, RO register + {29, 0, PchIntA, 16}, // PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh + {29, 1, PchIntB, 17}, // PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh + {29, 2, PchIntC, 18}, // PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh + {29, 3, PchIntD, 19}, // PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh + {29, 4, PchIntA, 16}, // PCI Express Port 13 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {29, 5, PchIntB, 17}, // PCI Express Port 14 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {29, 6, PchIntC, 18}, // PCI Express Port 15 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {29, 7, PchIntD, 19}, // PCI Express Port 16 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {28, 0, PchIntA, 16}, // PCI Express Port 1, INT is default, programmed in PciCfgSpace + FCh + {28, 1, PchIntB, 17}, // PCI Express Port 2, INT is default, programmed in PciCfgSpace + FCh + {28, 2, PchIntC, 18}, // PCI Express Port 3, INT is default, programmed in PciCfgSpace + FCh + {28, 3, PchIntD, 19}, // PCI Express Port 4, INT is default, programmed in PciCfgSpace + FCh + {28, 4, PchIntA, 16}, // PCI Express Port 5, INT is default, programmed in PciCfgSpace + FCh + {28, 5, PchIntB, 17}, // PCI Express Port 6, INT is default, programmed in PciCfgSpace + FCh + {28, 6, PchIntC, 18}, // PCI Express Port 7, INT is default, programmed in PciCfgSpace + FCh + {28, 7, PchIntD, 19}, // PCI Express Port 8, INT is default, programmed in PciCfgSpace + FCh + {27, 0, PchIntA, 16}, // PCI Express Port 17 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {27, 1, PchIntB, 17}, // PCI Express Port 18 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {27, 2, PchIntC, 18}, // PCI Express Port 19 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh + {27, 3, PchIntD, 19}, // PCI Express Port 20 (SKL PCH-H Only), INT is default, programmed in PciCfgSpace + FCh +// {24, 0, 0, 0}, // Reserved (used by RST PCIe Storage Cycle Router) + {23, 0, PchIntA, 16}, // SATA Controller, INTA is default, programmed in PciCfgSpace + 3Dh + {22, 0, PchIntA, 16}, // CSME: HECI #1 + {22, 1, PchIntB, 17}, // CSME: HECI #2 + {22, 2, PchIntC, 18}, // CSME: IDE-Redirection (IDE-R) + {22, 3, PchIntD, 19}, // CSME: Keyboard and Text (KT) Redirection + {22, 4, PchIntA, 16}, // CSME: HECI #3 +// {22, 7, PchNoInt, 0}, // CSME: WLAN + {20, 0, PchIntA, 16}, // USB 3.0 xHCI Controller, no default value, programmed in PciCfgSpace 3Dh + {20, 2, PchIntC, 18}, // Thermal Subsystem +// {20, 4, 0, 0}, // TraceHub Phantom (ACPI) Function +// {18, 0, PchNoInt, 0}, // CSME: KVMcc, doesn't use interrupts +// {18, 1, PchNoInt, 0}, // CSME: Clink, doesn't use interrupts +// {18, 2, PchNoInt, 0}, // CSME: PMT, doesn't use interrupts +// {18, 3, 0, 0}, // CSME: CSE UMA +// {18, 4, 0, 0} // CSME: fTPM DMA + {17, 5, PchIntA, 16} // SSATA controller. +#ifdef IE_SUPPORT + , +// {16, 0, PchIntA, 16}, // IE: HECI #1 +// {16, 1, PchIntB, 17}, // IE: HECI #2 +// {16, 2, PchIntC, 18}, // IE: IDE-Redirection (IDE-R) + {16, 3, PchIntD, 19} // IE: Keyboard and Text (KT) Redirection +// {16, 4, PchIntA, 16} // IE: HECI #3 +#endif // IE_SUPPORT +}; + +// +// mLpOnlyDevIntConfig[] table contains data on INTx and IRQ for devices that exist on SPT-LP but not on SPT-H. +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mLpOnlyDevIntConfig[] = { + {25, 1, PchIntB, 33}, // SerialIo I2C Controller #5, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[6] + {25, 2, PchIntC, 34} // SerialIo I2C Controller #4, INTA is default, programmed in PCR[SERIALIO] + PCICFGCTRL[5] +}; +/** + mPxRcConfig[] table contains data for 8259 routing (how PIRQx is mapped to IRQy). + This information is used by systems which choose to use legacy PIC + interrupt controller. Only IRQ3-7,9-12,14,15 are valid. Values from this table + will be programmed into ITSS.PxRC registers. +**/ +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPxRcConfig[] = { + 11, // PARC: PIRQA -> IRQ11 + 10, // PBRC: PIRQB -> IRQ10 + 11, // PCRC: PIRQC -> IRQ11 + 11, // PDRC: PIRQD -> IRQ11 + 11, // PERC: PIRQE -> IRQ11 + 11, // PFRC: PIRQF -> IRQ11 + 11, // PGRC: PIRQG -> IRQ11 + 11 // PHRC: PIRQH -> IRQ11 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusRsvdAddresses[] = { + 0xA0, + 0xA2, + 0xA4, + 0xA6 +}; + +/** + PchCreatePolicyDefaults creates the default setting of PCH Policy. + It allocates and zero out buffer, and fills in the Intel default settings. + + @param[out] PchPolicyPpi The pointer to get PCH Policy PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +PchCreatePolicyDefaults ( + OUT PCH_POLICY_PPI **PchPolicyPpi + ) +{ + PCH_POLICY_PPI *PchPolicy; + PCH_SERIES PchSeries; + UINT32 PortIndex; + UINT32 Index; + UINT8 IntConfigTableEntries; + + PchSeries = GetPchSeries (); + + PchPolicy = (PCH_POLICY_PPI *) AllocateZeroPool (sizeof (PCH_POLICY_PPI)); + if (PchPolicy == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + // + // Policy not listed here are set to 0/FALSE as default. + // + + /******************************** + General initialization + ********************************/ + PchPolicy->Revision = PCH_POLICY_REVISION; + PchPolicy->AcpiBase = PcdGet16 (PcdPchAcpiIoPortBaseAddress); + PchPolicy->TempMemBaseAddr = PCH_TEMP_BASE_ADDRESS; + + /******************************** + PCH general configuration + ********************************/ + // + // Default Svid Sdid configuration + // + PchPolicy->PchConfig.SubSystemVendorId = V_PCH_INTEL_VENDOR_ID; + PchPolicy->PchConfig.SubSystemId = V_PCH_DEFAULT_SID; + + /******************************** + PCI Express related settings + ********************************/ + + PchPolicy->TempPciBusMin = 2; + PchPolicy->TempPciBusMax = 10; + + PchPolicy->PcieConfig.RpFunctionSwap = TRUE; + + for (PortIndex = 0; PortIndex < GetPchMaxPciePortNum (); PortIndex++) { + PchPolicy->PcieConfig.RootPort[PortIndex].Aspm = PchPcieAspmAutoConfig; + PchPolicy->PcieConfig.RootPort[PortIndex].Enable = TRUE; + PchPolicy->PcieConfig.RootPort[PortIndex].PmSci = TRUE; + PchPolicy->PcieConfig.RootPort[PortIndex].AcsEnabled = TRUE; + + PchPolicy->PcieConfig.RootPort[PortIndex].MaxPayload = PchPcieMaxPayload256; + + PchPolicy->PcieConfig.RootPort[PortIndex].PhysicalSlotNumber = (UINT8) PortIndex; + + PchPolicy->PcieConfig.RootPort[PortIndex].L1Substates = PchPcieL1SubstatesL1_1_2; + + // + // PCIe LTR Configuration. + // + PchPolicy->PcieConfig.RootPort[PortIndex].LtrEnable = TRUE; + if (PchSeries == PchLp) { + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxSnoopLatency = 0x1003; + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxNoSnoopLatency = 0x1003; + } + if (PchSeries == PchH) { + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxSnoopLatency = 0x0846; + PchPolicy->PcieConfig.RootPort[PortIndex].LtrMaxNoSnoopLatency = 0x0846; + } + PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideMode = 2; + PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideMultiplier = 2; + PchPolicy->PcieConfig.RootPort[PortIndex].SnoopLatencyOverrideValue = 60; + PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideMode = 2; + PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideMultiplier = 2; + PchPolicy->PcieConfig.RootPort[PortIndex].NonSnoopLatencyOverrideValue = 60; + + PchPolicy->PcieConfig.RootPort[PortIndex].Uptp = 5; + PchPolicy->PcieConfig.RootPort[PortIndex].Dptp = 7; + } + + for (Index = 0; Index < GetPchMaxPciePortNum (); ++Index) { + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cm = 6; + PchPolicy->PcieConfig.EqPh3LaneParam[Index].Cp = 6; + } + + PchPolicy->PcieConfig2.SwEqCoeffList[0].Cm = 6; + PchPolicy->PcieConfig2.SwEqCoeffList[0].Cp = 8; + PchPolicy->PcieConfig2.SwEqCoeffList[1].Cm = 8; + PchPolicy->PcieConfig2.SwEqCoeffList[1].Cp = 2; + PchPolicy->PcieConfig2.SwEqCoeffList[2].Cm = 10; + PchPolicy->PcieConfig2.SwEqCoeffList[2].Cp = 6; + PchPolicy->PcieConfig2.SwEqCoeffList[3].Cm = 12; + PchPolicy->PcieConfig2.SwEqCoeffList[3].Cp = 8; + PchPolicy->PcieConfig2.SwEqCoeffList[4].Cm = 14; + PchPolicy->PcieConfig2.SwEqCoeffList[4].Cp = 2; + + /******************************** + SATA related settings + ********************************/ + PchPolicy->SataConfig.Enable = TRUE; + PchPolicy->SataConfig.SalpSupport = TRUE; + PchPolicy->SataConfig.SataMode = PchSataModeAhci; + + for (PortIndex = 0; PortIndex < GetPchMaxSataPortNum (); PortIndex++) { + PchPolicy->SataConfig.PortSettings[PortIndex].Enable = TRUE; + PchPolicy->SataConfig.PortSettings[PortIndex].DmVal = 15; + PchPolicy->SataConfig.PortSettings[PortIndex].DitoVal = 625; + } + + PchPolicy->SataConfig.Rst.Raid0 = TRUE; + PchPolicy->SataConfig.Rst.Raid1 = TRUE; + PchPolicy->SataConfig.Rst.Raid10 = TRUE; + PchPolicy->SataConfig.Rst.Raid5 = TRUE; + PchPolicy->SataConfig.Rst.Irrt = TRUE; + PchPolicy->SataConfig.Rst.OromUiBanner = TRUE; + PchPolicy->SataConfig.Rst.OromUiDelay = PchSataOromDelay2sec; + PchPolicy->SataConfig.Rst.HddUnlock = TRUE; + PchPolicy->SataConfig.Rst.LedLocate = TRUE; + PchPolicy->SataConfig.Rst.IrrtOnly = TRUE; + PchPolicy->SataConfig.Rst.SmartStorage = TRUE; + + for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + PchPolicy->SataConfig.RstPcieStorageRemap[Index].DeviceResetDelay = 100; + } + /******************************** + sSATA related settings + ********************************/ + PchPolicy->sSataConfig.Enable = TRUE; + // PchPolicy->sSataConfig.TestMode = FALSE; + // PchPolicy->sSataConfig.LegacyMode = FALSE; + PchPolicy->sSataConfig.SalpSupport = TRUE; + // PchPolicy->sSataConfig.eSATASpeedLimit = FALSE; + PchPolicy->sSataConfig.SataMode = PchSataModeAhci; + // PchPolicy->sSataConfig.SpeedLimit = PchsSataSpeedDefault; + + for (PortIndex = 0; PortIndex < GetPchMaxsSataPortNum (); PortIndex++) { + PchPolicy->sSataConfig.PortSettings[PortIndex].Enable = TRUE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].HotPlug = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].InterlockSw = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].External = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].SpinUp = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].SolidStateDrive = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].DevSlp = FALSE; + // PchPolicy->sSataConfig.PortSettings[PortIndex].EnableDitoConfig = FALSE; + PchPolicy->sSataConfig.PortSettings[PortIndex].DmVal = 15; + PchPolicy->sSataConfig.PortSettings[PortIndex].DitoVal = 625; + } + + // PchPolicy->sSataConfig.Rst.RaidAlternateId = FALSE; + PchPolicy->sSataConfig.Rst.Raid0 = TRUE; + PchPolicy->sSataConfig.Rst.Raid1 = TRUE; + PchPolicy->sSataConfig.Rst.Raid10 = TRUE; + PchPolicy->sSataConfig.Rst.Raid5 = TRUE; + PchPolicy->sSataConfig.Rst.Irrt = TRUE; + PchPolicy->sSataConfig.Rst.OromUiBanner = TRUE; + PchPolicy->sSataConfig.Rst.OromUiDelay = PchSataOromDelay2sec; + PchPolicy->sSataConfig.Rst.HddUnlock = TRUE; + PchPolicy->sSataConfig.Rst.LedLocate = TRUE; + PchPolicy->sSataConfig.Rst.IrrtOnly = TRUE; + PchPolicy->sSataConfig.Rst.SmartStorage = TRUE; + + for (Index = 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + //PchPolicy->sSataConfig.RstPcieStorageRemap[Index].Enable = 0; + //PchPolicy->sSataConfig.RstPcieStorageRemap[Index].RstPcieStoragePort = 0; + PchPolicy->sSataConfig.RstPcieStorageRemap[Index].DeviceResetDelay = 100; + } + + /******************************** + USB related configuration + ********************************/ + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex++) { + PchPolicy->UsbConfig.PortUsb20[PortIndex].Enable = TRUE; + } + + for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) { + PchPolicy->UsbConfig.PortUsb30[PortIndex].Enable = TRUE; + } + // + //XHCI Wake On USB Disabled + // + PchPolicy->UsbConfig.XhciWakeOnUsb = FALSE; + // + // USB Port Over Current Pins mapping, please set as per board layout. + // Default is PchUsbOverCurrentPin0(0) + // + PchPolicy->UsbConfig.PortUsb20[ 2].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb20[ 3].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb20[ 4].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb20[ 5].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb20[ 6].OverCurrentPin = PchUsbOverCurrentPin3; + PchPolicy->UsbConfig.PortUsb20[ 7].OverCurrentPin = PchUsbOverCurrentPin3; + PchPolicy->UsbConfig.PortUsb20[ 8].OverCurrentPin = PchUsbOverCurrentPin4; + PchPolicy->UsbConfig.PortUsb20[ 9].OverCurrentPin = PchUsbOverCurrentPin4; + PchPolicy->UsbConfig.PortUsb20[10].OverCurrentPin = PchUsbOverCurrentPin5; + PchPolicy->UsbConfig.PortUsb20[11].OverCurrentPin = PchUsbOverCurrentPin5; + PchPolicy->UsbConfig.PortUsb20[12].OverCurrentPin = PchUsbOverCurrentPin6; + PchPolicy->UsbConfig.PortUsb20[13].OverCurrentPin = PchUsbOverCurrentPin6; + PchPolicy->UsbConfig.PortUsb20[14].OverCurrentPin = PchUsbOverCurrentPin7; + PchPolicy->UsbConfig.PortUsb20[15].OverCurrentPin = PchUsbOverCurrentPin7; + + PchPolicy->UsbConfig.PortUsb30[2].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb30[3].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb30[4].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb30[5].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb30[6].OverCurrentPin = PchUsbOverCurrentPin3; + PchPolicy->UsbConfig.PortUsb30[7].OverCurrentPin = PchUsbOverCurrentPin3; + PchPolicy->UsbConfig.PortUsb30[8].OverCurrentPin = PchUsbOverCurrentPin4; + PchPolicy->UsbConfig.PortUsb30[9].OverCurrentPin = PchUsbOverCurrentPin4; + + // + // Default values of USB2 AFE settings. + // + for (Index = 0; Index < PCH_H_XHCI_MAX_USB2_PORTS; Index++) { + + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Predeemp = 2; + + PchPolicy->UsbConfig.PortUsb20[Index].Afe.Pehalfbit = 1; + } + + // + // Enable/Disable SSIC support in the setup menu + // + for (PortIndex = 0; PortIndex < PCH_XHCI_MAX_SSIC_PORT_COUNT; PortIndex++) { + PchPolicy->UsbConfig.SsicConfig.SsicPort[PortIndex].Enable = FALSE; + } + + // + // xDCI configuration + // + PchPolicy->UsbConfig.XdciConfig.Enable = FALSE; + + + /******************************** + Io Apic configuration + ********************************/ + PchPolicy->IoApicConfig.IoApicId = 0x02; + PchPolicy->IoApicConfig.IoApicEntry24_119 = FALSE; + + /******************************** + HPET Configuration + ********************************/ + PchPolicy->HpetConfig.Enable = TRUE; + PchPolicy->HpetConfig.Base = PCH_HPET_BASE_ADDRESS; + + /******************************** + HD-Audio configuration + ********************************/ + PchPolicy->HdAudioConfig.Enable = PCH_HDAUDIO_AUTO; + PchPolicy->HdAudioConfig.DspEnable = TRUE; + PchPolicy->HdAudioConfig.HdAudioLinkFrequency = PchHdaLinkFreq24MHz; + PchPolicy->HdAudioConfig.IDispLinkFrequency = PchHdaLinkFreq96MHz; + PchPolicy->HdAudioConfig.ResetWaitTimer = 600; // Must be at least 521us (25 frames) + PchPolicy->HdAudioConfig.DspEndpointDmic = PchHdaDmic4chArray; + + /******************************** + Lan configuration + ********************************/ + PchPolicy->LanConfig.Enable = TRUE; + /******************************** + SMBus configuration + ********************************/ + PchPolicy->SmbusConfig.Enable = TRUE; + PchPolicy->SmbusConfig.SmbusIoBase = PcdGet16 (PcdSmbusBaseAddress); + ASSERT (sizeof (mSmbusRsvdAddresses) <= PCH_MAX_SMBUS_RESERVED_ADDRESS); + PchPolicy->SmbusConfig.NumRsvdSmbusAddresses = sizeof (mSmbusRsvdAddresses); + CopyMem ( + PchPolicy->SmbusConfig.RsvdSmbusAddressTable, + mSmbusRsvdAddresses, + sizeof (mSmbusRsvdAddresses) + ); + + /******************************** + Lockdown configuration + ********************************/ + PchPolicy->LockDownConfig.GlobalSmi = TRUE; + // + // PCH BIOS Spec Flash Security Recommendations, + // Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit + // will mitigate malicious software attempts to replace the system BIOS option ROM with its own code. + // Here we always enable this as a Policy. + // + PchPolicy->LockDownConfig.BiosInterface = TRUE; + PchPolicy->LockDownConfig.RtcLock = TRUE; + + /******************************** + Thermal configuration. + ********************************/ + PchPolicy->ThermalConfig.ThermalDeviceEnable = 0; + PchPolicy->ThermalConfig.TsmicLock = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.SuggestedSetting = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.DmiHaAWC.SuggestedSetting = TRUE; + PchPolicy->ThermalConfig.ThermalThrottling.SataTT.SuggestedSetting = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = TRUE; + PchPolicy->ThermalConfig.MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnable = TRUE; + + /******************************** + MiscPm Configuration + ********************************/ + PchPolicy->PmConfig.PowerResetStatusClear.MeWakeSts = TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstColdSts = TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.MeHrstWarmSts = TRUE; + PchPolicy->PmConfig.PowerResetStatusClear.WolOvrWkSts = TRUE; + + PchPolicy->PmConfig.WakeConfig.WolEnableOverride = TRUE; + PchPolicy->PmConfig.WakeConfig.LanWakeFromDeepSx = TRUE; + + PchPolicy->PmConfig.PchSlpS3MinAssert = PchSlpS350ms; + PchPolicy->PmConfig.PchSlpS4MinAssert = PchSlpS44s; + PchPolicy->PmConfig.PchSlpSusMinAssert = PchSlpSus4s; + PchPolicy->PmConfig.PchSlpAMinAssert = PchSlpA2s; + + PchPolicy->PmConfig.PmcReadDisable = TRUE; + PchPolicy->PmConfig.SlpLanLowDc = TRUE; + PchPolicy->PmConfig.PciePllSsc = 0xFF; + + PchPolicy->PmConfig.SlpS0Enable = TRUE; + + PchPolicy->PmConfig.GrPfetDurOnDef = PchPmGrPfetDur5us; + + /******************************** + DMI related settings + ********************************/ + PchPolicy->DmiConfig.DmiAspm = TRUE; + PchPolicy->DmiConfig.DmiStopAndScreamEnable = FALSE; + + /******************************** + Serial IRQ Configuration + ********************************/ + PchPolicy->SerialIrqConfig.SirqEnable = TRUE; + PchPolicy->SerialIrqConfig.SirqMode = PchQuietMode; + PchPolicy->SerialIrqConfig.StartFramePulse = PchSfpw4Clk; + + + /******************************** + Interrupt Configuration + ********************************/ + IntConfigTableEntries = sizeof (mDevIntConfig) / sizeof (PCH_DEVICE_INTERRUPT_CONFIG); + ASSERT (IntConfigTableEntries <= PCH_MAX_DEVICE_INTERRUPT_CONFIG); + PchPolicy->PchInterruptConfig.NumOfDevIntConfig = IntConfigTableEntries; + CopyMem ( + PchPolicy->PchInterruptConfig.DevIntConfig, + mDevIntConfig, + sizeof (mDevIntConfig) + ); + if (GetPchSeries () == PchLp) { + CopyMem ( + &(PchPolicy->PchInterruptConfig.DevIntConfig[IntConfigTableEntries]), + mLpOnlyDevIntConfig, + sizeof (mLpOnlyDevIntConfig) + ); + PchPolicy->PchInterruptConfig.NumOfDevIntConfig += (sizeof (mLpOnlyDevIntConfig) / sizeof (PCH_DEVICE_INTERRUPT_CONFIG)); + } + + ASSERT ((sizeof (mPxRcConfig) / sizeof (UINT8)) <= PCH_MAX_PXRC_CONFIG); + CopyMem ( + PchPolicy->PchInterruptConfig.PxRcConfig, + mPxRcConfig, + sizeof (mPxRcConfig) + ); + + PchPolicy->PchInterruptConfig.GpioIrqRoute = 14; + PchPolicy->PchInterruptConfig.SciIrqSelect = 9; + PchPolicy->PchInterruptConfig.TcoIrqSelect = 9; + + + /******************************** + Port 61h emulation + ********************************/ + PchPolicy->Port61hSmmConfig.Enable = TRUE; + + + /******************************** + DCI Configuration + ********************************/ + PchPolicy->DciConfig.DciAutoDetect = TRUE; + + /******************************** + LPC Configuration + ********************************/ + PchPolicy->LpcConfig.EnhancePort8xhDecoding = TRUE; + + /******************************** + Power Optimizer related settings + ********************************/ + PchPolicy->SataConfig.PwrOptEnable = TRUE; + PchPolicy->sSataConfig.PwrOptEnable = TRUE; + + + PchPolicy->AdrConfig.PchAdrEn = FORCE_ENABLE; + PchPolicy->AdrConfig.AdrGpioSel = PM_SYNC_GPIO_B; + PchPolicy->AdrConfig.AdrHostPartitionReset = FORCE_DISABLE; + PchPolicy->AdrConfig.AdrTimerEn = FORCE_ENABLE; + PchPolicy->AdrConfig.AdrTimerVal = V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_TMR_100US; + PchPolicy->AdrConfig.AdrMultiplierVal = V_PCH_LBG_MROM_ADRTIMERCTRL_ADR_MULT_1; + + *PchPolicyPpi = PchPolicy; + return EFI_SUCCESS; +} + +/** + PchInstallPolicyPpi installs PchPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please update and override + any setting before calling this function. + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +PchInstallPolicyPpi ( + IN PCH_POLICY_PPI *PchPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PchPolicyPpiDesc; + + PchPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); + if (PchPolicyPpiDesc == NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + PchPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PchPolicyPpiDesc->Guid = &gPchPlatformPolicyPpiGuid; + PchPolicyPpiDesc->Ppi = PchPolicyPpi; + + // + // Print whole PCH_POLICY_PPI and serial out. + // + if (PchIsDwrFlow() == FALSE) { + PchPrintPolicyPpi (PchPolicyPpi); + } + + // + // Install PCH Policy PPI + // + Status = PeiServicesInstallPpi (PchPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf new file mode 100644 index 0000000000..fa433c9333 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLib.inf @@ -0,0 +1,58 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPchPolicyLib
+ FILE_GUID = BB1AC992-B2CA-4744-84B7-915C185576C5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PchPolicyLib
+
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ PcdLib
+ PeiServicesLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PchInfoLib
+ PchPmcLib #SERVER_BIOS
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ LewisburgPkg/PchRcPkg.dec #SERVER_BIOS
+
+
+[Pcd]
+ gEfiPchTokenSpaceGuid.PcdPchAcpiIoPortBaseAddress #SERVER_BIOS
+ gEfiPchTokenSpaceGuid.PcdSmbusBaseAddress #SERVER_BIOS
+ gEfiPchTokenSpaceGuid.PcdSerialIoUartDebugEnable
+ gEfiPchTokenSpaceGuid.PcdSerialIoUartNumber
+
+
+[Sources]
+ PeiPchPolicyLib.c
+ PeiPchPolicyLibrary.h
+ PchPrintPolicy.c
+ Rvp3PolicyLib.c
+
+
+[Ppis]
+ gPchPlatformPolicyPpiGuid ## PRODUCES # SERVER_BIOS
+
+[Depex]
+ gPchInitPreMemDonePpiGuid
\ No newline at end of file diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLibrary.h b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLibrary.h new file mode 100644 index 0000000000..9932afdc04 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/PeiPchPolicyLibrary.h @@ -0,0 +1,31 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PEI_PCH_POLICY_LIBRARY_H_ +#define _PEI_PCH_POLICY_LIBRARY_H_ + +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/PeiServicesLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PchInfoLib.h> +#include <Ppi/PchPolicy.h> +#include <PchAccess.h> +#include <Library/PchSerialIoLib.h> +#include <Library/PchPolicyLib.h> + +#define PCH_HPET_BASE_ADDRESS 0xFED00000 + + +#endif // _PEI_PCH_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/Rvp3PolicyLib.c b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/Rvp3PolicyLib.c new file mode 100644 index 0000000000..62cc91f821 --- /dev/null +++ b/Silicon/Intel/LewisburgPkg/Library/PeiPchPolicyLib/Rvp3PolicyLib.c @@ -0,0 +1,211 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "PeiPchPolicyLibrary.h" + +/* + Apply RVP3 PCH specific default settings + + @param[in] PchPolicyPpi The pointer to PCH Policy PPI instance +*/ +VOID +EFIAPI +PchRvp3DefaultPolicy ( + IN PCH_POLICY_PPI *PchPolicy + ) +{ + UINTN Index; + + // + // PCIE RP + // + for (Index = 0; Index < GetPchMaxPciePortNum (); Index++) { + PchPolicy->PcieConfig.RootPort[Index].ClkReqDetect = TRUE; + PchPolicy->PcieConfig.RootPort[Index].AdvancedErrorReporting = TRUE; + } + + PchPolicy->PcieConfig.RootPort[0].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[0].ClkReqNumber = 2; + PchPolicy->HsioPcieConfig.Lane[0].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[0].HsioRxSetCtle = 6; + + PchPolicy->HsioPcieConfig.Lane[1].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[1].HsioRxSetCtle = 6; + + PchPolicy->HsioPcieConfig.Lane[2].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[2].HsioRxSetCtle = 6; + + PchPolicy->HsioPcieConfig.Lane[3].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[3].HsioRxSetCtle = 6; + + PchPolicy->PcieConfig.RootPort[4].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[4].ClkReqNumber = 3; + + PchPolicy->PcieConfig.RootPort[5].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[5].ClkReqNumber = 1; + PchPolicy->HsioPcieConfig.Lane[5].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[5].HsioRxSetCtle = 8; + + PchPolicy->HsioPcieConfig.Lane[7].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[7].HsioRxSetCtle = 8; + + PchPolicy->PcieConfig.RootPort[8].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[8].ClkReqNumber = 5; + PchPolicy->HsioPcieConfig.Lane[8].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[8].HsioRxSetCtle = 8; + + PchPolicy->PcieConfig.RootPort[9].ClkReqSupported = TRUE; + PchPolicy->PcieConfig.RootPort[9].ClkReqNumber = 4; + PchPolicy->HsioPcieConfig.Lane[9].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[9].HsioRxSetCtle = 8; + + PchPolicy->HsioPcieConfig.Lane[10].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[10].HsioRxSetCtle = 8; + + PchPolicy->HsioPcieConfig.Lane[11].HsioRxSetCtleEnable = TRUE; + PchPolicy->HsioPcieConfig.Lane[11].HsioRxSetCtle = 8; + + // + // SATA + // + PchPolicy->HsioSataConfig.PortLane[0].HsioRxGen3EqBoostMagEnable = TRUE; + PchPolicy->HsioSataConfig.PortLane[0].HsioRxGen3EqBoostMag = 4; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen1DownscaleAmpEnable = TRUE; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen1DownscaleAmp = 0x2C; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen2DownscaleAmpEnable = 0; + PchPolicy->HsioSataConfig.PortLane[0].HsioTxGen2DownscaleAmp = 0; + + // + // USB + // + PchPolicy->UsbConfig.PortUsb20[0].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[0].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[0].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[0].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[1].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[1].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[1].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[1].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[2].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[2].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[2].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[2].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[3].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[3].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[3].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[3].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[4].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[4].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[4].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[4].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[5].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[5].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[5].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[5].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[6].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[6].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[6].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[6].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[7].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[7].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[7].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[7].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[8].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[8].Afe.Txiset = 5; + PchPolicy->UsbConfig.PortUsb20[8].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[8].Afe.Pehalfbit = 1; + + PchPolicy->UsbConfig.PortUsb20[9].Afe.Petxiset = 7; + PchPolicy->UsbConfig.PortUsb20[9].Afe.Txiset = 0; + PchPolicy->UsbConfig.PortUsb20[9].Afe.Predeemp = 2; + PchPolicy->UsbConfig.PortUsb20[9].Afe.Pehalfbit = 1; + + // OC Map for USB2 Ports + PchPolicy->UsbConfig.PortUsb20[ 0].OverCurrentPin = PchUsbOverCurrentPin0; + PchPolicy->UsbConfig.PortUsb20[ 1].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb20[ 2].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 3].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 4].OverCurrentPin = PchUsbOverCurrentPin2; + PchPolicy->UsbConfig.PortUsb20[ 5].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 6].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 7].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[ 8].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb20[ 9].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[10].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[11].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[12].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb20[13].OverCurrentPin = PchUsbOverCurrentPinSkip; + + // OC Map for USB3 Ports + PchPolicy->UsbConfig.PortUsb30[0].OverCurrentPin = PchUsbOverCurrentPin0; + PchPolicy->UsbConfig.PortUsb30[1].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb30[2].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb30[3].OverCurrentPin = PchUsbOverCurrentPin1; + PchPolicy->UsbConfig.PortUsb30[4].OverCurrentPin = PchUsbOverCurrentPinSkip; + PchPolicy->UsbConfig.PortUsb30[5].OverCurrentPin = PchUsbOverCurrentPinSkip; + + PchPolicy->UsbConfig.SsicConfig.SsicPort[0].Enable = TRUE; + PchPolicy->UsbConfig.SsicConfig.SsicPort[1].Enable = TRUE; + + // + // IOAPIC + // + PchPolicy->IoApicConfig.BdfValid = 1; + PchPolicy->IoApicConfig.BusNumber = 0xF0; + PchPolicy->IoApicConfig.DeviceNumber = 0x1F; + PchPolicy->IoApicConfig.FunctionNumber = 0; + + // + // LAN + // + PchPolicy->LanConfig.K1OffEnable = TRUE; + PchPolicy->LanConfig.ClkReqSupported = TRUE; + PchPolicy->LanConfig.ClkReqNumber = 3; + + // + // LOCK DOWN + // + PchPolicy->LockDownConfig.SpiEiss = TRUE; + PchPolicy->LockDownConfig.BiosLock = TRUE; + + // + // THERMAL + // + PchPolicy->ThermalConfig.ThermalThrottling.TTLevels.PchCrossThrottling = FALSE; + + // + // PM CONFIG + // + PchPolicy->PmConfig.PciClockRun = TRUE; + + // + // DMI + // + PchPolicy->DmiConfig.PwrOptEnable = TRUE; + + + // + // TRACEHUB + // + PchPolicy->PchTraceHubConfig.MemReg0Size = 0x100000; // 1MB + PchPolicy->PchTraceHubConfig.MemReg1Size = 0x100000; // 1MB + +} |