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Diffstat (limited to 'Silicon/Intel/PurleyRcPkg/Include')
9 files changed, 939 insertions, 0 deletions
diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/CsrToPcieAddress.h b/Silicon/Intel/PurleyRcPkg/Include/Library/CsrToPcieAddress.h new file mode 100644 index 0000000000..a4aaa24ba8 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/CsrToPcieAddress.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __CSR_TO_PCIE_ADDRESS_H__ +#define __CSR_TO_PCIE_ADDRESS_H__ + + +#include <UsraAccessType.h> + +////////////////////////////////////////////////////////////////////////// +// +// CSR to Pcie Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ); + + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/MmPciBaseLib.h b/Silicon/Intel/PurleyRcPkg/Include/Library/MmPciBaseLib.h new file mode 100644 index 0000000000..22b4179db3 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/MmPciBaseLib.h @@ -0,0 +1,54 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MM_PCIE_BASE_LIB_H_ +#define _MM_PCIE_BASE_LIB_H_ + +#include <Library/UsraAccessApi.h> + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +); + +/** + This procedure will get PCIE address + + @param[in] Seg Pcie Segment Number + @param[in] Bus Pcie Bus Number + @param[in] Device Pcie Device Number + @param[in] Function Pcie Function Number + + @retval PCIE address +**/ +UINTN +MmPciAddress( +IN UINT32 Seg, +IN UINT32 Bus, +IN UINT32 Device, +IN UINT32 Function, +IN UINT32 Register +); + +#endif // _MM_PCIE_BASE_LIB_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/PcieAddress.h b/Silicon/Intel/PurleyRcPkg/Include/Library/PcieAddress.h new file mode 100644 index 0000000000..3f0cbf8e6f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/PcieAddress.h @@ -0,0 +1,86 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PCIE_MMCFG_H__ +#define __PCIE_MMCFG_H__ + +#include <UsraAccessType.h> + + +////////////////////////////////////////////////////////////////////////// +// +// PCIE MMCFG Table definition +// This table was based on PCI Firmware Spec Rev 3.1 +// +////////////////////////////////////////////////////////////////////////// + +typedef struct + { + UINT8 Signature[4]; // "MCFG" Signature For this Table + UINT32 Length; // Length, in bytes, include base address allocation structures. + UINT8 Revision; // "1" + UINT8 SegMax; // The Maximum number of Segments + UINT16 ValidSegMap; // Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ... + UINT8 Reserved[4]; // Reserved +} PCIE_MMCFG_HEADER_TYPE; + +typedef struct + { + UINT32 BaseAddressL; // Processor-relative Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechanism + UINT32 BaseAddressH; // Processor-relative Base Address (Upper 32-bit) for the Enhanced Configuration Access Mechanism + UINT16 Segment; // PCI Segment Group Number. Default is 0. + UINT8 StartBus; // Start PCI Bus number decoded by the host bridge + UINT8 EndBus; // End PCI Bus number decoded by the host bridge + UINT8 Reserved[4]; // Reserved +} PCIE_MMCFG_BASE_ADDRESS_TYPE; + + +typedef struct + { + PCIE_MMCFG_HEADER_TYPE Header; // The header of MMCFG Table + PCIE_MMCFG_BASE_ADDRESS_TYPE MmcfgBase[1]; // First Array of base address allocation structures. +} PCIE_MMCFG_TABLE_TYPE; + + +/** + This Lib is used for platform to set platform specific Pcie MMCFG Table + + @param[in] MmcfgTable A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type + @param[in] NumOfSeg Number of Segments in the table + + @retval <>NULL The function completed successfully. + @retval NULL Return Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg +); + +/** + This Lib return PCIE MMCFG Base Address + + @param[in] Address A pointer of the address of the USRA Address Structure for PCIE type + + @retval <>NULL The function completed successfully. + @retval NULL Return Error +**/ +UINTN +EFIAPI +GetPcieSegMmcfgBaseAddress ( + IN USRA_ADDRESS *Address + ); + + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/PciePlatformHookLib.h b/Silicon/Intel/PurleyRcPkg/Include/Library/PciePlatformHookLib.h new file mode 100644 index 0000000000..6712b78ea6 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/PciePlatformHookLib.h @@ -0,0 +1,33 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PCIE_PLATFORM_HOOK_LIB_H__ +#define __PCIE_PLATFORM_HOOK_LIB_H__ + +typedef enum { + PcieInitStart, + BeforeBifurcation, + AfterBifurcation, + BeforePortInit, + AfterPortInit, + PcieInitEnd +} PCIE_HOOK_EVENT; + +EFI_STATUS +EFIAPI +PciePlatformHookEvent ( + IN PCIE_HOOK_EVENT Event, + IN VOID *Context + ); + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/Library/UsraAccessApi.h b/Silicon/Intel/PurleyRcPkg/Include/Library/UsraAccessApi.h new file mode 100644 index 0000000000..cbe365cea3 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Library/UsraAccessApi.h @@ -0,0 +1,91 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __USRA_ACCESS_API_H__ +#define __USRA_ACCESS_API_H__ + + +#include <UsraAccessType.h> + +////////////////////////////////////////////////////////////////////////// +// +// USRA Silicon Access Library +// +////////////////////////////////////////////////////////////////////////// + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterRead ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterWrite ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval RETURN_SUCCESS The function completed successfully. +**/ +RETURN_STATUS +EFIAPI +RegisterModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +GetRegisterAddress ( + IN USRA_ADDRESS *Address + ); + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/MaxSocket.h b/Silicon/Intel/PurleyRcPkg/Include/MaxSocket.h new file mode 100644 index 0000000000..f380967cc4 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/MaxSocket.h @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// +// This defines the maximum number of sockets supported by some modules. +// It is generally better to use a dynamic solution. +// This is also defined by build tools for some special build +// environments used in validation that do not support EDK II build +// and thus can't use PCD. +// + +#ifndef MAX_SOCKET +#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount)) +#endif + diff --git a/Silicon/Intel/PurleyRcPkg/Include/Ppi/SiliconRegAccess.h b/Silicon/Intel/PurleyRcPkg/Include/Ppi/SiliconRegAccess.h new file mode 100644 index 0000000000..c0f4624a8f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Ppi/SiliconRegAccess.h @@ -0,0 +1,168 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SILICON_REG_ACCESS_PPI_H__ +#define __SILICON_REG_ACCESS_PPI_H__ + +#include <UsraAccessType.h> + +extern EFI_GUID gUsraPpiGuid; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_READ)( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_WRITE)( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PPI_REG_MODIFY)( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +typedef +INTN +(EFIAPI *USRA_PPI_GET_ADDR)( + IN USRA_ADDRESS *Address + ); + +/// +/// This service abstracts the ability to read/write silicon register. +/// +typedef struct { + USRA_PPI_REG_READ RegRead; + USRA_PPI_REG_WRITE RegWrite; + + USRA_PPI_REG_MODIFY RegModify; + USRA_PPI_GET_ADDR GetRegAddr; +} USRA_PPI; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegWrite ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit Pcie silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +PeiRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +PeiGetRegAddr ( + IN USRA_ADDRESS *Address + ); + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/Protocol/SiliconRegAccess.h b/Silicon/Intel/PurleyRcPkg/Include/Protocol/SiliconRegAccess.h new file mode 100644 index 0000000000..72e556b270 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/Protocol/SiliconRegAccess.h @@ -0,0 +1,233 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SILICON_REG_ACCESS_PROTOCOL_H__ +#define __SILICON_REG_ACCESS_PROTOCOL_H__ + +#include <UsraAccessType.h> + +extern EFI_GUID gUsraProtocolGuid; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_READ)( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_WRITE)( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_REG_MODIFY)( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +typedef +INTN +(EFIAPI *USRA_PROTOCOL_GET_ADDR)( + IN USRA_ADDRESS *Address + ); + +/// +/// This service abstracts the ability to read/write silicon register. +/// +typedef struct { + USRA_PROTOCOL_REG_READ RegRead; + USRA_PROTOCOL_REG_WRITE RegWrite; + USRA_PROTOCOL_REG_MODIFY RegModify; + USRA_PROTOCOL_GET_ADDR GetRegAddr; +} USRA_PROTOCOL; + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +DxeRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +DxeGetRegAddr ( + IN USRA_ADDRESS *Address + ); + + /** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register read operations. + It transfers data from a register into a naturally aligned data buffer. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + @param[in] Buffer A pointer of buffer for the value read from the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegRead ( + IN USRA_ADDRESS *Address, + IN VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register write operations. + It transfers data from a naturally aligned data buffer into a silicon register. + + @param[in] Address A pointer of the address of the USRA Address Structure to be written + @param[in] Buffer A pointer of buffer for the value write to the register + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegWrite ( + IN USRA_ADDRESS *Address, + OUT VOID *Buffer + ); + +/** + This API Perform 8-bit, 16-bit, 32-bit or 64-bit silicon register AND then OR operations. It read data from a + register, And it with the AndBuffer, then Or it with the OrBuffer, and write the result back to the register + + @param[in] Address A pointer of the address of the silicon register to be written + @param[in] AndBuffer A pointer of buffer for the value used for AND operation + A NULL pointer means no AND operation. RegisterModify() equivalents to RegisterOr() + @param[in] OrBuffer A pointer of buffer for the value used for OR operation + A NULL pointer means no OR operation. RegisterModify() equivalents to RegisterAnd() + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +INTN +EFIAPI +SmmRegModify ( + IN USRA_ADDRESS *Address, + IN VOID *AndBuffer, + IN VOID *OrBuffer + ); + +/** + This API get the flat address from the given USRA Address. + + @param[in] Address A pointer of the address of the USRA Address Structure to be read out + + @retval The flat address +**/ +INTN +EFIAPI +SmmGetRegAddr ( + IN USRA_ADDRESS *Address + ); + + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Include/UsraAccessType.h b/Silicon/Intel/PurleyRcPkg/Include/UsraAccessType.h new file mode 100644 index 0000000000..d3a97a6446 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Include/UsraAccessType.h @@ -0,0 +1,201 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __USRA_ACCESS_TYPE_H__ +#define __USRA_ACCESS_TYPE_H__ + +typedef enum { + AddrTypePCIE = 0, + AddrTypePCIEBLK, + AddrTypeCSR, + AddrTypeMMIO, + AddrTypeIO, + AddrTypeMaximum +} USRA_ADDR_TYPE; + +typedef enum { + UsraWidth8 = 0, + UsraWidth16, + UsraWidth32, + UsraWidth64, + UsraWidthFifo8, + UsraWidthFifo16, + UsraWidthFifo32, + UsraWidthFifo64, + UsraWidthFill8, + UsraWidthFill16, + UsraWidthFill32, + UsraWidthFill64, + UsraWidthMaximum +} USRA_ACCESS_WIDTH; + +typedef enum { + CsrBoxInst = 0, + CsrChId, + CsrMcId, + CsrSubTypeMax +} CSR_INST_TYPE; + +#define USRA_ENABLE 1; +#define USRA_DISABLE 0; + +#pragma pack (1) + +typedef struct + { + UINT32 RawData32[2]; // RawData of two UINT32 type, place holder + UINT32 AddrType:8; // Address type: CSR, PCIE, MMIO, IO, SMBus ... + UINT32 AccessWidth:4; // The Access width for 8, 16,32,64 -bit access + UINT32 FastBootEn:1; // Fast Boot Flag, can be used to log register access trace for fast boot + UINT32 S3Enable:1; // S3 Enable bit, when enabled, it will save the write to script to support S3 + UINT32 HptrType:1; // Host Pointer type, below or above 4GB + UINT32 ConvertedType:1; // The address type was from converted type, use this field for address migration support + UINT32 RFU3:16; // Reserved for User use or Future Use + + UINT32 HostPtr:32; // The Host Pointer, to point to Attribute buffer etc. +} ADDR_ATTRIBUTE_TYPE; + +typedef struct + { + UINT32 Offset:12; // The PCIE Register Offset + UINT32 Func:3; // The PCIE Function + UINT32 Dev:5; // The PCIE Device + UINT32 Bus:8; // The PCIE Bus + UINT32 RFU1:4; // Reserved for User use or Future Use + + UINT32 Seg:16; // The PCI Segment + UINT32 Count:16; // Access Count + +} USRA_PCIE_ADDR_TYPE; + +typedef struct + { + UINT32 Offset; // This Offset occupies 32 bits. It's platform code's responsibilty to define the meaning of specific + // bits and use them accordingly. + UINT32 InstId:8; // The Box Instance, 0 based, Index/Port within the box, Set Index as 0 if the box has only one instances + UINT32 SocketId:8; // The socket Id + UINT32 InstType:8; // The Instance Type, it can be Box, Memory Channel etc. + UINT32 RFU:8; // Reserved for User use or Future Ues + +} USRA_CSR_ADDR_TYPE; + +typedef struct + { + UINT32 Offset:32; // The MMIO Offset + + UINT32 OffsetH: 32; // The MMIO Offset Higher 32-bit +} USRA_MMIO_ADDR_TYPE; + +typedef struct + { + UINT32 Offset:16; // The IO Offset + UINT32 RFU1:16; // Reserved for User use or Future Use + + UINT32 RFU2:32; // Reserved for User use or Future Use + +} USRA_IO_ADDR_TYPE; + +#pragma pack() + +typedef union { + UINT32 dwRawData[4]; + ADDR_ATTRIBUTE_TYPE Attribute; // The address attribute type. + USRA_PCIE_ADDR_TYPE Pcie; + USRA_PCIE_ADDR_TYPE PcieBlk; + USRA_CSR_ADDR_TYPE Csr; + USRA_MMIO_ADDR_TYPE Mmio; + USRA_IO_ADDR_TYPE Io; +} USRA_ADDRESS; + +// +// Assemble macro for USRA_PCIE_ADDR_TYPE +// +#define USRA_PCIE_SEG_ADDRESS(Address, WIDTH, SEG, BUS, DEV, FUNC, OFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(OFFSET) & 0x0FFF + +// +// Assemble macro for USRA_BDFO_ADDR_TYPE +// +#define USRA_PCIE_SEG_BDFO_ADDRESS(Address, WIDTH, SEG, BDFO) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIE; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Seg = (UINT32)(SEG); \ + ((USRA_ADDRESS *)(&Address))->Pcie.Bus = (UINT32)(BDFO >> 20) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Dev = (UINT32)(BDFO >> 15) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Func = (UINT32)(BDFO >> 12) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->Pcie.Offset = (UINT32)(BDFO) & 0x0FFF + +// +// Assemble macro for USRA_PCIE_BLK_ADDR_TYPE +// +#define USRA_BLOCK_PCIE_ADDRESS(Address, WIDTH, COUNT, SEG, BUS, DEV, FUNC, OFFSET) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AccessWidth = WIDTH; \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypePCIEBLK; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Count = (UINT32)COUNT; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Seg = (UINT32)SEG; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Bus = (UINT32)(BUS) & 0xFF; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Dev = (UINT32)(DEV) & 0x1F; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Func = (UINT32)(FUNC) & 0x07; \ + ((USRA_ADDRESS *)(&Address))->PcieBlk.Offset = (UINT32)(OFFSET) & 0x0FFF +// +// Assemble macro for USRA_PCIE_SEG_ADDR_TYPE +// +#define USRA_PCIE_ADDRESS(Address, WIDTH, BUS, DEV, FUNC, OFFSET) \ + USRA_PCIE_SEG_ADDRESS(Address, WIDTH, 0, BUS, DEV, FUNC, OFFSET) + +// +// Assemble macro for USRA_CSR_ADDR_TYPE +// +#define USRA_CSR_OFFSET_ADDRESS(Address, SOCKETID, INSTID, CSROFFSET, INSTTYPE) \ + USRA_ZERO_ADDRESS(Address); \ + ((USRA_ADDRESS *)(&Address))->Attribute.AddrType = AddrTypeCSR; \ + ((USRA_ADDRESS *)(&Address))->Csr.InstType = INSTTYPE; \ + ((USRA_ADDRESS *)(&Address))->Csr.SocketId = SOCKETID; \ + ((USRA_ADDRESS *)(&Address))->Csr.InstId = INSTID; \ + ((USRA_ADDRESS *)(&Address))->Csr.Offset = CSROFFSET + +// +// Assemble macro for ZERO_USRA ADDRESS +// +#define USRA_ZERO_ADDRESS(Address) \ + ((UINT32 *)&Address)[3] = (UINT32)0; \ + ((UINT32 *)&Address)[2] = (UINT32)0; \ + ((UINT32 *)&Address)[1] = (UINT32)0; \ + ((UINT32 *)&Address)[0] = (UINT32)0 + +// +// Assemble macro for ZERO_ADDR_TYPE +// +#define USRA_ZERO_ADDRESS_TYPE(Address, AddressType) \ + ((UINT32 *)&Address)[3] = (UINT32)0; \ + ((UINT32 *)&Address)[2] = (UINT32)((AddressType) & 0x0FF); \ + ((UINT32 *)&Address)[1] = (UINT32)0; \ + ((UINT32 *)&Address)[0] = (UINT32)0 + +#define USRA_ADDRESS_COPY(DestAddrPtr, SourceAddrPtr) \ + ((UINT32 *)DestAddrPtr)[3] = ((UINT32 *)SourceAddrPtr)[3]; \ + ((UINT32 *)DestAddrPtr)[2] = ((UINT32 *)SourceAddrPtr)[2]; \ + ((UINT32 *)DestAddrPtr)[1] = ((UINT32 *)SourceAddrPtr)[1]; \ + ((UINT32 *)DestAddrPtr)[0] = ((UINT32 *)SourceAddrPtr)[0]; + +#endif + |