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Diffstat (limited to 'Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include')
9 files changed, 1579 insertions, 0 deletions
diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h new file mode 100644 index 0000000000..79ab649751 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioConfig.h @@ -0,0 +1,306 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IIO_CONFIG_H +#define _IIO_CONFIG_H + +#pragma pack(1) //to align members on byte boundary +typedef struct { + +/** +================================================================================================== +================================== VTd Setup Options ================================== +================================================================================================== +**/ + + UINT8 VTdSupport; + UINT8 InterruptRemap; + UINT8 CoherencySupport; + UINT8 ATS; + UINT8 PostedInterrupt; + UINT8 PassThroughDma; + +/** +================================================================================================== +================================== PCIE Setup Options ================================== +================================================================================================== +**/ + UINT8 IioPresent[MAX_SOCKET]; + UINT8 VtdAcsWa; + + // Platform data needs to update these PCI Configuration settings + UINT8 SLOTIMP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Implemented - PCIE Capabilities (D0-10 / F0 / R0x92 / B8) + UINT16 SLOTPSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Physical slot Number - Slot Capabilities (D0-10 / F0 / R0xA4 / B31:19). Change to use 13 bits instead of 8 + UINT8 SLOTEIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17) + UINT8 SLOTSPLS[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Power Limit Scale - Slot Capabilities (D0-10 / F0 / R0xA4 / B16:15) + UINT8 SLOTSPLV[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Power Limit Value - Slot Capabilities (D0-10 / F0 / R0xA4 / B14:7) + UINT8 SLOTHPCAP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) + UINT8 SLOTHPSUP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + UINT8 SLOTPIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4) + UINT8 SLOTAIP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3) + UINT8 SLOTMRLSP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2) + UINT8 SLOTPCP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1) + UINT8 SLOTABP[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0) + UINT8 PcieSSDCapable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Indicate if Port will PcieSSD capable. + + // General PCIE Configuration + UINT8 ConfigIOU0[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P5p6p7p8) + UINT8 ConfigIOU1[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P9p10p11p12) + UINT8 ConfigIOU2[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) + UINT8 ConfigMCP0[MAX_SOCKET]; // 04-x16 (p13) + UINT8 ConfigMCP1[MAX_SOCKET]; // 04-x16 (p14) + UINT8 CompletionTimeoutGlobal; // + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; // + UINT8 StopAndScream; // + UINT8 SnoopResponseHoldOff; // + // + // PCIE capability + // + UINT8 PCIe_LTR; // + UINT8 PcieExtendedTagField; // + UINT8 PCIe_AtomicOpReq; // + UINT8 PcieMaxReadRequestSize; // + + + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + + + // mixc PCIE configuration + UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieAspm[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup + UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup + UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup + UINT8 ExtendedSync[MAX_TOTAL_PORTS]; // On Setup + UINT8 InbandPresenceDetect[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePortDisable[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePmeIntEn[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup + // + // VPP Control + // + UINT8 VppEnable[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj + UINT8 VppPort[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj + UINT8 VppAddress[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; //on Setup + UINT8 ComplianceMode[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup + UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for MISCCTRLSTS + // + UINT8 EOI[MAX_TOTAL_PORTS]; // On Setup + UINT8 MSIFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSINFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSICOREN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; //On Setup + UINT8 DISL0STx[MAX_TOTAL_PORTS]; //On Setup + UINT8 P2PWrtDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 Peer + UINT8 P2PRdDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 peer + UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIHP[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIPM[MAX_TOTAL_PORTS]; //On Setup + UINT8 SRIS[MAX_TOTAL_PORTS]; //On Setup + UINT8 TXEQ[MAX_TOTAL_PORTS]; //On Setup + UINT8 ECRC[MAX_TOTAL_PORTS]; //On Setup + // + // PCIE RAS (Errors) + // + + UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; // Unsupported Request per-port option + UINT8 Serr; + UINT8 Perr; + UINT8 IioErrorEn; + UINT8 LerEn; + UINT8 WheaPcieErrInjEn; + + // + // PciePll + // + UINT8 PciePllSsc; //On Setup + + // + // PCIE Link Training Ctrl + // + +/** +================================================================================================== +================================== Crystal Beach 3 Setup Options =========================== +================================================================================================== +**/ + UINT8 Cb3DcaEn[MAX_SOCKET]; // on setup + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; +/** +================================================================================================== +================================== MISC IOH Setup Options ========================== +================================================================================================== +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[MAX_SOCKET*NUMBER_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + UINT8 MctpEn; + + UINT8 LegacyVgaSoc; + UINT8 LegacyVgaStack; + + UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /display the PCIe port menu + +/** +================================================================================================== +================================== NTB Related Setup Options ========================== +================================================================================================== +**/ + UINT8 NtbPpd[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeOverride[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSplitBar[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSBar01Prefetch[MAX_NTB_PORTS]; //on setup option + UINT8 NtbXlinkCtlOverride[MAX_NTB_PORTS]; //on setup option + +/** +================================================================================================== +================================== VMD Related Setup Options ========================== +================================================================================================== +**/ + UINT8 VMDEnabled[MAX_VMD_STACKS]; + UINT8 VMDPortEnable[MAX_VMD_PORTS]; + UINT8 VMDHotPlugEnable[MAX_VMD_STACKS]; + UINT8 VMDCfgBarSz[MAX_VMD_STACKS]; + UINT8 VMDCfgBarAttr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz1[MAX_VMD_STACKS]; + UINT8 VMDMemBar1Attr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz2[MAX_VMD_STACKS]; + UINT8 VMDMemBar2Attr[MAX_VMD_STACKS]; + + /** + ================================================================================================== + ================================== PcieSSD Related Setup Options ========================== + ================================================================================================== + **/ + UINT8 PcieAICEnabled[MAX_VMD_STACKS]; // Indicate if PCIE AIC Device will be connected behind an specific IOUx + UINT8 PcieAICPortEnable[MAX_VMD_PORTS]; + UINT8 PcieAICHotPlugEnable[MAX_VMD_STACKS]; + +/** +================================================================================================== +================================== Gen3 Related Setup Options ========================== +================================================================================================== +**/ + + //PCIE Global Option + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieHotPlugEnable; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 RxClockWA; + UINT8 GlobalPme2AckTOCtrl; //on Setup + + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup +/** +================================================================================================== +================================== IOAPIC Related Setup Options ========================== +================================================================================================== +**/ + + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; +/** +================================================================================================== +================================== Security Related Setup Options ========================== +================================================================================================== +**/ + UINT8 LockChipset; + UINT8 PeciInTrustControlBit; + UINT8 ProcessorX2apic; + UINT8 ProcessorMsrLockControl; + +/** +================================================================================================== +================================== Iio Related Setup Options ========================== +================================================================================================== +**/ + UINT8 RtoEnable; // On Setup + UINT8 RtoLtssmLogger; // On Setup + UINT8 RtoLtssmLoggerStop; // On Setup + UINT8 RtoLtssmLoggerSpeed; // On Setup + UINT8 RtoLtssmLoggerMask; // On Setup + UINT8 RtoJitterLogger; // On Setup + UINT32 RtoSocketDevFuncHide[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup + UINT8 RtoGen3NTBTestCard[MAX_TOTAL_PORTS]; // On Setup + + UINT8 RtoGen3OverrideMode[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3TestCard[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoDnTxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoRxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoUpTxPreset[MAX_TOTAL_PORTS]; //On Setup + + UINT8 InboundConfiguration[MAX_TOTAL_PORTS]; //On Setup + +} IIO_CONFIG; +#pragma pack() + +#endif // _IIO_CONFIG_H diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h new file mode 100644 index 0000000000..7c980cb458 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioPlatformData.h @@ -0,0 +1,292 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IIO_PLATFORM_DATA_H_ +#define _IIO_PLATFORM_DATA_H_ + +#include <SysRegs.h> +#include <KtiSi.h> +#include <IioRegs.h> +#include <IioConfig.h> +#ifndef MINIBIOS_BUILD +#ifndef IA32 +#include <Uefi.h> +#include <PiDxe.h> +#include <Protocol/CpuCsrAccess.h> +#define IIO_CPU_CSR_ACCESS EFI_CPU_CSR_ACCESS_PROTOCOL +#endif +#endif + +#define IIO_HANDLE VOID * +#define IIO_STATUS UINT32 + +typedef struct { + UINT8 Register; + UINT8 Function; + UINT8 Device; + UINT8 Bus; + UINT32 ExtendedRegister; +} PCI_ROOT_BRIDGE_PCI_ADDRESS; + +typedef enum { + DmiTypeVc0, + DmiTypeVc1, + DmiTypeVcm, + MaxDmiVcType +} DMI_VC_TYPE; + +#define MaxDmiTcType 3 + +typedef enum { + IIOInitPhase1 = 1, + IIOInitPhase2 = 2, + IIOInitPhase3 = 4, +} IIO_INIT_PHASE; + +typedef enum { + IioBeforeBifurcation, // Point before IOU Bi-fucuation and link training, no generic inbound access at this point + IioAfterBifurcation, // Point immediately after IOU bifurcation and link training but before any PCIe root port initialization + IioPortEnumeration, // Point before Port initialization, no generic inbound access at this point + IioPortEnumProgramMISCCTRL, // Inside IioPortInit.PcieSlotInit + IioEnumEnd, + IioVtDPreEn, + IioVtDInit, + IioVtDEn, // At this point it has been decided to enable VtD through setup IioVtdInit.VtdInitialization + IioPostInitEnd, // this is the last stage of IIO PCIe port init + IioBeforeResources, // At this point IIO Ports configuration has been completed + IioAfterResources // At this point PCIe Resources allocation has been completed +} IIO_INIT_ENUMERATION; + + +extern const CHAR* IioPortLabel[]; + +#define IIO_PORT_LABEL(x) ( ((x) < NUMBER_PORTS_PER_SOCKET) ? (IioPortLabel[(x)]) : IioPortLabel[NUMBER_PORTS_PER_SOCKET] ) + +#pragma pack(1) + +typedef union{ + struct{ + UINT32 Value; + UINT32 ValueHigh; + }Address32bit; + UINT64 Address64bit; +}IIO_PTR_ADDRESS; + +typedef struct { + UINT32 Device; + UINT32 Function; + UINT32 RegOffset; + UINT32 AndMask; + UINT32 OrMask; +} PCI_OP_STRUCT; + +typedef struct { + UINT32 Instance; + UINT32 RegOffset; + UINT32 AndMask; + UINT32 OrMask; +} CSR_ACCESS_OP_STRUCT; + +typedef struct { + UINT8 Isoc; + UINT32 meRequestedSize; + UINT8 Vc1_pri_en; + UINT8 Isoc_Enable; +} ISOC_VC_TABLE_STRUCT; + +/* + * Following are the data structure defined to support multiple CBDMA types on a system + */ + +typedef struct{ + UINT32 DcaSupported : 1; + UINT32 NoSnoopSupported : 1; + UINT32 RelaxOrderSupported : 1; +}CB_CONFIG_CAPABILITY; + +typedef struct{ + UINT8 CB_VER; + UINT8 BusNo; + UINT8 DevNo; + UINT8 FunNo; + UINT8 MaxNoChannels; + CB_CONFIG_CAPABILITY CBConfigCap; +}CBDMA_CONTROLLER; + +typedef struct{ + CBDMA_CONTROLLER CbDmaDevice; +}DMA_HOST; + +// <<<< end of CBDMA data structures >>>> + +typedef union { +struct { + UINT32 Dev0 : 1; + UINT32 Dev1 : 1; + UINT32 Dev2 : 1; + UINT32 Dev3 : 1; + UINT32 Dev4 : 1; + UINT32 Dev5 : 1; + UINT32 Dev6 : 1; + UINT32 Dev7 : 1; + UINT32 Dev8 : 1; + UINT32 Dev9 : 1; + UINT32 Dev10 : 1; + UINT32 Dev11 : 1; + UINT32 Dev12 : 1; + UINT32 Dev13 : 1; + UINT32 Dev14 : 1; + UINT32 Dev15 : 1; + UINT32 Dev16 : 1; + UINT32 Dev17 : 1; + UINT32 Dev18 : 1; + UINT32 Dev19 : 1; + UINT32 Dev20 : 1; + UINT32 Dev21 : 1; + UINT32 Dev22 : 1; + UINT32 Dev23 : 1; + UINT32 Dev24 : 1; + UINT32 Dev25 : 1; + UINT32 Dev26 : 1; + UINT32 Dev27 : 1; + UINT32 Dev28 : 1; + UINT32 Dev29 : 1; + UINT32 Dev30 : 1; + UINT32 Dev31 : 1; + } Bits; + UINT32 Data; +} DEVHIDE_FIELD; + +typedef struct{ + UINT32 DevToHide[NUM_DEVHIDE_REGS]; +} IIO_DEVFUNHIDE; + +typedef struct{ + IIO_DEVFUNHIDE IioStackDevHide[MAX_IIO_STACK]; +}IIO_DEVFUNHIDE_TABLE; + +typedef struct { + UINT8 CpuType; + UINT8 CpuStepping; + UINT8 CpuSubType; + UINT8 IsocEnable; + UINT8 EVMode; + UINT32 meRequestedSize; + UINT8 DmiVc[MaxDmiVcType]; + UINT8 DmiVcId[MaxDmiVcType]; + UINT8 DmiTc[MaxDmiTcType]; + UINT8 PlatformType; + UINT8 IOxAPICCallbackBootEvent; + UINT8 RasOperation; + UINT8 SocketUnderOnline; + UINT8 CompletedReadyToBootEventServices; + UINT8 SocketPresent[MaxIIO]; + UINT8 SocketBaseBusNumber[MaxIIO]; + UINT8 SocketLimitBusNumber[MaxIIO]; + UINT8 StackPresentBitmap[MaxIIO]; + UINT64_STRUCT SegMmcfgBase[MaxIIO]; + UINT8 SegmentSocket[MaxIIO]; + UINT8 SocketStackPersonality[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBus[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackBaseBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketStackLimitBusNumber[MaxIIO][MAX_IIO_STACK]; + UINT8 SocketPortBusNumber[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 StackPerPort[MaxIIO][NUMBER_PORTS_PER_SOCKET]; + UINT8 SocketUncoreBusNumber[MaxIIO]; + UINT32 PchIoApicBase; + UINT32 PciResourceMem32Base[MaxIIO]; + UINT32 PciResourceMem32Limit[MaxIIO]; + UINT8 Pci64BitResourceAllocation; + UINT32 StackPciResourceMem32Limit[MaxIIO][MAX_IIO_STACK]; + UINT32 VtdBarAddress[MaxIIO][MAX_IIO_STACK]; + UINT32 IoApicBase[MaxIIO][MAX_IIO_STACK]; + UINT32 RcBaseAddress; + UINT64 PciExpressBase; + UINT32 PmBase; + UINT32 PchSegRegBaseAddress; + UINT8 PcieRiser1Type; + UINT8 PcieRiser2Type; + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT8 Emulation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT8 IODC; + UINT8 MultiPch; + UINT8 FpgaActive[MaxIIO]; +} IIO_V_DATA; + +typedef struct { + UINT8 Device; + UINT8 Function; +} IIO_PORT_INFO; + +typedef struct { + UINT8 Valid; + UINT8 IioUplinkPortIndex; //defines platform specific uplink port index (if any else FF) + IIO_PORT_INFO UplinkPortInfo; +}IIO_UPLINK_PORT_INFO; + +typedef struct _INTEL_IIO_PORT_INFO { + UINT8 Device; + UINT8 Function; + UINT8 RtoDevice; + UINT8 RtoFunction; + UINT8 RtoClusterDevice; + UINT8 RtoClusterFunction; + UINT8 RtoReutLinkSel; + UINT8 SuperClusterPort; +} INTEL_IIO_PORT_INFO; + +typedef struct _INTEL_DMI_PCIE_INFO { + INTEL_IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} INTEL_DMI_PCIE_INFO; + +typedef struct _INTEL_IIO_PRELINK_DATA { + INTEL_DMI_PCIE_INFO PcieInfo; + IIO_UPLINK_PORT_INFO UplinkInfo[MaxIIO]; +} INTEL_IIO_PRELINK_DATA; + +typedef struct { + UINT8 PciePortPresent[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortConfig[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortOwnership[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 CurrentPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 MaxPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 LinkedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 SpeedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 LaneReversedPXPMap[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortMaxWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegWidth[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + UINT8 PciePortNegSpeed[MaxIIO*NUMBER_PORTS_PER_SOCKET]; + IIO_PTR_ADDRESS PtrAddress; + IIO_PTR_ADDRESS PtrPcieTopology; + UINT64 McastRsvdMemory; + DMA_HOST DMAhost[MaxIIO]; + UINT8 resetRequired; +} IIO_OUT_DATA; + +typedef struct { + IIO_V_DATA IioVData; + INTEL_IIO_PRELINK_DATA PreLinkData; + IIO_OUT_DATA IioOutData; +} IIO_VAR; + +typedef struct { + IIO_CONFIG SetupData; + IIO_VAR IioVar; +} IIO_GLOBALS; + +#pragma pack() + +#endif //_IIO_PLATFORM_DATA_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h new file mode 100644 index 0000000000..f91a879a4e --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioRegs.h @@ -0,0 +1,320 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IIO_REGS_H_ +#define _IIO_REGS_H_ + +/** +================================================================================================== +================================== General Defintions ================================== +================================================================================================== +**/ + +#define NUMBER_PORTS_PER_SOCKET 21 +#define IIO_UPLINK_PORT_INDEX 5 //Port 2A is the uplink port in Neon-City ///TODO Check if this is required for SKX/Purley SKX_TTEST +#define MaxIIO MAX_SOCKET + +#if MAX_SOCKET > 4 +#define TOTAL_CB3_DEVICES 64 // Todo Check SKX CB3 devices (IOAT_TOTAL_FUNCS * MAX_SOCKET). Note: this covers up to 8S. +#define MAX_TOTAL_PORTS 168 //NUMBER_PORTS_PER_SOCKET * MaxIIO. As now, treats setup S0-S3 = S4_S7 as optimal +#else +#define TOTAL_CB3_DEVICES 32 // Todo Check SKX CB3 devices. +#define MAX_TOTAL_PORTS 84 //NUMBER_PORTS_PER_SOCKET * MaxIIO +#endif + +#if MAX_SOCKET > 4 +#define TOTAL_IIO_STACKS 48 // MAX_SOCKET * MAX_IIO_STACK. Not reflect architecture but only sysHost structure! +#define TOTAL_SYSTEM_IIO_STACKS 32 // In term of system architecture support +#else +#define TOTAL_IIO_STACKS 24 // MAX_SOCKET * MAX_IIO_STACK +#define TOTAL_SYSTEM_IIO_STACKS 24 // In term of system architecture support +#endif + +#define NUMBER_NTB_PORTS_PER_SOCKET 3 +#if MAX_SOCKET > 4 +#define MAX_NTB_PORTS 24 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#else +#define MAX_NTB_PORTS 12 // NUMBER_NTB_PORTS_PER_SOCKET * MAX_SOCKET +#endif +#define VMD_STACK_PER_SOCKET 3 +#define VMD_PORT_PER_STACK 4 +#define VMD_PORTS_PER_SOCKET 12 +#if MAX_SOCKET > 4 +#define MAX_VMD_PORTS 96 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#define MAX_VMD_STACKS 24 // VMD_STACK_PER_SOCKET * MAX_SOCKET +#else +#define MAX_VMD_PORTS 48 // VMD_PORTS_PER_SOCKET * MAX_SOCKET +#define MAX_VMD_STACKS 12 // VMD_STACK_PER_SOCKET * MAX_SOCKET +#endif + + +#define VARIABLE_FUNC3_ELEMENTS 4 +#if MAX_SOCKET > 4 +#define MAX_TOTAL_CORE_HIDE 32 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#else +#define MAX_TOTAL_CORE_HIDE 16 //(MAX_SOCKET * VARIABLE_FUNC3_ELEMENTS) +#endif + +#define MAX_IOU_PORT_DEVICES 4 + + +/** +================================================================================================== +================================== IIO Root Port Defintions ==================== +================================================================================================== +**/ +typedef enum { + IioPortA = 0, + IioPortB = 1, + IioPortC = 2, + IioPortD = 3 +}IIOPORTS; + +typedef enum { + IioIou0 = 0, + IioIou1, + IioIou2, + IioMcp0, + IioMcp1, + IioIouMax +} IIOIOUS; + +// +// Bifurcation control register shorthand +// +#define IIO_BIFURCATE_AUTO 0xFF + +// Ports 1D-1A, 2D-2A, 3D-3A +// +#define IIO_BIFURCATE_x4x4x4x4 0 +#define IIO_BIFURCATE_x4x4xxx8 1 +#define IIO_BIFURCATE_xxx8x4x4 2 +#define IIO_BIFURCATE_xxx8xxx8 3 +#define IIO_BIFURCATE_xxxxxx16 4 +#define IIO_BIFURCATE_xxxxxxxx 0xF + +#define PORT_0_INDEX 0 +#define PCIE_PORT_2_DEV 0x02 + +// IOU2 +#define PORT_1A_INDEX 1 +#define PORT_1B_INDEX 2 +#define PORT_1C_INDEX 3 +#define PORT_1D_INDEX 4 +// IOU0 +#define PORT_2A_INDEX 5 +#define PORT_2B_INDEX 6 +#define PORT_2C_INDEX 7 +#define PORT_2D_INDEX 8 +// IOU1 +#define PORT_3A_INDEX 9 +#define PORT_3B_INDEX 10 +#define PORT_3C_INDEX 11 +#define PORT_3D_INDEX 12 +//MCP0 +#define PORT_4A_INDEX 13 +#define PORT_4B_INDEX 14 +#define PORT_4C_INDEX 15 +#define PORT_4D_INDEX 16 +//MCP1 +#define PORT_5A_INDEX 17 +#define PORT_5B_INDEX 18 +#define PORT_5C_INDEX 19 +#define PORT_5D_INDEX 20 + +// +#define SOCKET_0_INDEX 0 +#define SOCKET_1_INDEX 21 +#define SOCKET_2_INDEX 42 +#define SOCKET_3_INDEX 63 +#define SOCKET_4_INDEX 84 +#define SOCKET_5_INDEX 105 +#define SOCKET_6_INDEX 126 +#define SOCKET_7_INDEX 147 + +#define PCIE_PORT_0_DEV 0x00 +#define PCIE_PORT_0_FUNC 0x00 + +#define PCIE_PORT_1A_DEV 0x00 +#define PCIE_PORT_1B_DEV 0x01 +#define PCIE_PORT_1C_DEV 0x02 +#define PCIE_PORT_1D_DEV 0x03 +#define PCIE_PORT_1A_FUNC 0x00 +#define PCIE_PORT_1B_FUNC 0x00 +#define PCIE_PORT_1C_FUNC 0x00 +#define PCIE_PORT_1D_FUNC 0x00 + +#define PCIE_PORT_2A_DEV 0x00 +#define PCIE_PORT_2B_DEV 0x01 +#define PCIE_PORT_2C_DEV 0x02 +#define PCIE_PORT_2D_DEV 0x03 +#define PCIE_PORT_2A_FUNC 0x00 +#define PCIE_PORT_2B_FUNC 0x00 +#define PCIE_PORT_2C_FUNC 0x00 +#define PCIE_PORT_2D_FUNC 0x00 + +#define PCIE_PORT_3A_DEV 0x00 +#define PCIE_PORT_3B_DEV 0x01 +#define PCIE_PORT_3C_DEV 0x02 +#define PCIE_PORT_3D_DEV 0x03 +#define PCIE_PORT_3A_FUNC 0x00 +#define PCIE_PORT_3B_FUNC 0x00 +#define PCIE_PORT_3C_FUNC 0x00 +#define PCIE_PORT_3D_FUNC 0x00 + +#define PCIE_PORT_4A_DEV 0x00 +#define PCIE_PORT_4B_DEV 0x01 +#define PCIE_PORT_4C_DEV 0x02 +#define PCIE_PORT_4D_DEV 0x03 +#define PCIE_PORT_4A_FUNC 0x00 +#define PCIE_PORT_4B_FUNC 0x00 +#define PCIE_PORT_4C_FUNC 0x00 +#define PCIE_PORT_4D_FUNC 0x00 + +#define PCIE_PORT_5A_DEV 0x00 +#define PCIE_PORT_5B_DEV 0x01 +#define PCIE_PORT_5C_DEV 0x02 +#define PCIE_PORT_5D_DEV 0x03 +#define PCIE_PORT_5A_FUNC 0x00 +#define PCIE_PORT_5B_FUNC 0x00 +#define PCIE_PORT_5C_FUNC 0x00 +#define PCIE_PORT_5D_FUNC 0x00 + +#define PCIE_PORT_GLOBAL_RTO_DEV 0x07 +#define PCIE_PORT_GLOBAL_RTO_FUNC 0x07 + +#define PCIE_PORT_0_RTO_DEV 0x07 +#define PCIE_PORT_0_RTO_FUNC 0x00 + +#define PCIE_PORT_1A_RTO_DEV 0x07 +#define PCIE_PORT_1A_RTO_FUNC 0x00 +#define PCIE_PORT_1B_RTO_DEV 0x07 +#define PCIE_PORT_1B_RTO_FUNC 0x01 +#define PCIE_PORT_1C_RTO_DEV 0x07 +#define PCIE_PORT_1C_RTO_FUNC 0x02 +#define PCIE_PORT_1D_RTO_DEV 0x07 +#define PCIE_PORT_1D_RTO_FUNC 0x03 + + +#define PCIE_PORT_2A_RTO_DEV 0x07 +#define PCIE_PORT_2A_RTO_FUNC 0x00 +#define PCIE_PORT_2B_RTO_DEV 0x07 +#define PCIE_PORT_2B_RTO_FUNC 0x01 +#define PCIE_PORT_2C_RTO_DEV 0x07 +#define PCIE_PORT_2C_RTO_FUNC 0x02 +#define PCIE_PORT_2D_RTO_DEV 0x07 +#define PCIE_PORT_2D_RTO_FUNC 0x03 + +#define PCIE_PORT_3A_RTO_DEV 0x07 +#define PCIE_PORT_3A_RTO_FUNC 0x00 +#define PCIE_PORT_3B_RTO_DEV 0x07 +#define PCIE_PORT_3B_RTO_FUNC 0x01 +#define PCIE_PORT_3C_RTO_DEV 0x07 +#define PCIE_PORT_3C_RTO_FUNC 0x02 +#define PCIE_PORT_3D_RTO_DEV 0x07 +#define PCIE_PORT_3D_RTO_FUNC 0x03 + +#define PCIE_PORT_4A_RTO_DEV 0x07 +#define PCIE_PORT_4A_RTO_FUNC 0x00 +#define PCIE_PORT_4B_RTO_DEV 0x07 +#define PCIE_PORT_4B_RTO_FUNC 0x01 +#define PCIE_PORT_4C_RTO_DEV 0x07 +#define PCIE_PORT_4C_RTO_FUNC 0x02 +#define PCIE_PORT_4D_RTO_DEV 0x07 +#define PCIE_PORT_4D_RTO_FUNC 0x03 + +#define PCIE_PORT_5A_RTO_DEV 0x07 +#define PCIE_PORT_5A_RTO_FUNC 0x00 +#define PCIE_PORT_5B_RTO_DEV 0x07 +#define PCIE_PORT_5B_RTO_FUNC 0x01 +#define PCIE_PORT_5C_RTO_DEV 0x07 +#define PCIE_PORT_5C_RTO_FUNC 0x02 +#define PCIE_PORT_5D_RTO_DEV 0x07 +#define PCIE_PORT_5D_RTO_FUNC 0x03 + +#define PCIE_PORT_0_LINK_SEL 0x00 +#define PCIE_PORT_1A_LINK_SEL 0x00 +#define PCIE_PORT_1B_LINK_SEL 0x01 +#define PCIE_PORT_1C_LINK_SEL 0x02 +#define PCIE_PORT_1D_LINK_SEL 0x03 +#define PCIE_PORT_2A_LINK_SEL 0x00 +#define PCIE_PORT_2B_LINK_SEL 0x01 +#define PCIE_PORT_2C_LINK_SEL 0x02 +#define PCIE_PORT_2D_LINK_SEL 0x03 +#define PCIE_PORT_3A_LINK_SEL 0x00 +#define PCIE_PORT_3B_LINK_SEL 0x01 +#define PCIE_PORT_3C_LINK_SEL 0x02 +#define PCIE_PORT_3D_LINK_SEL 0x03 +#define PCIE_PORT_4A_LINK_SEL 0x00 +#define PCIE_PORT_4B_LINK_SEL 0x01 +#define PCIE_PORT_4C_LINK_SEL 0x02 +#define PCIE_PORT_4D_LINK_SEL 0x03 +#define PCIE_PORT_5A_LINK_SEL 0x00 +#define PCIE_PORT_5B_LINK_SEL 0x01 +#define PCIE_PORT_5C_LINK_SEL 0x02 +#define PCIE_PORT_5D_LINK_SEL 0x03 + +#define PCIE_PORT_0_SUPER_CLUSTER_PORT 0x00 +#define PCIE_PORT_1A_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1B_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1C_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_1D_SUPER_CLUSTER_PORT 0x01 +#define PCIE_PORT_2A_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2B_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2C_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_2D_SUPER_CLUSTER_PORT 0x05 +#define PCIE_PORT_3A_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3B_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3C_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_3D_SUPER_CLUSTER_PORT 0x09 +#define PCIE_PORT_4A_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4B_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4C_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_4D_SUPER_CLUSTER_PORT 0x0D +#define PCIE_PORT_5A_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5B_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5C_SUPER_CLUSTER_PORT 0x11 +#define PCIE_PORT_5D_SUPER_CLUSTER_PORT 0x11 + +#define PORT_LINK_WIDTH_x16 16 +#define PORT_LINK_WIDTH_x8 8 +#define PORT_LINK_WIDTH_x4 4 +#define PORT_LINK_WIDTH_x2 2 +#define PORT_LINK_WIDTH_x1 1 + +// +// Port Config Mode +// +#define REGULAR_PCIE_OWNERSHIP 0 +#define PCIE_PORT_REGULAR_MODE 1 +#define PCIE_PORT_NTB_MODE 2 +#define VMD_OWNERSHIP 3 +#define PCIEAIC_OCL_OWNERSHIP 4 + + +/** +================================================================================================== +================================== Devide Hide Definitions ======================================= +================================================================================================== +**/ + +#define NUM_DEVHIDE_REGS 8 +// Hide all 8 Devices for every Stack +#define MAX_DEVHIDE_REGS (MAX_IIO_STACK * NUM_DEVHIDE_REGS) +#if MaxIIO > 4 +#define MAX_DEVHIDE_REGS_PER_SYSTEM 384 //(MAX_DEVHIDE_REGS * MaxIIO) +#else +#define MAX_DEVHIDE_REGS_PER_SYSTEM 192 //(MAX_DEVHIDE_REGS * MaxIIO) +#endif + +#endif //_IIO_REGS_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h new file mode 100644 index 0000000000..bd505703b0 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Iio/IioSetupDefinitions.h @@ -0,0 +1,117 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef IIOSETUPDEFINITIONS_H_ +#define IIOSETUPDEFINITIONS_H_ + +/** +================================================================================================== +================= Equates common for Setup options (.vfr/.hfr) and source files (.c/.h) ========== +================================================================================================== +**/ + +#define PCIE_ASPM_AUTO 7 +#define PCIE_ASPM_DISABLE 0 +#define PCIE_ASPM_L0S_ONLY 1 +#define PCIE_ASPM_L1_ONLY 2 +#define PCIE_ASPM_L0S_L1_BOTH 3 + +#define PCIE_LINK_SPEED_AUTO 0 +#define PCIE_LINK_SPEED_GEN1 1 +#define PCIE_LINK_SPEED_GEN2 2 +#define PCIE_LINK_SPEED_GEN3 3 + +#define PCIE_L0S_4US_8US 3 +#define PCIE_L1_8US_16US 4 + +#define IIO_OPTION_AUTO 2 +#define IIO_OPTION_ENABLE 1 +#define IIO_OPTION_DISABLE 0 + +#define GEN3MANUAL_PH2_PRECURSOR_MIN 0 +#define GEN3MANUAL_PH2_CURSOR_MIN 0 +#define GEN3MANUAL_PH2_POSTCURSOR_MIN 0 + +#define GEN3MANUAL_PH2_PRECURSOR_MAX 63 +#define GEN3MANUAL_PH2_CURSOR_MAX 63 +#define GEN3MANUAL_PH2_POSTCURSOR_MAX 63 + +#define GEN3MANUAL_PH2_PRECURSOR_DEFAULT 11 +#define GEN3MANUAL_PH2_CURSOR_DEFAULT 41 +#define GEN3MANUAL_PH2_POSTCURSOR_DEFAULT 11 + +#define GEN3MANUAL_PH3_PRECURSOR_MIN 0 +#define GEN3MANUAL_PH3_CURSOR_MIN 0 +#define GEN3MANUAL_PH3_POSTCURSOR_MIN 0 + +#define GEN3MANUAL_PH3_PRECURSOR_MAX 63 +#define GEN3MANUAL_PH3_CURSOR_MAX 63 +#define GEN3MANUAL_PH3_POSTCURSOR_MAX 63 + +#define GEN3MANUAL_PH3_PRECURSOR_DEFAULT 11 +#define GEN3MANUAL_PH3_CURSOR_DEFAULT 41 +#define GEN3MANUAL_PH3_POSTCURSOR_DEFAULT 11 + +#define RTO_GEN3_OVERRIDE_MODE_UNIPHY 0 +#define RTO_GEN3_OVERRIDE_MODE_MANUAL 1 +#define RTO_GEN3_OVERRIDE_MODE_TEST_CARD 2 +#define RTO_GEN3_OVERRIDE_MODE_ALTERNATE_TXEQ 3 + +#define RTO_GEN3_TEST_CARD_LAGUNA 0 +#define RTO_GEN3_TEST_CARD_NTB 1 + +#define RTO_GEN3_EQ_MODE_TESTCARD 1 +#define RTO_GEN3_EQ_MODE_NTB_TESTCARD 2 + + +#define COMPLETION_TIMEOUT_260MS_900MS 9 + +#define SNOOP_RESP_DEF_VALUE 6 + +#define MC_INDEX_POS_12 0xC + +#define MC_NUM_GROUP_8 8 + +#define CONFIG_IOU_AUTO 0xFF + +#define NTB_BARSIZE_PBAR23_DEFAULT 0xC +#define NTB_BARSIZE_PBAR45_DEFAULT 0xC +#define NTB_BARSIZE_PBAR4_DEFAULT 0xC +#define NTB_BARSIZE_PBAR5_DEFAULT 0xC +#define NTB_BARSIZE_SBAR23_DEFAULT 0xC +#define NTB_BARSIZE_SBAR45_DEFAULT 0xC +#define NTB_BARSIZE_SBAR4_DEFAULT 0xC +#define NTB_BARSIZE_SBAR5_DEFAULT 0xC +#define NTB_IIO_XLINK_CTL_DSD_USP 2 + +#define VMD_CFG_BAR_SIZE_DEFAULT 25 +#define VMD_MEM_BAR_SIZE1_DEFAULT 25 +#define VMD_MEM_BAR_SIZE2_DEFAULT 20 + +#define VMD_32BIT_NONPREFETCH 0 +#define VMD_64BIT_NONPREFETCH 1 +#define VMD_64BIT_PREFETCH 2 + +#define IODC_DISABLE 0 +#define IODC_AUTO 1 +#define IODC_EN_REM_INVITOM_PUSH 2 +#define IODC_EN_REM_INVITOM_ALLOCFLOW 3 +#define IODC_EN_REM_INVITOM_ALLOC_NONALLOC 4 +#define IODC_EN_REM_INVITOM_AND_WCILF 5 +#define IODC_GLOBAL_KTI_OPTION 6 + +#define PCIE_PORT_DISABLE 0 +#define PCIE_PORT_ENABLE 1 +#define PCIE_PORT_AUTO 2 + +#endif /* IIOSETUPDEFINITIONS_H_ */ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h new file mode 100644 index 0000000000..a393e46639 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiDisc.h @@ -0,0 +1,32 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _KTI_DISCOVERY_H_ +#define _KTI_DISCOVERY_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant conditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" +#include "KtiSi.h" + +#define MAX_TREE_NODES (MAX_SOCKET + 2) // 2 additional nodes since a node will appear more than once in the tree when it is being constructed +#define MAX_RING_TREE_NODES 46 // A CPU with 3 links supported will have 1 + 1*3 + 3*2 + 6*2 + 12*2 = 46 nodes maximum in ring tree +#define MAX_RINGS 6 // Maximum number of rings possible in systems with upto 8 sockets (HyperCube) +#define CPUS_PER_RING 4 // # of CPUs in a CPU ring +#define VN0 0 +#define VN1 1 +#define TX 0 +#define RX 1 + +#endif // _KTI_DISCOVERY_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h new file mode 100644 index 0000000000..afbd81265b --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiHost.h @@ -0,0 +1,142 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +// Definition Flag: +// 1. KTI_HW_PLATFORM -> run with real hardware or SoftIVT +// 2. KTI_SW_SIMULATION -> run with KTIRC Simulation +// 3. IA32 -> run with IA32 mode + + +#ifndef _KTI_HOST_H_ +#define _KTI_HOST_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant conditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" +#include "KtiSi.h" +#include "KtiDisc.h" + +#pragma pack(1) + +typedef INT32 KTI_STATUS; +#ifndef NULL +#define NULL 0 +#endif +#define CONST const +#define STATIC static +#define VOID void +#define VOLATILE volatile +#define KTI_SUCCESS 0 +#define KTI_REBOOT 1 +#define KTI_SNC_CHANGED 2 +#define KTI_IGNORE 3 +#define KTI_FAILURE -1 + +// +// Warning log +// +#define MAX_WARNING_LOGS 16 + +typedef enum { + NORMAL_OPERATION = 0, + RECOVERY_OPERATION +} SNC_COLDRESET_REGISTER_OPERATION_TYPE; + +typedef enum { + KTI_GROUP = 0, +} GROUP_TYPE; + +/********************************************************* + KTIRC Host Structure Related +*********************************************************/ + +typedef enum { + KTI_LINK0 = 0x0, + KTI_LINK1, + KTI_LINK2 +} KTI_LOGIC_LINK; + +typedef enum { + FULL_SPEED = 0, + HALF_SPEED +} KTI_LINK_SPEED_TYPE; + + +// +// Definitions to be used in Eparam tables: +// +typedef enum { + PER_LANES_TXEQ_ENABLED = 0, // each lane use different TXEQ value + ALL_LANES_TXEQ_ENABLED // all lanes use same TXEQ value +} LANE_TXEQ_TYPE; + +// +// Number of Clusters. +// +typedef enum { + CLUSTER_MODE_1, + CLUSTER_MODE_2, +} CLUSTER_MODE; + +typedef enum { + LCC = 0, // 10c + MCC, // 14c + HCC, // 22c + XCC, // 28c + MAX_CHOP_TYPES +} PHYSICAL_CHOP; + + +// +// PHY settings that are system dependent. Need 1 of these for each socket/link/freq. +// + +typedef struct { + UINT8 SocketID; + UINT8 AllLanesUseSameTxeq; + UINT8 Freq; + UINT32 Link; + UINT32 TXEQL[20]; + UINT32 CTLEPEAK[5]; +} PER_LANE_EPARAM_LINK_INFO; + +// +// This is for full speed mode, all lanes have the same TXEQ setting +// +typedef struct { + UINT8 SocketID; + UINT8 Freq; + UINT32 Link; + UINT32 AllLanesTXEQ; + UINT8 CTLEPEAK; +} ALL_LANES_EPARAM_LINK_INFO; + +#define ADAPTIVE_CTLE 0x3f +#define PER_LANE_ADAPTIVE_CTLE 0X3f3f3f3f + +typedef enum { + TYPE_UBOX = 0, + TYPE_UBOX_IIO, + TYPE_MCP, + TYPE_FPGA, + TYPE_DISABLED, // This item must be prior to stack specific disable types + TYPE_UBOX_IIO_DIS, + TYPE_MCP_DIS, + TYPE_FPGA_DIS, + TYPE_NONE +} STACK_TYPE; + +#pragma pack() + +#endif // _KTI_HOST_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h new file mode 100644 index 0000000000..41904a724e --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/KtiSi.h @@ -0,0 +1,45 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _KTI_SI_H_ +#define _KTI_SI_H_ +#ifdef _MSC_VER +#pragma warning (disable: 4127 4214 4100) // disable C4127: constant conditional expression +#endif +#include "DataTypes.h" +#include "PlatformHost.h" + +/********************************************************* + KTI Topology Related +*********************************************************/ +#define SI_MAX_CPU_SOCKETS 8 // Maximum CPU sockets supported by Si +#define SI_MAX_KTI_PORTS 3 // Maximum KTI ports supported by Si + +/********************************************************* + IIO Stacks +*********************************************************/ +#define IIO_CSTACK 0 +#define IIO_PSTACK0 1 +#define IIO_PSTACK1 2 +#define IIO_PSTACK2 3 +#define IIO_PSTACK3 4 +#define IIO_PSTACK4 5 +#define MAX_IIO_STACK 6 + +/********************************************************* + M3KTI +*********************************************************/ +#define MAX_M3KTI 2 +#define MAX_PORT_IN_M3KTI 2 + +#endif // _KTI_SI_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h new file mode 100644 index 0000000000..4c03534e8a --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Protocol/CpuCsrAccess.h @@ -0,0 +1,149 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _CPUCSRACCESS_PROTOCOL_H_
+#define _CPUCSRACCESS_PROTOCOL_H_
+
+//
+// CPU CSR Access Protocol GUID
+//
+// {0067835F-9A50-433a-8CBB-852078197814}
+#define EFI_CPU_CSR_ACCESS_GUID \
+ { \
+ 0x67835f, 0x9a50, 0x433a, 0x8c, 0xbb, 0x85, 0x20, 0x78, 0x19, 0x78, 0x14 \
+ }
+
+//#define REG_ADDR( bus, dev, func, reg, size ) ((size << 28) + ((bus+2) << 20) + (dev << 15) + (func << 12) + reg)
+
+typedef
+UINT64
+(EFIAPI *GET_CPU_CSR_ADDRESS) (
+ IN UINT8 SocId,
+ IN UINT8 BoxInst,
+ IN UINT32 Offset,
+ IN OUT UINT8 *Size
+ );
+
+typedef
+UINT32
+(EFIAPI *READ_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 BoxInst,
+ IN UINT32 Offset
+ );
+
+typedef
+VOID
+(EFIAPI *WRITE_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 BoxInst,
+ IN UINT32 RegOffset,
+ IN UINT32 Data
+ );
+
+typedef
+UINT32
+(EFIAPI *READ_MC_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 McId,
+ IN UINT32 Offset
+ );
+
+typedef
+VOID
+(EFIAPI *WRITE_MC_CPU_CSR) (
+ IN UINT8 SocId,
+ IN UINT8 McId,
+ IN UINT32 RegOffset,
+ IN UINT32 Data
+ );
+
+typedef
+UINTN
+(EFIAPI *GET_MC_CPU_ADDR) (
+ IN UINT8 SocId,
+ IN UINT8 McId,
+ IN UINT32 RegOffset
+ );
+
+typedef
+UINT32
+(EFIAPI *READ_PCI_CSR) (
+ IN UINT8 socket,
+ IN UINT32 reg
+ );
+
+typedef
+VOID
+(EFIAPI *WRITE_PCI_CSR) (
+ IN UINT8 socket,
+ IN UINT32 reg,
+ IN UINT32 data
+ );
+
+typedef
+UINT32
+(EFIAPI *GET_PCI_CSR_ADDR) (
+ IN UINT8 socket,
+ IN UINT32 reg
+ );
+
+typedef
+VOID
+(EFIAPI *UPDATE_CPU_CSR_ACCESS_VAR) (
+ VOID
+ );
+
+typedef
+UINT32
+(EFIAPI *BIOS_2_PCODE_MAILBOX_WRITE) (
+ IN UINT8 socket,
+ IN UINT32 command,
+ IN UINT32 data
+ );
+
+typedef
+UINT64
+(EFIAPI *BIOS_2_VCODE_MAILBOX_WRITE) (
+ IN UINT8 socket,
+ IN UINT32 command,
+ IN UINT32 data
+ );
+
+typedef
+VOID
+(EFIAPI *BREAK_AT_CHECK_POINT) (
+ IN UINT8 majorCode,
+ IN UINT8 minorCode,
+ IN UINT16 data
+ );
+
+typedef struct _EFI_CPU_CSR_ACCESS_PROTOCOL {
+ GET_CPU_CSR_ADDRESS GetCpuCsrAddress;
+ READ_CPU_CSR ReadCpuCsr;
+ WRITE_CPU_CSR WriteCpuCsr;
+ BIOS_2_PCODE_MAILBOX_WRITE Bios2PcodeMailBoxWrite;
+ BIOS_2_VCODE_MAILBOX_WRITE Bios2VcodeMailBoxWrite;
+ READ_MC_CPU_CSR ReadMcCpuCsr;
+ WRITE_MC_CPU_CSR WriteMcCpuCsr;
+ GET_MC_CPU_ADDR GetMcCpuCsrAddress;
+ UPDATE_CPU_CSR_ACCESS_VAR UpdateCpuCsrAccessVar;
+ READ_PCI_CSR ReadPciCsr;
+ WRITE_PCI_CSR WritePciCsr;
+ GET_PCI_CSR_ADDR GetPciCsrAddress;
+ BREAK_AT_CHECK_POINT BreakAtCheckpoint;
+} EFI_CPU_CSR_ACCESS_PROTOCOL;
+
+extern EFI_GUID gEfiCpuCsrAccessGuid;
+
+#endif
diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h new file mode 100644 index 0000000000..2c03670a02 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Chip/Skx/Include/Setup/IioUniversalData.h @@ -0,0 +1,176 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _IIO_UNIVERSAL_DATA_ +#define _IIO_UNIVERSAL_DATA_ + +#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } +#include "SysHost.h" +#include "UncoreCommonIncludes.h" +#include <Guid/SocketVariable.h> + +//--------------------------------------------------------------------------------------// +// Structure definitions for Universal Data Store (UDS) +//--------------------------------------------------------------------------------------// +#define UINT64 unsigned long long + +#pragma pack(1) + + +typedef struct { + UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation) + UINT8 PeerSocId; // Socket ID + UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - IIO) + UINT8 PeerPort; // Port of the peer socket +}QPI_PEER_DATA; + +typedef struct { + UINT8 Valid; + UINT8 SocketFirstBus; + UINT8 SocketLastBus; + UINT8 segmentSocket; + UINT8 PcieSegment; + UINT64_STRUCT SegMmcfgBase; + UINT8 stackPresentBitmap; + UINT8 StackBus[MAX_IIO_STACK]; + UINT8 M2PciePresentBitmap; + UINT8 TotM3Kti; + UINT8 TotCha; + UINT32 ChaList; + UINT32 SocId; + QPI_PEER_DATA PeerInfo[MAX_KTI_PORTS]; // QPI LEP info +} QPI_CPU_DATA; + +typedef struct { + UINT8 Valid; + UINT8 SocId; + QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info +} QPI_IIO_DATA; + +typedef struct { + IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} IIO_DMI_PCIE_INFO; + +typedef struct _STACK_RES { + UINT8 Personality; + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; + UINT32 VtdBarAddress; +} STACK_RES; + +typedef struct { + UINT8 Valid; + UINT8 SocketID; // Socket ID of the IIO (0..3) + UINT8 BusBase; + UINT8 BusLimit; + UINT16 PciResourceIoBase; + UINT16 PciResourceIoLimit; + UINT32 IoApicBase; + UINT32 IoApicLimit; + UINT32 PciResourceMem32Base; + UINT32 PciResourceMem32Limit; + UINT64 PciResourceMem64Base; + UINT64 PciResourceMem64Limit; + STACK_RES StackRes[MAX_IIO_STACK]; + UINT32 RcBaseAddress; + IIO_DMI_PCIE_INFO PcieInfo; + UINT8 DmaDeviceCount; +} IIO_RESOURCE_INSTANCE; + +typedef struct { + UINT16 PlatGlobalIoBase; // Global IO Base + UINT16 PlatGlobalIoLimit; // Global IO Limit + UINT32 PlatGlobalMmiolBase; // Global Mmiol base + UINT32 PlatGlobalMmiolLimit; // Global Mmiol limit + UINT64 PlatGlobalMmiohBase; // Global Mmioh Base [43:0] + UINT64 PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0] + QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU + QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO + UINT32 MemTsegSize; + UINT32 MemIedSize; + UINT64 PciExpressBase; + UINT32 PciExpressSize; + UINT32 MemTolm; + IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; + UINT8 numofIIO; + UINT8 MaxBusNumber; + UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv + UINT8 MaxCoreToBusRatio[MAX_SOCKET]; // Package Max Non-turbo Ratio (per socket). + UINT8 MinCoreToBusRatio[MAX_SOCKET]; // Package Maximum Efficiency Ratio (per socket). + UINT8 EVMode; + UINT8 Pci64BitResourceAllocation; + UINT8 SkuPersonality[MAX_SOCKET]; + UINT8 VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + UINT16 IoGranularity; + UINT32 MmiolGranularity; + UINT64_STRUCT MmiohGranularity; + UINT8 RemoteRequestThreshold; +} PLATFORM_DATA; + +typedef struct { + UINT8 CurrentCsiLinkSpeed;// Current programmed CSI Link speed (Slow/Full speed mode) + UINT8 CurrentCsiLinkFrequency; // Current requested CSI Link frequency (in GT) + UINT32 OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM + UINT8 IsocEnable; + UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB + UINT8 DmiVc1; + UINT8 DmiVcm; + UINT32 CpuPCPSInfo; + UINT8 MinimumCpuStepping; + UINT8 LtsxEnable; + UINT8 MctpEn; + UINT8 cpuType; + UINT8 cpuSubType; + UINT8 SystemRasType; + UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC + UINT32 socketPresentBitMap; // bitmap of sockets with CPUs present detected by QPI RC + UINT32 FpgaPresentBitMap; // bitmap of NID w/ fpga present detected by QPI RC + UINT16 tolmLimit; + UINT32 tohmLimit; + UINT32 mmCfgBase; + UINT32 RcVersion; + UINT8 DdrXoverMode; // DDR 2.2 Mode + // For RAS + UINT8 bootMode; + UINT8 OutClusterOnDieEn; // Whether RC enabled COD support + UINT8 OutSncEn; + UINT8 OutNumOfCluster; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT8 numChPerMC; + UINT8 maxCh; + UINT8 maxIMC; + UINT16 LlcSizeReg; + UINT8 chEnabled[MAX_SOCKET][MAX_CH]; + UINT8 mcId[MAX_SOCKET][MAX_CH]; + UINT8 memNode[MC_MAX_NODE]; + UINT8 IoDcMode; + UINT8 CpuAccSupport; + UINT8 SmbusErrorRecovery; +} SYSTEM_STATUS; + +typedef struct { + PLATFORM_DATA PlatformData; + SYSTEM_STATUS SystemStatus; + UINT32 OemValue; +} IIO_UDS; +#pragma pack() + +#endif |