diff options
Diffstat (limited to 'Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include')
13 files changed, 1713 insertions, 0 deletions
diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h new file mode 100644 index 0000000000..6a5f37d3d4 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CpuHost.h @@ -0,0 +1,259 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef cpuhost_h +#define cpuhost_h +#include "PlatformHost.h" +#include "DataTypes.h" +#include "SysHostChipCommon.h" + +#define inline __inline + +// +// CPU ExtFamily/Family/Model bit[19:4] of cpuid(1)_eax +// +#ifndef CPU_FAMILY_HSX +#define CPU_FAMILY_HSX 0x306F // Haswell CPU +#endif +#ifndef CPU_FAMILY_SKX +#define CPU_FAMILY_SKX 0x5065 // Skylake CPU +#endif +#ifndef CPU_FAMILY_ICX +#define CPU_FAMILY_ICX 0x606a // IceLake CPU +#endif +#ifndef CPU_FAMILY_KNH +#define CPU_FAMILY_KNH 0x706F // KnightsHill CPU +#endif + + +//typedef INT32 CPU_STATUS; // this causes MiniBIOS build failure +typedef int CPU_STATUS; +#define CPU_SUCCESS 0 +#define CPU_FAILURE -1 + + +// +// Reset types needed post execution +// +#define POST_RESET_NO_RESET 0x0 +#define POST_RESET_WARM 0x2 // bit1 +#define POST_RESET_POWERGOOD 0x4 // bit2 +#define POST_RESET_AMI 0x8 // bit3 + +// +// Max reservable TOR entries defines +// +#define MAX_TOR_ENTRIES_ISOC 15 +#define MAX_TOR_ENTRIES_NORMAL 17 + +// +// Error Code used for LogError() +// +#define ERROR_CPU_BIST 0xC0 + #define ERROR_CPU_BIST_MINOR_SOME_SOCKET 0x01 + #define ERROR_CPU_BIST_MINOR_SOME_BISTRESULTMASK 0x02 + #define ERROR_CPU_BIST_MINOR_ALL 0x03 + +// +// Error Codes used for LogError() and LogWarning() +// +#define WARN_CPU_BIST 0xC0 +#define WARN_CPU_BIST_MINOR_LOWER_TILE_RANGE 0x01 +#define WARN_CPU_BIST_MINOR_MIDDLE_TILE_RANGE 0x02 +#define WARN_CPU_BIST_MINOR_UPPER_TILE_RANGE 0x03 +#define WARN_CPU_BIST_MINOR_ALL 0x04 + + +// +// MSR definitions +// +#ifndef MSR_IA32_PLATFORM_ID +#define MSR_IA32_PLATFORM_ID 0x0017 +#endif +#ifndef MSR_APIC_BASE +#define MSR_APIC_BASE 0x001B +#endif +#ifndef MSR_EBC_FREQUENCY_ID +#define MSR_EBC_FREQUENCY_ID 0x002C +#endif +#ifndef MSR_CORE_THREAD_COUNT +#define MSR_CORE_THREAD_COUNT 0x0035 +#endif +#ifndef MSR_SOCKET_ID +#define MSR_SOCKET_ID 0x0039 +#endif +#ifndef MSR_IA32_FEATURE_CONTROL +#define MSR_IA32_FEATURE_CONTROL 0x003A +#endif +#ifndef VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR +#define VIRTUAL_MSR_MCA_ON_NON_NEW_CACHABLE_MMIO_EN_ADDR 0x61 +#endif +#ifndef MCAONNONNEMCACHEABLEMMIO_BIT +#define MCAONNONNEMCACHEABLEMMIO_BIT 0x1 +#endif +#ifndef MSR_IA32_BIOS_UPDT_TRIG +#define MSR_IA32_BIOS_UPDT_TRIG 0x0079 +#endif +#ifndef MSR_TRACE_HUB_STH_ACPIBAR_BASE +#define MSR_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080 +#define B_MSR_TRACE_HUB_STH_ACPIBAR_BASE_LOCK BIT0 +#define V_MSR_TRACE_HUB_STH_ACPIBAR_BASE_MASK 0x0003FFFF +#endif +#ifndef PCH_TRACE_HUB_FW_BASE_ADDRESS +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE0C0000 ///< TraceHub FW MMIO base address +#endif +#ifndef MSR_IA32_BIOS_SIGN_ID +#define MSR_IA32_BIOS_SIGN_ID 0x008B +#endif +#ifndef MSR_PLATFORM_INFO +#define MSR_PLATFORM_INFO 0x00CE +#endif +#ifndef MSR_PMG_CST_CONFIG_CONTROL +#define MSR_PMG_CST_CONFIG_CONTROL 0x00E2 +#endif +#ifndef MSR_PMG_IO_CAPTURE_BASE +#define MSR_PMG_IO_CAPTURE_BASE 0x0E4 +#endif +#ifndef MSR_MCG_CONTAIN +#define MSR_MCG_CONTAIN 0x178 +#define B_MSR_MCG_CONTAIN_PE BIT0 +#endif +#ifndef MSR_IA32_MCG_CAP +#define MSR_IA32_MCG_CAP 0x179 +#define B_MSR_MCG_CAP_GCM BIT24 +#endif +#ifndef MSR_CLOCK_FLEX_MAX +#define MSR_CLOCK_FLEX_MAX 0x0194 +#endif +#ifndef MSR_IA32_PERF_STS +#define MSR_IA32_PERF_STS 0x0198 +#endif +#ifndef MSR_IA32_PERF_CTL +#define MSR_IA32_PERF_CTL 0x0199 +#endif +#ifndef MSR_IA32_MISC_ENABLES +#define MSR_IA32_MISC_ENABLES 0x01A0 +#endif +#ifndef IA32_MISC_ENABLE +#define IA32_MISC_ENABLE 0x01A0 +#endif +#ifndef FAST_STRING_ENABLE_BIT +#define FAST_STRING_ENABLE_BIT 0x1 +#endif +#ifndef MSR_MISC_PWR_MGMT +#define MSR_MISC_PWR_MGMT 0x01AA +#endif +#ifndef MSR_TURBO_POWER_CURRENT_LIMIT +#define MSR_TURBO_POWER_CURRENT_LIMIT 0x1AC +#endif +#ifndef MSR_TURBO_RATIO_LIMIT +#define MSR_TURBO_RATIO_LIMIT 0x01AD +#endif +#ifndef MSR_POWER_CTRL +#define MSR_POWER_CTRL 0x01FC +#endif +#ifndef MSR_NO_EVICT_MODE +#define MSR_NO_EVICT_MODE 0x02E0 +#endif +#ifndef MSR_IA32_MC7_CTL +#define MSR_IA32_MC7_CTL 0x041C +#endif +#ifndef MSR_IA32_MC8_MISC2 +#define MSR_IA32_MC8_MISC2 0x0288 +#endif +#ifndef MSR_PCIEXBAR +#define MSR_PCIEXBAR 0x0300 +#endif +#ifndef MSR_PPIN_CTL +#define MSR_PPIN_CTL 0x004E +#endif +#ifndef MSR_PPIN +#define MSR_PPIN 0x004F +#endif +#ifndef MSR_MC_CTL +#define MSR_MC_CTL 0x0434 +#endif +#define MSR_UNCORE_FREQ 0x0620 + +#define MSR_UPI0_MC_STS 0x0415 +#define MSR_UPI1_MC_STS 0x0431 +#define MSR_UPI2_MC_STS 0x044d + +#ifndef MTRR_PHYS_BASE_0 +#define MTRR_PHYS_BASE_0 0x0200 +#define MTRR_PHYS_MASK_0 0x0201 +#define MTRR_PHYS_BASE_1 0x0202 +#define MTRR_PHYS_MASK_1 0x0203 +#define MTRR_PHYS_BASE_2 0x0204 +#define MTRR_PHYS_MASK_2 0x0205 +#define MTRR_PHYS_BASE_3 0x0206 +#define MTRR_PHYS_MASK_3 0x0207 +#define MTRR_PHYS_BASE_4 0x0208 +#define MTRR_PHYS_MASK_4 0x0209 +#define MTRR_PHYS_BASE_5 0x020A +#define MTRR_PHYS_MASK_5 0x020B +#define MTRR_PHYS_BASE_6 0x020C +#define MTRR_PHYS_MASK_6 0x020D +#define MTRR_PHYS_BASE_7 0x020E +#define MTRR_PHYS_MASK_7 0x020F +#define MTRR_FIX_64K_00000 0x0250 +#define MTRR_FIX_16K_80000 0x0258 +#define MTRR_FIX_16K_A0000 0x0259 +#define MTRR_FIX_4K_C0000 0x0268 +#define MTRR_FIX_4K_C8000 0x0269 +#define MTRR_FIX_4K_D0000 0x026A +#define MTRR_FIX_4K_D8000 0x026B +#define MTRR_FIX_4K_E0000 0x026C +#define MTRR_FIX_4K_E8000 0x026D +#define MTRR_FIX_4K_F0000 0x026E +#define MTRR_FIX_4K_F8000 0x026F +#define MTRR_DEF_TYPE 0x02FF + +#define MTRR_MEMORY_TYPE_UC 0x00 +#define MTRR_MEMORY_TYPE_WC 0x01 +#define MTRR_MEMORY_TYPE_WT 0x04 +#define MTRR_MEMORY_TYPE_WP 0x05 +#define MTRR_MEMORY_TYPE_WB 0x06 + +#define MTRR_DEF_TYPE_E 0x0800 +#define MTRR_DEF_TYPE_FE 0x0400 +#define MTRR_PHYS_MASK_VALID 0x0800 +#endif // MTRR_PHYS_BASE_0 + +// +// Memory-mapped APIC Offsets +// +#define APIC_LOCAL_APIC_ID 0x020 +#define APIC_ICR_LO 0x300 +#define APIC_ICR_HI 0x310 +#define APIC_TMR_INITIAL_CNT 0x380 +#define APIC_TMR_CURRENT_CNT 0x390 + +// +// APIC Timer runs at 133MHz and by default decrements +// the current count register at once per two clocks. +// t = time in milliseconds +// c = APIC Timer Initial Value +// c = (t * 10^(-6) sec) * (133 * 10^6 count/sec) * (1/2 clocks) +// Notice seconds and exponents cancel out leaving count value +// c = (t * 133 / 2) +// +#define APIC_TMR_1US (1 * 133 / 2) +#define APIC_TMR_10US (10 * 133 / 2) +#define APIC_TMR_20US (20 * 133 / 2) +#define APIC_TMR_100US (100 * 133 / 2) +#define APIC_TMR_200US (200 * 133 / 2) +#define APIC_TMR_10MS (10 * 1000 * 133 / 2) + + +#endif // cpuhost_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h new file mode 100644 index 0000000000..62313e536f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/CsrToPcieAddress.h @@ -0,0 +1,48 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __CSR_TO_PCIE_ADDRESS_H__
+#define __CSR_TO_PCIE_ADDRESS_H__
+
+
+#include <UsraAccessApi.h>
+
+//////////////////////////////////////////////////////////////////////////
+//
+// Common Silicon Address Library
+// This Lib provide the way use platform Library instance
+//
+//////////////////////////////////////////////////////////////////////////
+
+
+/**
+ This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address
+
+ @param[in] Global Global pointer
+ @param[in] Virtual Virtual address
+ @param[in] Address A pointer of the address of the USRA Address Structure
+ @param[out] AlignedAddress A pointer of aligned address converted from USRA address
+
+ @retval NULL The function completed successfully.
+ @retval <>NULL Return Error
+**/
+UINTN
+EFIAPI
+CsrGetPcieAlignAddress (
+ IN VOID *Global,
+ IN BOOLEAN Virtual,
+ IN USRA_ADDRESS *Address,
+ OUT UINTN *AlignedAddress
+ );
+
+#endif
diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h new file mode 100644 index 0000000000..83c1ace657 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/DataTypes.h @@ -0,0 +1,117 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _datatypes_h +#define _datatypes_h + +typedef unsigned char BOOLEAN; +//typedef signed char INT8; // SKX TODO: All string/ASCII/ANSI character based functions need to be ported to use CHAR type due +// to GCC difference. After that porting occurs, then INT8 should be defined as signed type. MS compiler treats char as signed value. +// GNU compiler treats char as unsigned value. This creates havoc when trying to make code compatible with runtime libraries. So... +// henceforth all strings usage will be of type CHAR and not INT8. +typedef char CHAR; +#if defined(__GNUC__) && !defined(MINIBIOS_BUILD) +typedef signed char INT8; +#else +typedef char INT8; +#endif +typedef char CHAR8; +typedef unsigned char UINT8; +typedef short INT16; +typedef unsigned short UINT16; +typedef int INT32; +typedef unsigned int UINT32; +typedef unsigned int MMRC_STATUS; +#define MMRC_SUCCESS 0 +#define MMRC_FAILURE 0xFFFFFFFF +#ifndef CONST +#define CONST const +#endif +#ifndef IN +#define IN +#endif +#ifndef OUT +#define OUT +#endif +#ifndef NULL +#define NULL ((VOID *) 0) +#endif +#ifdef MINIBIOS_BUILD +typedef unsigned long long UINT64; +#endif +typedef unsigned char UCHAR8; +typedef unsigned short CHAR16; +//typedef signed long long SINT64; +//typedef signed long SINT32; +//typedef signed short SINT16; +//typedef signed char SINT8; +#define SINT8 INT8 +#define SINT16 INT16 +#define SINT32 INT32 + +#define CONST const +#define STATIC static +#define VOID void +#define VOLATILE volatile + +#ifndef TRUE +#define TRUE ((BOOLEAN) 1 == 1) +#endif +#ifndef FALSE +#define FALSE ((BOOLEAN) 0 == 1) +#endif + +typedef UINT64 UINTX; + +typedef struct u64_struct { + UINT32 lo; + UINT32 hi; +} UINT64_STRUCT, *PUINT64_STRUCT; + +typedef struct u128_struct { + UINT32 one; + UINT32 two; + UINT32 three; + UINT32 four; +} UINT128; + +typedef struct { + UINT32 Data1; + UINT16 Data2; + UINT16 Data3; + UINT8 Data4[8]; +} GUID_RC; + +#ifndef NT32_BUILD +#if defined (RC_SIM) || defined (MINIBIOS_BUILD) +typedef GUID_RC EFI_GUID; +#endif // #if defined (RC_SIM) || defined (MINIBIOS_BUILD) + +#ifdef MINIBIOS_BUILD +typedef INT32 INTN; +typedef UINT32 UINTN; +typedef UINTN RETURN_STATUS; +#define MAX_BIT (1 << ((sizeof (UINTN) << 3) - 1)) +#define ENCODE_ERROR(StatusCode) ((RETURN_STATUS)(MAX_BIT | (StatusCode))) +#define RETURN_SUCCESS 0 +#define RETURN_UNSUPPORTED ENCODE_ERROR (3) +#define EFIAPI +#define PcdUsraSupportS3 FALSE + +#endif // #ifdef MINIBIOS_BUILD +#endif // #ifndef NT32_BUILD + + +#define MAX_STRING_LENGTH 0x100 + +#endif // _datatypes_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h new file mode 100644 index 0000000000..e9bc5fddf9 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHost.h @@ -0,0 +1,333 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _memhost_h +#define _memhost_h +#include "DataTypes.h" +#include "PlatformHost.h" +#include "SysRegs.h" +#include "MemRegs.h" +#include "MemDefaults.h" +#include "MrcCommonTypes.h" +#include "MemHostChipCommon.h" +#include "KtiSi.h" + +#define MAX_DIMMTABLEINDEX (MAX_CH * MAX_DIMM) + + +#define MAXFIELDVAL(bitfield) (bitfield = 0xffffffff) + +//EFI_GUID definition locations for different BDAT/BSSA cases + +#include <PiPei.h> + +// Debug Build code +// These should be disabled for all normal builds and only enable on demand for debugging +//#define DEBUG_TURNAROUNDS 1 +#define DEBUG_PERFORMANCE_STATS 1 +//#define DEBUG_RDRAND 1 +//#define DEBUG_SENSEAMP 1 + +#ifdef DEBUG_PERFORMANCE_STATS +#define MAX_NOZONE 20 +#endif // DEBUG_PERFORMANCE_STATS + +#define PGT_TIMER_ENABLE 1 +#define PGT_TIMER_DISABLE 0 + +// +// DDR3 frequencies 800 - 2666 +// DDR4 frequencies 1333 - 4200 +// +#define MAX_SUP_FREQ 28 // 26 frequencies are supported (800, 1067, 1333, 1600, 1867, 2133, 2400, 2666, 2933, + // 3200, 3400, 3467, 3600, 3733, 3800, 4000, 4200, 4266, 4400) + + + + +/// +/// External signal names +/// +typedef enum { + RAS_N, CAS_N, WE_N, + BA0, BA1, BA2, + A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, + CS0_N, CS1_N, CS2_N, CS3_N, CS4_N, CS5_N, CS6_N, CS7_N, CS8_N, CS9_N, + CKE0, CKE1, CKE2, CKE3, CKE4, CKE5, + ODT0, ODT1, ODT2, ODT3, ODT4, ODT5, + PAR, ALERT_N, + BG0, BG1, ACT_N, C0, C1, C2, + CK0, CK1, CK2, CK3, CK4, CK5, + FNV_GOOD_PARITY, DESELECT, PRECHARGE, GNT, // these are actually commands as opposed to signals + gsmCsnDelim = INT32_MAX +} GSM_CSN; + +typedef struct { + INT16 left; + INT16 right; +} SIGNAL_EYE; + +#define MAX_PHASE 2 // MAX_PHASE + +// +// Common Core dummy defines +// + +#ifndef MAX_MC_CH +#define MAX_MC_CH 2 // Max channels per MC +#endif +#ifndef MAX_CLUSTERS +#define MAX_CLUSTERS 1 // Maximum number of clusters supported +#endif + +#ifndef MAX_EDC +#define MAX_EDC 1 // Maximum number of EDC supported +#endif + +#define CATCHALL_TIMEOUT 100000 // 100 ms + +#pragma pack(push, 1) + +extern const UINT16 rankSize[MAX_TECH]; ///< Rank size in 64 MB units +extern const UINT16 rankSizeDDR4[MAX_TECH]; ///< Rank size in 64 MB units + + +#define ALL_DRAMS 0xFF // Indicates to write to all DRAMs when in PDA mode +#define ALL_DATABUFFERS 0xFF // Indicates to write to all Buffers in PBA Mode + +typedef enum { +INVALID_BUS, +SMBUS, +EMRS, +CPGC, +SAD, +} BUS_TYPE; + +#ifdef SERIAL_DBG_MSG +#define MemDebugPrint(dbgInfo) debugPrintMem dbgInfo +#define MspDebugPrint(dbgInfo) debugPrintMsp dbgInfo +#define MmrcDebugPrint(dbgInfo) +#define OutputExtendedCheckpoint(dbgInfo) +#else +#define MemDebugPrint(dbgInfo) +#define MspDebugPrint(dbgInfo) +#define MmrcDebugPrint(dbgInfo) +#define OutputExtendedCheckpoint(dbgInfo) OutputCheckpoint dbgInfo +#endif + + +typedef enum +{ + MRC_PF_NULL, // All policy flags turned off. + MRC_PF_COLD = BIT0, // Execute MRC function on cold reset. + MRC_PF_FAST = BIT1, // Execute MRC function on cold reset when S3 data is present. + MRC_PF_WARM = BIT2, // Execute MRC function on warm reset. + MRC_PF_S3 = BIT3, // Execute MRC function on S3 exit. + //MRC_PF_FULL_MRC = BIT4, // Execute MRC function when in Full MRC mode. + //MRC_PF_MINI_MRC = BIT5, // Execute MRC function when in Mini-MRC mode. + MRC_PF_ALL = 0xF // All policy flags turned off. +} PFSelectorType; + +typedef enum +{ + MRC_MP_NULL, // All policy flags turned off + MRC_MP_SERIAL = BIT0, // Execute function when in serial mode + MRC_MP_PARALLEL = BIT1, // Execute function when in parallel mode + MRC_MP_LOOP = BIT2, // Execute function for each socket when in serial mode + MRC_MP_BOTH = MRC_MP_SERIAL | MRC_MP_PARALLEL, // Execute function in both modes + MRC_MP_BOTH_LOOP = MRC_MP_SERIAL | MRC_MP_PARALLEL | MRC_MP_LOOP, // Execute function in both modes and loop +} MPSelectorType; + +// +// TRR defines +// +#define PTRR_MODE BIT0 +#define TRR_MODE_A BIT1 +#define TRR_IMMUNE BIT2 +#ifdef TRR_MODE_B_SUPPORT +#define TRR_MODE_B BIT3 +#endif //TRR_MODE_B_SUPPORT + +typedef struct { + UINT8 stackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket + UINT8 StackBus[MAX_SOCKET][MAX_IIO_STACK]; ///< Bus of each stack + UINT8 SocketFirstBus[MAX_SOCKET]; + UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only + UINT8 SocketLastBus[MAX_SOCKET]; + UINT8 segmentSocket[MAX_SOCKET]; + UINT8 cpuType; + UINT8 stepping; + UINT32 socketPresentBitMap; + UINT32 FpgaPresentBitMap; + UINT32 mmCfgBase; + UINT8 maxCh; + UINT8 maxIMC; + UINT8 numChPerMC; + UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; + UINT8 mcId[MAX_SOCKET][MAX_CH]; + CPU_CSR_ACCESS_VAR_CHIP ///< Chip hook to enable CPU_CSR_ACCESS_VAR fields +} CPU_CSR_ACCESS_VAR; + +#pragma pack(pop) + +/// +/// (MPT_MT - MemeoryPowerTraining_MarginType)param type for power training steps +/// +typedef enum { + GetMargin = 0, + TerMargin = 1, + BerMargin = 2 +} MPT_MT; + +/// +/// (MPT_PT - MemeoryPowerTraining_ParamType)param type for power training steps +/// +typedef enum { + PerChPerByte = 0, + PerRank = 1, + PerStrobe = 2, + PerCh = 3, + PerMC = 4 +} MPT_PT; + +/// +/// (MPT_P - MemeoryPowerTraining_Param)param for power training steps +/// +typedef enum { + traindramron = 0, + trainmcodt = 1, + trainnontgtodt = 2, + trainrttwr = 3, + trainmcron = 4, + traintxeq = 5, + trainimode = 6, + trainctle = 7, + traintcocomp = 8, +} MPT_P; + +#define IMC0 0 +#define IMC1 1 + +// +// PPR Status +// +#define PPR_STS_SUCCESS 0x00 +#define PPR_STS_ADDR_VALID 0x01 +#define PPR_STS_FAILED 0x02 + +#define DRAM_UNKNOWN 0xFF + +#pragma pack(push, 1) +// +// ----------------------------------------------------------------------------- + +// +// NVRAM structures for S3 state +// + +#define MAX_CMD_CSR 16 +#define MAX_SIDE 2 + +// +// ----------------------------------------------------------------------------- +// +// ddrChannelSetup STRUCT 4t ; Channel setup structure declaration +// +// enabled BYTE ? ; Channel enable switch: +// ; 0 = channel disabled +// ; 1 = channel enabled +// +// options BYTE ? ; Bit-mapped options: +// +// numDimmSlots BYTE ? ; Number of Dimm slots per channel +// ; Valid options are 1, 2 or 3 +// ; MAX_DIMM is defined in mrcplatform.h. This option can be no larger than MAX_DIMM. +// ; It overrides MAX_DIMM when it is smaller. +// +// ddrChannelSetup ENDS +// +// ----------------------------------------------------------------------------- +// + +// +// ----------------------------------------------------------------------------- +// +// Node bit-mapped options +// +// ddrSocketSetup STRUCT 4t ; Socket setup structure declaration +// +// enabled BYTE ? ; imc enable switch: +// ; 0 = imc disabled +// ; 1 = imc enabled +// +// options BYTE ? ; Bit-mapped options per socket: +// +// vrefDefaultValue BYTE ? ; Default DCP value per socket for DIMM Vref = Vddq/2 +// +// vrefDcp smbDevice <> ; Defines override of DCP SMBus device and address +// ; compId = DCP_ISL9072X or DCP_AD5247 +// ; strapAddress +// ; busSegment +// +// ddrSocketSetup ENDS +// +// ----------------------------------------------------------------------------- +// + +/// +/// PPR DRAM Address +/// +typedef struct { + UINT8 dimm; + UINT8 rank; + UINT8 subRank; + UINT32 dramMask; + UINT8 bank; + UINT32 row; +} PPR_ADDR; + +// HIGH_ADDR_EN enables extention of the MMIO hole to force memory to high address region +#define HIGH_ADDR_EN BIT0 +#define CR_MIXED_SKU BIT2 //used to enable(1)- halt on mixed sku discovery and disable(0) - warn on mixed sku discovery + +//#pragma pack(pop) + +/// +/// Sub-boot state internal to MRC (8-15 are definable). The 2 main boot types and paths through QPIRC/MRC - NormalBoot and S3Resume. +/// Within NormalBoot and S3Resume, the sub-boot type can be cold, warm, fast warm, fast cold, and ADR resume. These are populated +/// at the beginning of MRC so they are not applicable for QPIRC. +/// +typedef enum SubBootMode +{ + ColdBoot = 8, // Normal path through MRC with full mem detection, init, training, etc. + WarmBoot = 9, // Warm boot path through MRC. Some functionality can be skipped for speed. + WarmBootFast = 10, // Fast warm boot path uses the NVRAM structure to skip as much MRC + // code as possible to try to get through MRC fast. Should be as close + // as possible to the S3 flow. + ColdBootFast = 11, // Fast cold boot path uses the NVRAM structure to skip as much MRC + // code as possible on a cold boot. + AdrResume = 12, // ADR flow can skip most of MRC (i.e. take the S3 path) for DIMMs that + // are in self-refresh. But the DIMMs that are not in self-refresh + // must go through more of MRC. + Reserved13 = 13 +} SubBootMode; + +#define MAX_ADV_MT_LOG 16 + +#define MEM_CHIP_POLICY_DEF(x) host->var.mem.memChipPolicy.x +#define MEM_CHIP_POLICY_VALUE(host, x) host->var.mem.memChipPolicy.x +#define CHIP_FUNC_CALL(host, x) x + +#pragma pack(pop) + +#endif // _memhost_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h new file mode 100644 index 0000000000..8a0de60293 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemHostChipCommon.h @@ -0,0 +1,128 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _memhostchipcommon_h +#define _memhostchipcommon_h + +#include "SysHostChipCommon.h" + +#define NODE_TO_SKT(node) (node / MAX_IMC) +#define SKT_TO_NODE(socket, mc) ((socket << 1) | (mc & BIT0)) +#define NODE_TO_MC(node) (node % MAX_IMC) +#define SKTMC_TO_NODE(socket, mc) ((socket * MAX_IMC) | (mc % MAX_IMC)) +#define NODECH_TO_SKTCH(node, ch) (((node % MAX_IMC)*MAX_MC_CH) + ch) + +// + +// +//MAX_CHANNELS and DYNVAR_MAX were previously defined in MmrcProjectDefinitionsGenerated.h, but +// now are here and must be manually updated as needed depending on MMRC tool execution (they have been +// removed from automatic generation by the tool) +// +// Channels +// +#define MAX_CHANNELS 6 + +#define DYNVAR_MAX 51 + +#define MAX_IMC 2 + +#define MAX_MC_CH 3 // Max channels per MC +#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) // Max number of memory nodes +#define MAX_DIMM 2 // Max DIMM per channel + +#define MAX_DIMM3 3 // Max DIMM per channel +#define MAX_TECH 19 // Number of entries in DRAM technology table + +#define MAX_RIR 4 // Number of Rank Interleave Register rules for DDR +#define MAX_RIR_DDRT 4 // Number of Rank Interleave Register rules for NVMDIMM +#define MAX_RIR_WAYS 8 // Number of interleave ways for RIR for DDR +#define TAD_RULES 8 // Number of TAD rule registers +#define MAX_TAD_WAYS 3 // Number of interleave ways for TAD RULES +#define SAD_RULES 24 // Number of SAD rule registers +#define MAX_SAD_RULES 24 // Number of SAD rule registers +#define MAX_STROBE 18 // Number of strobe groups +#define MAX_SEEDS 10 // Maximum +#if QR_DIMM_SUPPORT +#define MAX_RANK_DIMM 4 // Max ranks per DIMM +#else +#define MAX_RANK_DIMM 2 // Max ranks per DIMM +#endif +#define MAX_RANK_CH 8 // Max ranks per channel +#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel +#define SPD_MODULE_PART 18 // Number of bytes of module part - DDR3 +#define SPD_MODULE_PART_DDR4 20 // Number of bytes of module part - DDR4 +#define SAD_RULES_ADDR_RANGE 4 // Max IOT rules = 4, Total address limits (lower(4) entries each) +// Ctl FUBs +#define NUM_CTL_PLATFORM_GROUPS 4 + +// SPD Defines +//----------------------------------------------------------------------------- + +#pragma pack(1) + +// +// Define the WDB line. The WDB line is like the cache line. +// +#define MRC_WDB_LINES 32 +#define MRC_WDB_LINE_SIZE 64 +#define CADB_LINES 16 +// Define in the Critical Section function on what to wait. +// +typedef enum { + DoneAndRefDrained, + Done, + Immediate +} EWaitOn; + +typedef enum { + ssOne = 0, + ssTwo, + ssThree, + ssFour, +} TSubSequencesNumber; + +#define MAX_PHASE_IN_FINE_ADJUSTMENT 64 +#pragma pack() + +#define SKX_PCKG_TYPE 4 //CMD_CTL_DELAY_H + +#define CHIP_IOGPDLY_PSECS SKX_PCKG_TYPE + +// +// Chip specific section of the struct CPU_CSR_ACCESS_VAR +// +#define CPU_CSR_ACCESS_VAR_CHIP \ + + +typedef enum { + TYPE_SCF_BAR = 0, + TYPE_PCU_BAR, + TYPE_MEM_BAR0, + TYPE_MEM_BAR1, + TYPE_MEM_BAR2, + TYPE_MEM_BAR3, + TYPE_MEM_BAR4, + TYPE_MEM_BAR5, + TYPE_MEM_BAR6, + TYPE_MEM_BAR7, + TYPE_SBREG_BAR, + TYPE_MAX_MMIO_BAR +} MMIO_BARS; + + +// Output structures based on scope +#define MAX_BITS 72 + +#endif // _memhostchipcommon_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h new file mode 100644 index 0000000000..5e68cab7c5 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MemRegs.h @@ -0,0 +1,19 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _memregs_h +#define _memregs_h + +#define SPD_LR_PERS_BYTES_TOTAL 15 // LR DIMM Total number of Personality Bytes + +#endif // _memregs_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h new file mode 100644 index 0000000000..3f444664b0 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/MrcCommonTypes.h @@ -0,0 +1,26 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MrcCommonTypes_h_ +#define _MrcCommonTypes_h_ + +#include "DataTypes.h" + +#define INT32_MIN (0x80000000) +#ifndef INT32_MAX //INT32_MAX->Already defined +#define INT32_MAX (0x7FFFFFFF) +#endif +#define INT16_MIN (0x8000) +#define INT16_MAX (0x7FFF) + +#endif // _MrcCommonTypes_h_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h new file mode 100644 index 0000000000..00882a17e6 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/PcieAddress.h @@ -0,0 +1,71 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __PCIE_MMCFG_H__ +#define __PCIE_MMCFG_H__ + +#include <UsraAccessApi.h> + + +////////////////////////////////////////////////////////////////////////// +// +// PCIE MMCFG Table definition +// This table was based on PCI Firmwar Spec Rev 3.1 +// +////////////////////////////////////////////////////////////////////////// + +typedef struct + { + UINT8 Signature[4]; ///< “MCFG”. Signature For this Table + UINT32 Length; ///< Length, in bytes, include base address allocation structures. + UINT8 Revision; ///< "1" + UINT8 SegMax; ///< The Maximum number of Segments + UINT16 ValidSegMap; ///< Valid Segment Bit Map, LSB Bit0 for Seg0, bit1 for seg1 ... + UINT8 Reserved[4]; ///< Reserved +} PCIE_MMCFG_HEADER_TYPE; + +typedef struct + { + UINT32 BaseAddressL; ///< Processor-relative Base Address (Lower 32-bit) for the Enhanced Configuration Access Mechanism + UINT32 BaseAddressH; ///< Processor-relative Base Address (Upper 32-bit) for the Enhanced Configuration Access Mechanism + UINT16 Segment; ///< PCI Segment Group Number. Default is 0. + UINT8 StartBus; ///< Start PCI Bus number decoded by the host bridge + UINT8 EndBus; ///< End PCI Bus number decoded by the host bridge + UINT8 Reserved[4]; ///< Reserved +} PCIE_MMCFG_BASE_ADDRESS_TYPE; + + +typedef struct + { + PCIE_MMCFG_HEADER_TYPE Header; ///< The header of MMCFG Table + PCIE_MMCFG_BASE_ADDRESS_TYPE MmcfgBase[1]; ///< First Arrary of base address allocation structures. +} PCIE_MMCFG_TABLE_TYPE; + + +/** + This Lib is used for platfor to set platform specific Pcie MMCFG Table + + @param MmcfgTable: A pointer of the MMCFG Table structure for PCIE_MMCFG_TABLE_TYPE type. + @param NumOfSeg: Sumber of Segments in the table. + + @retval <>NULL The function completed successfully. + @retval NULL Returen Error +**/ +UINTN +EFIAPI +SetPcieSegMmcfgTable ( + IN PCIE_MMCFG_TABLE_TYPE *MmcfgTable, + IN UINT32 NumOfSeg +); + +#endif diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h new file mode 100644 index 0000000000..082c6effd5 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/Printf.h @@ -0,0 +1,80 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _printf_h +#define _printf_h + +#include "DataTypes.h" + +#define PRINTF_CONTROL_OUTOF_SYNC_ERR_MAJOR 0xCF +#define PRINTF_CONTROL_OUTOF_SYNC_ERR_MINOR 0x01 + +#define TAB_STOP 4 +#define LEFT_JUSTIFY 0x01 +#define PREFIX_SIGN 0x02 +#define PREFIX_BLANK 0x04 +#define COMMON_PREFIX_ZERO 0x08 +#define LONG_TYPE 0x10 + +#define INT_SIGNED 0x20 +#define COMA_TYPE 0x40 +#define LONG_LONG_TYPE 0x80 +#define TO_UPPER 0x100 + +#define CHAR_CR 0x0d +#define CHAR_LF 0x0a + +// +// ANSI Escape sequences for color +// +#define ANSI_FOREGROUND_BLACK 30 +#define ANSI_FOREGROUND_RED 31 +#define ANSI_FOREGROUND_GREEN 32 +#define ANSI_FOREGROUND_YELLOW 33 +#define ANSI_FOREGROUND_BLUE 34 +#define ANSI_FOREGROUND_MAGENTA 35 +#define ANSI_FOREGROUND_CYAN 36 +#define ANSI_FOREGROUND_WHITE 37 + +#define ANSI_BACKGROUND_BLACK 40 +#define ANSI_BACKGROUND_RED 41 +#define ANSI_BACKGROUND_GREEN 42 +#define ANSI_BACKGROUND_YELLOW 43 +#define ANSI_BACKGROUND_BLUE 44 +#define ANSI_BACKGROUND_MAGENTA 45 +#define ANSI_BACKGROUND_CYAN 46 +#define ANSI_BACKGROUND_WHITE 47 + +#define ANSI_ATTRIBUTE_OFF 0 +#define ANSI_ATTRIBUTE_BOLD 1 +#define ANSI_ATTRIBUTE_UNDERSCORE 4 +#define ANSI_ATTRIBUTE_BLINK 5 +#define ANSI_ATTRIBUTE_REVERSE 7 +#define ANSI_ATTRIBUTE_CONCEAL 8 + +#ifndef INT32_MAX +#define INT32_MAX 0x7fffffffU +#endif + +#ifndef va_start +typedef INT8 * va_list; +#define _INTSIZEOF(n) ((sizeof (n) + sizeof (UINT32) - 1) &~(sizeof (UINT32) - 1)) +#define va_start(ap, v) (ap = (va_list) & v + _INTSIZEOF (v)) +#define va_arg(ap, t) (*(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t))) +#define va_end(ap) (ap = (va_list) 0) +#endif + +#define ISDIGIT(_c) (((_c) >= '0') && ((_c) <= '9')) +#define ISHEXDIGIT(_c) (((_c) >= 'a') && ((_c) <= 'f')) + +#endif // _printf_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h new file mode 100644 index 0000000000..c3b6693a0b --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHost.h @@ -0,0 +1,142 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _syshost_h +#define _syshost_h +//#define CCMRC 1 + + +#define RC_SIM_FASTCADB 0 + + + +// +// Host reset states (0-7 are definable) +// +typedef enum BootMode { + NormalBoot = 0, // Normal path through RC with full init, mem detection, init, training, etc. + // Some of these MRC specific init routines can be skipped based on MRC input params + // in addition to the sub-boot type (WarmBoot, WarmBootFast, etc). + S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3 + // init and be optimized for speed. +} BootMode; + + +typedef struct sysHost SYSHOST, *PSYSHOST; + +#include "DataTypes.h" +#include "SysHostChipCommon.h" +#include "Printf.h" +#include "PlatformHost.h" +#include "CpuHost.h" +#include "MemHost.h" +#include "KtiHost.h" +#include "UsbDebugPort.h" + +#include "SysRegs.h" +#include "IioPlatformData.h" + +// +// ------------------------------------- +// Declarations and directives +// ------------------------------------- +// Reference Code (RC) revision in BCD format: +// [31:24] = Major revision number +// [23:16] = Minor revision number +// [15:8] = Release Candidate number +// +#define CCMRC_REVISION 0x00500000 + +#define SUCCESS 0 + +#define SDBG_MIN BIT0 +#define SDBG_MAX BIT1 +#define SDBG_TRACE BIT2 +#define SDBG_MEM_TRAIN BIT3 + SDBG_MAX +#define SDBG_TST BIT4 +#define SDBG_CPGC BIT5 +#define SDBG_RCWRITETAG BIT6 +#define SDBG_REG_ACCESS BIT6 // Displays all register accesses. +#define SDBG_MINMAX SDBG_MIN + SDBG_MAX + +#define SDBG_BUF_ENABLE 1 +#define SDBG_BUF_DISABLE 0 +#define SDBG_BUF_EN_DEFAULT SDBG_BUF_DISABLE // Default disable + +#define SDBG_PIPE_ENABLE 1 +#define SDBG_PIPE_DISABLE 0 +#define SDBG_PIPE_DEFAULT SDBG_PIPE_DISABLE + +#define SDBG_PIPE_COMPRESS_ENABLE 1 +#define SDBG_PIPE_COMPRESS_DISABLE 0 +#define SDBG_PIPE_COMPRESS_DEFAULT SDBG_PIPE_COMPRESS_DISABLE + + +// +// ----------------------------------------------------------------------------- +// Variable structures +// + +// +// Warning log +// +#define MAX_LOG 64 + +#define USB_BUF_LIMIT (4096-160) +#define USB_BUF_SIZE (USB_BUF_LIMIT + 160) + +// +// System previous boot error structure +// +#define MC_BANK_STATUS_REG 1 +#define MC_BANK_ADDRESS_REG 2 +#define MC_BANK_MISC_REG 3 + +#define MSR_LOG_VALID BIT31 +#define MSR_LOG_UC BIT29 +#define MSR_LOG_EN BIT28 + +// Bit definitions for commonSetup.options +// ; PROMOTE_WARN_EN enables warnings to be treated as fatal error +// ; PROMOTE_MRC_WARN_EN enables MRC warnings to be treated as fatal error +// ; HALT_ON_ERROR_EN enables errors to loop forever +#define PROMOTE_WARN_EN BIT0 +#define PROMOTE_MRC_WARN_EN BIT1 +#define HALT_ON_ERROR_EN BIT2 + + +// ----------------------------------------------------------------------------- +// + +// +// Handle assertions with RC_ASSERT +// +#if defined(SIM_BUILD) || defined(IA32) || defined (HEADLESS_MRC) + +#define RC_ASSERT(assertion, majorCode, minorCode) \ + if (!(assertion)) { \ + DebugPrintRc (host, 0xFF, "\n\nRC_ASSERT! %s: %u %s ", __FILE__, __LINE__, #assertion);\ + FatalError (host, majorCode, minorCode);\ + } + +#else + +#define RC_ASSERT(assertion, majorCode, minorCode) \ + if (!(assertion)) { \ + CpuCsrAccessError (host, "\n\nRC_ASSERT! %s: %u %s ", __FILE__, __LINE__, #assertion);\ + } + +#endif + + +#endif // _syshost_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h new file mode 100644 index 0000000000..2b0685674f --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysHostChipCommon.h @@ -0,0 +1,92 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _SYSHOST_CHIP_COMMON_H_ +#define _SYSHOST_CHIP_COMMON_H_ + +#ifndef SEGMENT_ACCESS +#define SEGMENT_ACCESS +#endif + +// +// Steppings +// +#define A0_REV 0x00 + +//TODO:Need to remove the old ones. Keep for noe to allow building +#define CPU_HSX 0 +#define CPU_IVT 1 +#define CPU_BDX 2 +#define CPU_SKX 0 + +// Defines for socketType +// +#define SOCKET_2S 0 +#define SOCKET_4S 1 +#define SOCKET_HEDT 2 + +// +// CpuPciAccess +// +#define READ_ACCESS 0 +#define WRITE_ACCESS 1 + +#pragma pack(1) + +typedef union { + struct { + UINT32 Bit0:1; + UINT32 Bit1:1; + UINT32 Bit2:1; + UINT32 Bit3:1; + UINT32 Bit4:1; + UINT32 Bit5:1; + UINT32 Bit6:1; + UINT32 Bit7:1; + UINT32 Bit8:1; + UINT32 Bit9:1; + UINT32 Bit10:1; + UINT32 Bit11:1; + UINT32 Bit12:1; + UINT32 Bit13:1; + UINT32 Bit14:1; + UINT32 Bit15:1; + UINT32 Bit16:1; + UINT32 Bit17:1; + UINT32 Bit18:1; + UINT32 Bit19:1; + UINT32 Bit20:1; + UINT32 Bit21:1; + UINT32 Bit22:1; + UINT32 Bit23:1; + UINT32 Bit24:1; + UINT32 Bit25:1; + UINT32 Bit26:1; + UINT32 Bit27:1; + UINT32 Bit28:1; + UINT32 Bit29:1; + UINT32 Bit30:1; + UINT32 Bit31:1; + } Bits; + UINT32 Data; +} DUMMY_REG; + +#pragma pack() + +// +// System previous boot error structure +// +#define MAX_PREV_BOOT_ERR_ENTRIES 15 + + +#endif // _SYSHOST_CHIP_COMMON_H_ diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h new file mode 100644 index 0000000000..565d13db60 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/SysRegs.h @@ -0,0 +1,74 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _sysregs_h +#define _sysregs_h + +#include "DataTypes.h" + +#ifndef BIT0 +#define BIT0 1 +#define BIT1 (1 << 1) +#define BIT2 (1 << 2) +#define BIT3 (1 << 3) +#define BIT4 (1 << 4) +#define BIT5 (1 << 5) +#define BIT6 (1 << 6) +#define BIT7 (1 << 7) +#define BIT8 (1 << 8) +#define BIT9 (1 << 9) +#endif +#ifndef BIT10 +#define BIT10 (1 << 10) +#define BIT11 (1 << 11) +#define BIT12 (1 << 12) +#define BIT13 (1 << 13) +#define BIT14 (1 << 14) +#define BIT15 (1 << 15) +#define BIT16 (1 << 16) +#define BIT17 (1 << 17) +#define BIT18 (1 << 18) +#define BIT19 (1 << 19) +#define BIT20 (1 << 20) +#define BIT21 (1 << 21) +#define BIT22 (1 << 22) +#define BIT23 (1 << 23) +#define BIT24 (1 << 24) +#define BIT25 (1 << 25) +#define BIT26 (1 << 26) +#define BIT27 (1 << 27) +#define BIT28 (1 << 28) +#define BIT29 (1 << 29) +#define BIT30 (1 << 30) +#define BIT31 (UINT32) (1 << 31) +#endif + +#ifndef TRUE +#define TRUE ((BOOLEAN) 1 == 1) +#endif + +#ifndef FALSE +#define FALSE ((BOOLEAN) 0 == 1) +#endif + +#ifndef ABS +#define ABS(x) (((x) < 0) ? (-x) : (x)) +#endif +// +// disable compiler warning to use bit fields on unsigned short/long types +// +#ifdef _MSC_VER +#pragma warning(disable : 4214) +#endif + +#endif // _sysregs_h diff --git a/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h new file mode 100644 index 0000000000..e6d9d37ba9 --- /dev/null +++ b/Silicon/Intel/PurleyRcPkg/Library/BaseMemoryCoreLib/Core/Include/UsbDebugPort.h @@ -0,0 +1,324 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _USB_DEBUG_PORT_INTERNAL_H +#define _USB_DEBUG_PORT_INTERNAL_H + +#include "DataTypes.h" + +#define PCI_VENDOR_ID_OFFSET 0x00 +#define PCI_DEVICE_ID_OFFSET 0x02 +#define PCI_COMMAND_OFFSET 0x04 +#define PCI_PRIMARY_STATUS_OFFSET 0x06 +#define PCI_REVISION_ID_OFFSET 0x08 +#define PCI_CLASSCODE_OFFSET 0x09 +#define PCI_SUBCLASSCODE_OFFSET 0x0A +#define PCI_BASECLASSCODE_OFFSET 0x0B // Base Class Code Register +#define PCI_CACHELINE_SIZE_OFFSET 0x0C +#define PCI_LATENCY_TIMER_OFFSET 0x0D +#define PCI_HEADER_TYPE_OFFSET 0x0E +#define PCI_BIST_OFFSET 0x0F +#define PCI_BASE_ADDRESSREG_OFFSET 0x10 +#define PCI_CARDBUS_CIS_OFFSET 0x28 +#define PCI_SVID_OFFSET 0x2C // SubSystem Vendor id +#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C +#define PCI_SID_OFFSET 0x2E // SubSystem ID +#define PCI_SUBSYSTEM_ID_OFFSET 0x2E +#define PCI_EXPANSION_ROM_BASE 0x30 +#define PCI_CAPBILITY_POINTER_OFFSET 0x34 +#define PCI_INT_LINE_OFFSET 0x3C // Interrupt Line Register +#define PCI_INT_PIN_OFFSET 0x3D // Interrupt Pin Register +#define PCI_MAXGNT_OFFSET 0x3E // Max Grant Register +#define PCI_MAXLAT_OFFSET 0x3F // Max Latency Register + +#define PCI_CLASS_SERIAL 0x0C +#define PCI_CLASS_SERIAL_USB 0x03 + +#define IS_BIT_SET(Register, BitMask) (((*(volatile UINT32 *)(Register)) & (BitMask)) != 0) +#define IS_BIT_CLEAR(Register, BitMask) (((*(volatile UINT32 *)(Register)) & (BitMask)) == 0) + +#define SET_R32_BIT(Register, BitMask) \ + { \ + UINT32 RegisterValue = *(volatile UINT32 *)(Register); \ + RegisterValue |= (UINT32)(BitMask); \ + *(volatile UINT32 *)(Register) = RegisterValue; \ + } + +#define CLR_R32_BIT(Register, BitMask) \ + { \ + UINT32 RegisterValue = *(volatile UINT32 *)(Register); \ + RegisterValue &= (UINT32)(~(BitMask)); \ + *(volatile UINT32 *)(Register) = RegisterValue; \ + } + +#define CLR_AND_SET_R32_BIT(Register, BitMask, Value) \ + { \ + UINT32 RegisterValue = *(volatile UINT32 *)(Register); \ + RegisterValue &= (UINT32)(~(BitMask)); \ + RegisterValue |= (UINT32)(Value); \ + *(volatile UINT32 *)(Register) = RegisterValue; \ + } + +#define SET_R16_BIT(Register, BitMask) \ + { \ + UINT16 RegisterValue = *(volatile UINT16 *)(Register); \ + RegisterValue |= (UINT16)(BitMask); \ + *(volatile UINT16 *)(Register) = RegisterValue; \ + } + +#define CLR_R16_BIT(Register, BitMask) \ + { \ + UINT16 RegisterValue = *(volatile UINT16 *)(Register); \ + RegisterValue &= (UINT16)(~(BitMask)); \ + *(volatile UINT16 *)(Register) = RegisterValue; \ + } + +#define SET_R8_BIT(Register, BitMask) \ + { \ + UINT8 RegisterValue = *(volatile UINT8 *)(Register); \ + RegisterValue |= (UINT8)(BitMask); \ + *(volatile UINT8 *)(Register) = RegisterValue; \ + } + +#define CLR_R8_BIT(Register, BitMask) \ + { \ + UINT8 RegisterValue = *(volatile UINT8 *)(Register); \ + RegisterValue &= (UINT8)(~(BitMask)); \ + *(volatile UINT8 *)(Register) = RegisterValue; \ + } + +#define PCI_CLASS_SERIAL_USB_EHCI 0x20 +#define PCI_CAPABILITY_ID_DEBUG_PORT 0x0A + +#define PCI_USB2_SBRN_OFFSET 0x60 +#define PCI_PRIMARY_BUS_NUMBER_OFFSET 0x18 +#define PCI_SECONDARY_BUS_NUMBER_OFFSET 0x19 +#define PCI_SUBORDINATE_BUS_NUMBER_OFFSET 0x1A + +#define PCI_BRIDGE_MBASE_OFFSET 0x20 +#define PCI_BRIDGE_MLIMIT_OFFSET 0x22 + +#define PCI_EHCI_DEFAULT_BUS_NUMBER 0x00 +#define PCI_EHCI_DEFAULT_DEVICE_NUMBER 0x1D +#define PCI_EHCI_DEFAULT_FUNCTION_NUMBER 0x00 +#define PCI_EHCI_DEFAULT_DEBUG_CAPID_OFFSET 0x58 +#define PCI_EHCI_DEFAULT_DEBUG_BASE_OFFSET 0x5A + +// +// USB PIDs +// +#define USB2_PID_TOKEN_OUT 0xE1 +#define USB2_PID_TOKEN_IN 0x69 +#define USB2_PID_TOKEN_SOF 0xA5 +#define USB2_PID_TOKEN_SETUP 0x2D + +#define USB2_PID_DATA0 0xC3 +#define USB2_PID_DATA1 0x4B +#define USB2_PID_DATA2 0x87 +#define USB2_PID_MDATA 0x0F + +#define USB2_PID_HANDSHAKE_ACK 0xD2 +#define USB2_PID_HANDSHAKE_NAK 0x5A +#define USB2_PID_HANDSHAKE_STALL 0x1E +#define USB2_PID_HANDSHAKE_NYET 0x96 + +#define USB2_PID_SPECIAL_PRE 0x3C +#define USB2_PID_SPECIAL_ERR 0x3C +#define USB2_PID_SPECIAL_SPLIT 0x78 +#define USB2_PID_SPECIAL_PING 0xB4 +#define USB2_PID_SPECIAL_RESERVED 0xF0 + +// +// USB2 Debug Port Register +// +#define USB2_DEBUG_PORT_STATUS_OWNER 0x40000000 +#define USB2_DEBUG_PORT_STATUS_ENABLED 0x10000000 +#define USB2_DEBUG_PORT_STATUS_DONE 0x00010000 +#define USB2_DEBUG_PORT_STATUS_INUSE 0x00000400 +#define USB2_DEBUG_PORT_STATUS_EXCEPTION 0x00000380 +#define USB2_DEBUG_PORT_STATUS_ERROR 0x00000040 +#define USB2_DEBUG_PORT_STATUS_GO 0x00000020 +#define USB2_DEBUG_PORT_STATUS_WRITE 0x00000010 +#define USB2_DEBUG_PORT_STATUS_LENGTH 0x0000000F + +#define USB2_DEBUG_PORT_DEFAULT_ADDRESS 127 + +#define USB2_DEBUG_PORT_DEVICE_BUFFER_MAX 8 + +typedef struct _USB2_DEBUG_PORT_REGISTER { + UINT32 ControlStatus; + UINT8 TokenPid; + UINT8 SendPid; + UINT8 ReceivedPid; + UINT8 Reserved1; + UINT8 DataBuffer[USB2_DEBUG_PORT_DEVICE_BUFFER_MAX]; + UINT8 UsbEndPoint; + UINT8 UsbAddress; + UINT8 Reserved2; + UINT8 Reserved3; +}USB2_DEBUG_PORT_REGISTER; + +typedef struct _USB2_EHCI_CAPABILITY_REGISTER { + UINT8 CapLength; + UINT8 Reserved; + UINT16 HciVersion; + UINT32 HcsParams; + UINT32 HccParams; + UINT32 HcspPortRoute; +}USB2_EHCI_CAPABILITY_REGISTER; + +#define USB2_EHCI_USBCMD_RUN 0x00000001 +#define USB2_EHCI_USBCMD_RESET 0x00000002 + +#define USB2_EHCI_USBSTS_HC_HALTED 0x00001000 + +#define USB2_EHCI_PORTSC_PORT_OWNER 0x00002000 +#define USB2_EHCI_PORTSC_PORT_POWER 0x00001000 +#define USB2_EHCI_PORTSC_PORT_RESET 0x00000100 +#define USB2_EHCI_PORTSC_PORT_SUSPEND 0x00000080 +#define USB2_EHCI_PORTSC_PORT_ENABLED 0x00000004 + +typedef struct _USB2_EHCI_OPERATIONAL_REGISTER { + UINT32 UsbCommand; + UINT32 UsbStatus; + UINT32 UsbInterruptEnable; + UINT32 UsbFrameIndex; + UINT32 SegmentSelector; + UINT32 FrameListBaseAddress; + UINT32 NextAsyncListAddress; + UINT32 Reserved[9]; + UINT32 ConfigFlag; + UINT32 PortSc[0x0F]; +}USB2_EHCI_OPERATIONAL_REGISTER; + +#define USB2_DEBUG_PORT_DRIVER_BUFFER_MAX USB2_DEBUG_PORT_DEVICE_BUFFER_MAX * 2 + +typedef struct _USB2_DEBUG_PORT_INSTANCE { + + UINT32 EhciCapRegister; + UINT32 EhciOpRegister; + UINT32 PortSc; + UINT32 DebugRegister; + + BOOLEAN Ready; + + UINT8 PciBusNumber; + UINT8 PciDeviceNumber; + UINT8 PciDeviceFunction; + + UINT8 Reserved1; + UINT8 BarIndex; + UINT16 BarOffset; + + UINT32 PortBase; + UINT8 PortNumber; + UINT8 PortAddress; + UINT8 ReadEndpoint; + UINT8 WriteEndpoint; + + UINT8 ReadEndpointDataToggle; + UINT8 WriteEndpointDataToggle; + UINT8 Reserved2[2]; + + INT32 TempDataLength; + INT32 TempDataIndex; + UINT8 TempData[USB2_DEBUG_PORT_DRIVER_BUFFER_MAX]; +}USB2_DEBUG_PORT_INSTANCE; + +// +// Setup Packet +// +// Data phase transfer direction +// +#define USB2_REQUEST_TYPE_HOST_TO_DEVICE 0x00 +#define USB2_REQUEST_TYPE_DEVICE_TO_HOST 0x80 + +// +// Type +// +#define USB2_REQUEST_TYPE_STANDARD 0x00 +#define USB2_REQUEST_TYPE_CLASS 0x20 +#define USB2_REQUEST_TYPE_VENDOR 0x40 + +// +// Recipient +// +#define USB2_REQUEST_TYPE_DEVICE 0x00 +#define USB2_REQUEST_TYPE_INTERFACE 0x01 +#define USB2_REQUEST_TYPE_ENDPOINT 0x02 +#define USB2_REQUEST_TYPE_OTHER 0x03 + +// +// Request +// +#define USB2_REQUEST_GET_STATUS 0x00 +#define USB2_REQUEST_CLEAR_FEATURE 0x01 +#define USB2_REQUEST_SET_FEATURE 0x03 +#define USB2_REQUEST_SET_ADDRESS 0x05 +#define USB2_REQUEST_GET_DESCRIPTOR 0x06 +#define USB2_REQUEST_SET_DESCRIPTOR 0x07 +#define USB2_REQUEST_GET_CONFIGURATION 0x08 +#define USB2_REQUEST_SET_CONFIGURATION 0x09 +#define USB2_REQUEST_GET_INTERFACE 0x0A +#define USB2_REQUEST_SET_INTERFACE 0x11 + +// +// Descriptor Types +// +#define USB2_DESCRIPTOR_TYPE_DEVICE 0x01 +#define USB2_DESCRIPTOR_TYPE_CONFIGURATION 0x02 +#define USB2_DESCRIPTOR_TYPE_STRING 0x03 +#define USB2_DESCRIPTOR_TYPE_INTERFACE 0x04 +#define USB2_DESCRIPTOR_TYPE_ENDPOINT 0x05 +#define USB2_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06 +#define USB2_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION 0x07 +#define USB2_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08 +#define USB2_DESCRIPTOR_TYPE_OTG 0x09 +#define USB2_DESCRIPTOR_TYPE_DEBUG 0x0A + +// +// Standard Feature Selectors +// +#define USB2_FEATURE_DEVICE_REMOTE_WAKEUP 0x01 +#define USB2_FEATURE_ENDPOINT_HALT 0x00 +#define USB2_FEATURE_TEST_MODE 0x02 +#define USB2_FEATURE_OTG_B_HNP_ENABLE 0x03 +#define USB2_FEATURE_OTG_A_HNP_SUPPORT 0x04 +#define USB2_FEATURE_OTG_A_ALT_HNP_SUPPORT 0x05 +#define USB2_FEATURE_DEBUG_MODE 0x06 + +typedef struct _USB2_SETUP_PACKET { + UINT8 RequestType; + UINT8 Request; + UINT8 Value[2]; + UINT16 Index; + UINT16 Length_; +}USB2_SETUP_PACKET; + +typedef struct _USB2_DEBUG_DESCRIPTOR_TYPE { + UINT8 Length_; + UINT8 DescriptorType; + UINT8 DebugInEndpoint; + UINT8 DebugOutEndpoint; +}USB2_DEBUG_DESCRIPTOR_TYPE; + +typedef struct _USB2_ENDPOINT_DESCRIPTOR_TYPE { + UINT8 Length_; + UINT8 DescriptorType; + UINT8 EndpointAddress; + UINT8 Attributes; + UINT16 MaxPacketSize; + UINT8 Interval; +}USB2_ENDPOINT_DESCRIPTOR_TYPE; + +#endif /* _USB_DEBUG_PORT_H */ |