diff options
Diffstat (limited to 'Silicon/Intel/PurleySktPkg/Include/Guid')
12 files changed, 1294 insertions, 0 deletions
diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryConfigData.h b/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryConfigData.h new file mode 100644 index 0000000000..5102ba7a8f --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryConfigData.h @@ -0,0 +1,25 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MEMORY_CONFIG_DATA_GUID_H_ +#define _MEMORY_CONFIG_DATA_GUID_H_ + +#define EFI_MEMORY_CONFIG_DATA_GUID \ + { \ + 0x80dbd530, 0xb74c, 0x4f11, {0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }\ + } + +extern EFI_GUID gEfiMemoryConfigDataGuid; +extern CHAR16 EfiMemoryConfigVariable[]; + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryMapData.h b/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryMapData.h new file mode 100644 index 0000000000..b5cc47bbf5 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/MemoryMapData.h @@ -0,0 +1,75 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _MEMORY_MAP_GUID_H_ +#define _MEMORY_MAP_GUID_H_ + +#include "SysHost.h" +#include "UncoreCommonIncludes.h" +#include "PartialMirrorGuid.h" + +// {F8870015-6994-4b98-95A2-BD56DA91C07F} +#define EFI_MEMORY_MAP_GUID \ + { \ + 0xf8870015,0x6994,0x4b98,0x95,0xa2,0xbd,0x56,0xda,0x91,0xc0,0x7f \ + } + +extern EFI_GUID gEfiMemoryMapGuid; +extern CHAR16 EfiMemoryMapVariable[]; + +// +// System Memory Map HOB information +// + +#pragma pack(1) + +struct SystemMemoryMapElement { + UINT8 NodeId; // Node ID of the HA Owning the memory + UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA + UINT8 ImcInterBitmap; // IMC interleave bitmap for this DRAM rule - ONLY IN NUMA + UINT32 BaseAddress; // Base Address of the element in 64MB chunks + UINT32 ElementSize; // Size of this memory element in 64MB chunks +}; + +struct SystemMemoryMapHob { + UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. + UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. + UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. + UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. + UINT32 memSize; // Total physical memory size + UINT16 memFreq; // Mem Frequency + UINT8 memMode; // 0 - Independent, 1 - Lockstep + UINT8 DimmType; + UINT16 DramType; + UINT8 DdrVoltage; + UINT8 AepDimmPresent; // If at least one Aep Dimm Present (used by Nfit), then this should get set + UINT8 SADNum; + UINT8 XMPProfilesSup; + UINT8 cpuType; + UINT8 cpuStepping; + UINT8 SystemRasType; + UINT8 RasModesEnabled; // RAS modes that are enabled + UINT8 ExRasModesEnabled; // Extended RAS modes that are enabled + UINT8 RasModesSupported; //RAS modes that are supported by current memory population. + UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration + UINT8 NumOfCluster; + UINT8 NumChPerMC; + UINT8 numberEntries; // Number of Memory Map Elements + UINT8 maxIMC; + UINT8 maxCh; + struct SystemMemoryMapElement Element[MAX_SOCKET * SAD_RULES]; +}; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/PartialMirrorGuid.h b/Silicon/Intel/PurleySktPkg/Include/Guid/PartialMirrorGuid.h new file mode 100644 index 0000000000..d8e770fba6 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/PartialMirrorGuid.h @@ -0,0 +1,65 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PARTIAL_MIRROR_GUID_H_ +#define _PARTIAL_MIRROR_GUID_H_ + +#define ADDRESS_BASED_MIRROR_VARIABLE_GUID { 0x7b9be2e0, 0xe28a, 0x4197, 0xad, 0x3e, 0x32, 0xf0, 0x62, 0xf9, 0x46, 0x2c } + +#define ADDRESS_RANGE_MIRROR_VARIABLE_CURRENT L"MirrorCurrent" +#define ADDRESS_RANGE_MIRROR_VARIABLE_REQUEST L"MirrorRequest" +#define ADDRESS_BASED_MIRROR_VARIABLE_SIZE sizeof(ADDRESS_RANGE_MIRROR_VARIABLE_DATA) +#define ADDRESS_BASED_MIRROR_VARIABLE_ATTRIBUTE (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS) +#define ADDRESS_RANGE_MIRROR_VARIABLE_VERSION 1 +#define MIRROR_STATUS_SUCCESS 0 +#define MIRROR_STATUS_MIRROR_INCAPABLE 1 +#define MIRROR_STATUS_VERSION_MISMATCH 2 +#define MIRROR_STATUS_INVALID_REQUEST 3 +#define MIRROR_STATUS_UNSUPPORTED_CONFIG 4 +#define MIRROR_STATUS_OEM_SPECIFIC_CONFIGURATION 5 + +extern EFI_GUID gAddressBasedMirrorGuid; + +#pragma pack(1) + +typedef struct { +// +// MirroredAmountAbove4GB is the amount of available memory above 4GB that needs to be mirrored +// measured in basis point (hundredths of percent e.g. 12% = 1275). +// In a multi-socket system, platform is required to distribute the mirrored memory ranges such that the +// amount mirrored is approximately proportional to the amount of memory on each NUMA node. E.g. on +// a two node machine with 64GB on node 0 and 32GB on node 1, a request for 12GB of mirrored memory +// should be allocated with 8GB of mirror on node 0 and 4GB on node 1. +// +// For example, if the total memory in the system is 48GB and 12GB of memory above the 4GB addresses needs to be mirrored then the amount would be: +// Total Memory = 48 GB +// Total Memory above 4GB = 44 GB +// Percentage = 8/44 * 100 = 18.18% = 1818 basis points +// Consider a 2S system with 32 GB of memory attached to socket 0 and 16GB on socket 1, +// then socket 0 should mirror 8 GB of memory and socket 1 mirror 4GB to maintain the requested 18%. +// This ensures that OS has an adequate amount of mirrored memory on each NUMA domain. +// + UINT8 MirrorVersion; + BOOLEAN MirrorMemoryBelow4GB; + UINT16 MirroredAmountAbove4GB; + UINT8 MirrorStatus; +} ADDRESS_RANGE_MIRROR_VARIABLE_DATA; + +typedef struct { + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorCurrentType; + ADDRESS_RANGE_MIRROR_VARIABLE_DATA MirrorRequestType; +} RASMEMORYINFO; +#pragma pack() + + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SmramMemoryReserve.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SmramMemoryReserve.h new file mode 100644 index 0000000000..26b708279f --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SmramMemoryReserve.h @@ -0,0 +1,49 @@ +/** @file
+
+Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+This program and the accompanying materials are licensed and made available under
+the terms and conditions of the BSD License that accompanies this distribution.
+The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php.
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_
+#define _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_
+
+#define EFI_SMM_PEI_SMRAM_MEMORY_RESERVE \
+ { \
+ 0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d } \
+ }
+
+/**
+* GUID specific data structure of HOB for reserving SMRAM regions.
+*
+* Inconsistent with specification here:
+* EFI_HOB_SMRAM_DESCRIPTOR_BLOCK has been changed to EFI_SMRAM_HOB_DESCRIPTOR_BLOCK.
+* This inconsistency is kept in code in order for backward compatibility.
+**/
+typedef struct {
+ ///
+ /// Designates the number of possible regions in the system
+ /// that can be usable for SMRAM.
+ ///
+ /// Inconsistent with specification here:
+ /// In Framework SMM CIS 0.91 specification, it defines the field type as UINTN.
+ /// However, HOBs are supposed to be CPU neutral, so UINT32 should be used instead.
+ ///
+ UINT32 NumberOfSmmReservedRegions;
+ ///
+ /// Used throughout this protocol to describe the candidate
+ /// regions for SMRAM that are supported by this platform.
+ ///
+ EFI_SMRAM_DESCRIPTOR Descriptor[1];
+} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK;
+
+extern EFI_GUID gEfiSmmPeiSmramMemoryReserveGuid;
+
+#endif
+
diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketCommonRcVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketCommonRcVariable.h new file mode 100644 index 0000000000..b2472e14bd --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketCommonRcVariable.h @@ -0,0 +1,45 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_COMMONRC_CONFIG_DATA_H__ +#define __SOCKET_COMMONRC_CONFIG_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketCommonRcVariableGuid; +#define SOCKET_COMMONRC_CONFIGURATION_NAME L"SocketCommonRcConfig" + +#pragma pack(1) +typedef struct { + // + // Common Section of RC + // + UINT32 MmiohBase; + UINT16 MmiohSize; + UINT8 MmcfgBase; + UINT8 MmcfgSize; + UINT8 IsocEn; + UINT8 NumaEn; + UINT8 MirrorMode; + UINT8 LockStep; + UINT8 CpuStepping; + UINT8 SystemRasType; + UINT32 FpgaPresentBitMap; +} SOCKET_COMMONRC_CONFIGURATION; +#pragma pack() + +#endif + + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketIioVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketIioVariable.h new file mode 100644 index 0000000000..2a47851f17 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketIioVariable.h @@ -0,0 +1,269 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_IIO_CONFIG_DATA_H__ +#define __SOCKET_IIO_CONFIG_DATA_H__ + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketIioVariableGuid; +#define SOCKET_IIO_CONFIGURATION_NAME L"SocketIioConfig" + +#pragma pack(1) + + +typedef struct { + +/** +================================================================================================== +================================== VTd Setup Options ================================== +================================================================================================== +**/ + UINT8 VTdSupport; + UINT8 InterruptRemap; + UINT8 CoherencySupport; + UINT8 ATS; + UINT8 PostedInterrupt; + UINT8 PassThroughDma; +/** +================================================================================================== +================================== PCIE Setup Options ================================== +================================================================================================== +**/ + UINT8 IioPresent[MAX_SOCKET]; + UINT8 VtdAcsWa; + + // Platform data needs to update these PCI Configuration settings + UINT8 SLOTHPCAP[MAX_TOTAL_PORTS]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6) + UINT8 SLOTHPSUP[MAX_TOTAL_PORTS]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5) + + // General PCIE Configuration + UINT8 ConfigIOU0[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P5p6p7p8) + UINT8 ConfigIOU1[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P9p10p11p12) + UINT8 ConfigIOU2[MAX_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4) + UINT8 ConfigMCP0[MAX_SOCKET]; // 04-x16 (p13) + UINT8 ConfigMCP1[MAX_SOCKET]; // 04-x16 (p14) + UINT8 CompletionTimeoutGlobal; // + UINT8 CompletionTimeoutGlobalValue; + UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CoherentReadPart; + UINT8 CoherentReadFull; + UINT8 PcieGlobalAspm; // + UINT8 StopAndScream; // + UINT8 SnoopResponseHoldOff; // + // + // PCIE capability + // + UINT8 PCIe_LTR; // + UINT8 PcieExtendedTagField; // + UINT8 PCIe_AtomicOpReq; // + UINT8 PcieMaxReadRequestSize; // + + + UINT8 RpCorrectableErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableNonFatalErrorEsc[MAX_SOCKET]; //on Setup + UINT8 RpUncorrectableFatalErrorEsc[MAX_SOCKET]; //on Setup + + // mixc PCIE configuration + UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieAspm[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieMaxPayload[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; // On Setup + UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; // On Setup + UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup + UINT8 ExtendedSync[MAX_TOTAL_PORTS]; // On Setup + UINT8 InbandPresenceDetect[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePortDisable[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 PciePmeIntEn[MAX_TOTAL_PORTS]; // Not implemented in code + UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for Link Control2 + // + UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; //on Setup + UINT8 ComplianceMode[MAX_TOTAL_PORTS]; // On Setup PRD + UINT8 PciePortLinkMaxWidth[MAX_TOTAL_PORTS]; // On Setup + UINT8 DeEmphasis[MAX_TOTAL_PORTS]; // On Setup + + // + // PCIE setup options for MISCCTRLSTS + // + UINT8 EOI[MAX_TOTAL_PORTS]; // On Setup + UINT8 MSIFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSINFATEN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 MSICOREN[MAX_TOTAL_PORTS]; //On Setup. + UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; //On Setup + UINT8 DISL0STx[MAX_TOTAL_PORTS]; //On Setup + UINT8 P2PWrtDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 Peer + UINT8 P2PRdDis[MAX_TOTAL_PORTS]; //On Setup Peer 2 peer + UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIHP[MAX_TOTAL_PORTS]; //On Setup + UINT8 ACPIPM[MAX_TOTAL_PORTS]; //On Setup + UINT8 SRIS[MAX_TOTAL_PORTS]; //On Setup + UINT8 TXEQ[MAX_TOTAL_PORTS]; //On Setup + UINT8 ECRC[MAX_TOTAL_PORTS]; //On Setup + // + // PCIE RAS (Errors) + // + + UINT8 PcieUnsupportedRequests[MAX_TOTAL_PORTS]; // Unsupported Request per-port option + + // + // PCIE Link Training Ctrl + // + +/** +================================================================================================== +================================== Crystal Beach 3 Setup Options =========================== +================================================================================================== +**/ + UINT8 Cb3DcaEn[MAX_SOCKET]; // on setup + UINT8 Cb3DmaEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 Cb3NoSnoopEn[TOTAL_CB3_DEVICES]; // on setup + UINT8 DisableTPH; + UINT8 PrioritizeTPH; + UINT8 CbRelaxedOrdering; + +/** +================================================================================================== +================================== MISC IOH Setup Options ========================== +================================================================================================== +**/ + + // The following are for hiding each individual device and function + UINT8 PEXPHIDE[MAX_TOTAL_PORTS]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD + UINT8 DevPresIoApicIio[TOTAL_IIO_STACKS]; + // Hide IOAPIC Device 5, Function 4 + UINT8 PCUF6Hide; // Hide Device PCU Device 30, Function 6 + UINT8 EN1K; // Enable/Disable 1K granularity of IO for P2P bridges 0:20:0:98 bit 2 + UINT8 DualCvIoFlow; // Dual CV IO Flow + UINT8 Pci64BitResourceAllocation; + UINT8 PcieBiosTrainEnable; // Used as a work around for A0 PCIe + UINT8 MultiCastEnable; // MultiCastEnable test enable + UINT8 McastBaseAddrRegion; // McastBaseAddrRegion + UINT8 McastIndexPosition; // McastIndexPosition + UINT8 McastNumGroup; // McastNumGroup + + + UINT8 HidePEXPMenu[MAX_TOTAL_PORTS]; // to suppress /display the PCIe port menu + +/** +================================================================================================== +================================== NTB Related Setup Options ========================== +================================================================================================== +**/ + UINT8 NtbPpd[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeOverride[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSplitBar[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizePBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar23[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar45[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar4[MAX_NTB_PORTS]; //on setup option + UINT8 NtbBarSizeSBar5[MAX_NTB_PORTS]; //on setup option + UINT8 NtbSBar01Prefetch[MAX_NTB_PORTS]; //on setup option + UINT8 NtbXlinkCtlOverride[MAX_NTB_PORTS]; //on setup option + +/** +================================================================================================== +================================== VMD Related Setup Options ========================== +================================================================================================== +**/ + UINT8 VMDEnabled[MAX_VMD_STACKS]; + UINT8 VMDPortEnable[MAX_VMD_PORTS]; + UINT8 VMDHotPlugEnable[MAX_VMD_STACKS]; + UINT8 VMDCfgBarSz[MAX_VMD_STACKS]; + UINT8 VMDCfgBarAttr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz1[MAX_VMD_STACKS]; + UINT8 VMDMemBar1Attr[MAX_VMD_STACKS]; + UINT8 VMDMemBarSz2[MAX_VMD_STACKS]; + UINT8 VMDMemBar2Attr[MAX_VMD_STACKS]; + + + /** + ================================================================================================== + ================================== PCIe SSD Related Setup Options ========================== + ================================================================================================== + **/ + + UINT8 PcieAICEnabled[MAX_VMD_STACKS]; + UINT8 PcieAICPortEnable[MAX_VMD_PORTS]; + UINT8 PcieAICHotPlugEnable[MAX_VMD_STACKS]; + + /** + ================================================================================================== + ================================== PCIe Global Related Setup Options ========================== + ================================================================================================== + **/ + UINT8 NoSnoopRdCfg; //on Setup + UINT8 NoSnoopWrCfg; //on Setup + UINT8 MaxReadCompCombSize; //on Setup + UINT8 ProblematicPort; //on Setup + UINT8 DmiAllocatingFlow; //on Setup + UINT8 PcieAllocatingFlow; //on Setup + UINT8 PcieHotPlugEnable; //on Setup + UINT8 PcieAcpiHotPlugEnable; //on Setup + UINT8 HaltOnDmiDegraded; //on Setup + UINT8 RxClockWA; + UINT8 GlobalPme2AckTOCtrl; //on Setup + UINT8 MctpEn; //On Setup + UINT8 PcieSlotOprom1; //On Setup + UINT8 PcieSlotOprom2; //On Setup + UINT8 PcieSlotOprom3; //On Setup + UINT8 PcieSlotOprom4; //On Setup + UINT8 PcieSlotOprom5; //On Setup + UINT8 PcieSlotOprom6; //On Setup + UINT8 PcieSlotOprom7; //On Setup + UINT8 PcieSlotOprom8; //On Setup + UINT8 PcieSlotItemCtrl; //On Setup + UINT8 PcieRelaxedOrdering; //On Setup + UINT8 PciePhyTestMode; //On setup +/** +================================================================================================== +================================== Iio Related Setup Options ========================== +================================================================================================== +**/ + + UINT8 RtoEnable; + UINT8 RtoLtssmLogger; // On Setup + UINT8 RtoLtssmLoggerStop; // On Setup + UINT8 RtoLtssmLoggerSpeed; // On Setup + UINT8 RtoLtssmLoggerMask; // On Setup + UINT8 RtoJitterLogger; // On Setup + UINT32 RtoSocketDevFuncHide[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup + UINT8 RtoGen3NTBTestCard[MAX_TOTAL_PORTS]; // On Setup + + UINT8 RtoGen3OverrideMode[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3TestCard[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh2_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Precursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Cursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoGen3ManualPh3_Postcursor[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoDnTxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoRxPreset[MAX_TOTAL_PORTS]; //On Setup + UINT8 RtoUpTxPreset[MAX_TOTAL_PORTS]; //On Setup + + UINT8 InboundConfiguration[MAX_TOTAL_PORTS]; //On Setup + +} SOCKET_IIO_CONFIGURATION; +#pragma pack() + +#endif diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMemoryVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMemoryVariable.h new file mode 100644 index 0000000000..ef0b5a300a --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMemoryVariable.h @@ -0,0 +1,221 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_MEMORY_CONFIG_DATA_H__ +#define __SOCKET_MEMORY_CONFIG_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" +#include <MemDefaults.h> + +extern EFI_GUID gEfiSocketMemoryVariableGuid; +#define SOCKET_MEMORY_CONFIGURATION_NAME L"SocketMemoryConfig" + +#pragma pack(1) +typedef struct { + UINT8 RtoMaxNodeInterleave; + UINT8 MemoryHotPlugBase; + UINT8 MemoryHotPlugLen; + UINT8 Srat; + UINT8 SratMemoryHotPlug; + UINT8 SratCpuHotPlug; + UINT8 PagePolicy; + UINT8 PatrolScrub; + UINT8 PatrolScrubDuration; + UINT8 PatrolScrubAddrMode; + UINT8 partialmirror; + UINT8 partialmirrorsad0; + UINT8 PartialMirrorUefi; + UINT16 PartialMirrorUefiPercent; + UINT16 partialmirrorsize[MAX_PARTIAL_MIRROR]; // Array of sizes of different partial mirrors + UINT8 DemandScrubMode; + UINT8 SddcPlusOneEn; + UINT16 spareErrTh; + UINT8 DieSparing; + UINT8 DieSparingAggressivenessLevel; + UINT8 ADDDCEn; + UINT8 AdddcErrInjEn; + UINT8 leakyBktLo; + UINT8 leakyBktHi; + UINT8 DutyCycleTraining; + UINT8 refreshMode; + UINT8 dllResetTestLoops; + UINT8 DdrMemoryType; + UINT8 HwMemTest; + UINT16 MemTestLoops; + UINT8 EccSupport; + UINT8 SocketInterleaveBelow4GB; + UINT8 RtoDimmManagement; + UINT8 RtoPartitionDDRTDimm; + UINT8 RtoPartitionRatio[16]; //[MAX_SOCKET * MAX_IMC] = [8] + UINT8 volMemMode; + UINT8 RtoPerMemMode; + UINT8 memInterleaveGran1LM; + UINT8 RtoMemInterleaveGranPMemUMA; + UINT8 RtoCfgMask2LM; + UINT8 ImcInterleaving; + UINT8 ChannelInterleaving; + UINT8 RankInterleaving; + UINT8 CkeProgramming; + UINT8 SrefProgramming; + UINT8 PkgcSrefEn; + UINT8 CkeIdleTimer; + UINT8 ApdEn; + UINT8 PpdEn; + UINT8 DdrtCkeEn; + UINT8 OppSrefEn; + UINT8 DdrtSrefEn; + UINT8 MdllOffEn; + UINT8 CkMode; + UINT8 MemTestOnFastBoot; + UINT8 AttemptFastBoot; + UINT8 AttemptFastBootCold; + UINT8 bdatEn; + UINT8 ScrambleEnDDRT; + UINT8 ScrambleEn; // for ddr4 + UINT8 allowCorrectableError; + UINT16 ScrambleSeedLow; + UINT16 ScrambleSeedHigh; + UINT8 CustomRefreshRateEn; + UINT8 CustomRefreshRate; + UINT8 mcBgfThreshold; + UINT8 readVrefCenter; + UINT8 wrVrefCenter; + UINT8 haltOnMemErr; + UINT8 thermalthrottlingsupport; + UINT8 thermalmemtrip; + UINT8 DimmTempStatValue; + UINT8 XMPProfilesSup; + UINT8 XMPMode; + UINT8 tCAS; + UINT8 tRP; + UINT8 tRCD; + UINT8 tRAS; + UINT8 tWR; + UINT16 tRFC; + UINT8 tRRD; + UINT8 tRTP; + UINT8 tWTR; + UINT8 tFAW; + UINT8 tCWL; + UINT8 tRC; + UINT8 commandTiming; + UINT16 tREFI; + UINT8 DdrFreqLimit; + UINT16 Vdd; + UINT8 lrdimmModuleDelay; + UINT32 rmtPatternLength; + UINT32 rmtPatternLengthExt; + UINT8 check_pm_sts; + UINT8 check_platform_detect; + UINT8 MemPwrSave; + UINT8 ElectricalThrottlingMode; + UINT8 MultiThreaded; + UINT8 promoteMrcWarnings; + UINT8 promoteWarnings; + UINT8 oppReadInWmm; + UINT16 normOppInterval; + UINT8 sck0ch0; + UINT8 sck0ch1; + UINT8 sck0ch2; + UINT8 sck0ch3; + UINT8 sck0ch4; + UINT8 sck0ch5; + UINT8 sck1ch0; + UINT8 sck1ch1; + UINT8 sck1ch2; + UINT8 sck1ch3; + UINT8 sck1ch4; + UINT8 sck1ch5; + UINT8 sck2ch0; + UINT8 sck2ch1; + UINT8 sck2ch2; + UINT8 sck2ch3; + UINT8 sck2ch4; + UINT8 sck2ch5; + UINT8 sck3ch0; + UINT8 sck3ch1; + UINT8 sck3ch2; + UINT8 sck3ch3; + UINT8 sck3ch4; + UINT8 sck3ch5; + UINT8 mdllSden; + UINT8 memhotSupport; + UINT8 MemhotOutputOnlyOpt; + UINT8 ADREn; + UINT8 RankMargin; + UINT8 EnableBacksideRMT; + UINT8 EnableBacksideCMDRMT; + UINT8 Reserved_0; + UINT8 rankMaskEn; + UINT8 RankSparing; + UINT8 multiSparingRanks; + UINT8 caParity; + UINT8 dimmIsolation; + UINT8 smbSpeed; + UINT8 EnforcePOR; + UINT8 pda; + UINT8 turnaroundOpt; + UINT8 oneRankTimingMode; + UINT8 eyeDiagram; + + UINT8 DramRaplInit; + UINT8 BwLimitTfOvrd; + UINT8 perbitmargin; + UINT8 DramRaplExtendedRange; + UINT8 CmsEnableDramPm; + UINT8 logParsing; + UINT8 WritePreamble; + UINT8 ReadPreamble; + UINT8 WrCRC; + + UINT8 Reserved_1; + UINT8 Reserved_2; + UINT8 Reserved_3; + UINT8 Reserved_4; + UINT8 Reserved_5; + UINT8 Reserved_6; + UINT8 Reserved_7; + UINT8 Reserved_8; + + UINT8 RmtOnColdFastBoot; + UINT8 mrcRepeatTest; + UINT8 RtoLowMemChannel; + UINT8 RtoHighAddressStartBitPosition; + UINT8 staggerref; + UINT32 memFlows; + UINT32 memFlowsExt; + UINT8 Blockgnt2cmd1cyc; + UINT8 Disddrtopprd; + UINT8 setTDPDIMMPower; + UINT8 setSecureEraseAllDIMMs; + UINT8 setSecureEraseSktCh[48]; + // + // PPR related + // + UINT8 pprType; + UINT8 pprErrInjTest; + // CR QoS Configuration Profiles + UINT8 crQosConfig; + UINT8 Reserved_11; + UINT8 Reserved_12; + UINT8 Reserved_13; + UINT8 imcBclk; + UINT8 spdCrcCheck; +} SOCKET_MEMORY_CONFIGURATION; + +#pragma pack() + +#endif + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMpLinkVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMpLinkVariable.h new file mode 100644 index 0000000000..3f51792d8b --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketMpLinkVariable.h @@ -0,0 +1,117 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_MP_LINK_CONFIG_DATA_H__ +#define __SOCKET_MP_LINK_CONFIG_DATA_H__ + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketMpLinkVariableGuid; +#define SOCKET_MP_LINK_CONFIGURATION_NAME L"SocketMpLinkConfig" + +#pragma pack(1) +typedef struct { + // SKXTODO: rename to Kti when removing HSX code + UINT8 QpiSetupNvVariableStartTag; // This must be the very first one of the whole KTI Setup NV variable! + + // + // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options + // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook + // which updates the KTI resource map + // + // + // KTI host structure inputs + // + UINT8 BusRatio[MAX_SOCKET]; + UINT8 LegacyVgaSoc; // Socket that claims the legacy VGA range; valid values are 0-3; 0 is default. + UINT8 LegacyVgaStack; // Stack that claims the legacy VGA range; valid values are 0-3; 0 is default. + UINT8 MmioP2pDis; // 1 - Disable; 0 - Enable + UINT8 DebugPrintLevel; // Bit 0 - Fatal, Bit1 - Warning, Bit2 - Info Summary; Bit 3 - Info detailed. 1 - Enable; 0 - Disable + UINT8 DegradePrecedence; // Use DEGRADE_PRECEDENCE definition; TOPOLOGY_PRECEDENCE is default + + // + // Phy/Link Layer Options + // + UINT8 QpiLinkSpeedMode; // Link speed mode selection; 0 - Slow Speed; 1- Full Speed + UINT8 QpiLinkSpeed; // One of SPEED_REC_96GT, SPEED_REC_104GT, MAX_KTI_LINK_SPEED (default), FREQ_PER_LINK + UINT8 KtiLinkL0pEn; // 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiLinkL1En; // 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiFailoverEn; // 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 KtiLbEn; // 0 - Disable(default), 1 - Enable + UINT8 KtiCrcMode; // 0 - 8 bit CRC 1 - 16 bit CRC Mode + UINT8 QpiCpuSktHotPlugEn; // 0 - Disable (default), 1 - Enable + UINT8 KtiCpuSktHotPlugTopology; // 0 - 4S Topology (default), 1 - 8S Topology + UINT8 KtiSkuMismatchCheck; // 0 - No, 1 - Yes (default) + UINT8 KtiLinkVnaOverride; // 0x100 - per link, 0xff - max (default), 0x00 - min + UINT8 SncEn; // 0 - Disable (default), 1 - Enable + UINT8 IoDcMode; // 0 - Disable IODC, 1 - AUTO (default), 2 - IODC_EN_REM_INVITOM_PUSH, 3 - IODC_EN_REM_INVITOM_ALLOCFLOW + // 4 - IODC_EN_REM_INVITOM_ALLOC_NONALLOC, 5 - IODC_EN_REM_INVITOM_AND_WCILF + UINT8 DirectoryModeEn; // 0 - Disable; 1 - Enable (default) + UINT8 XptPrefetchEn; // XPT Prefetch : 1 - Enable (Default); 0 - Disable + UINT8 KtiPrefetchEn; // KTI Prefetch : 1 - Enable (Default); 0 - Disable + UINT8 RdCurForXptPrefetchEn; // RdCur for XPT Prefetch : 0 - Disable, 1 - Enable, 2- Auto (default) + UINT8 IrqThreshold; // KTI IRQ Threshold setting + UINT8 TscSyncEn; // TSC Sync Enable: 0 - Disable; 1 - Enable; 2 - AUTO (default) + UINT8 StaleAtoSOptEn; // HA A to S directory optimization + UINT8 LLCDeadLineAlloc; // Never fill dead lines in LLC: 1 - Enable, 0 - Disable + +#define CSICPUPRTVARIABLE(x) x##KtiPortDisable;x##KtiLinkSpeed;x##KtiLinkVnaOverride; + + UINT8 KtiCpuPerPortStartTag; + CSICPUPRTVARIABLE(UINT8 Cpu0P0) + CSICPUPRTVARIABLE(UINT8 Cpu0P1) + CSICPUPRTVARIABLE(UINT8 Cpu0P2) +#if MAX_SOCKET > 1 + CSICPUPRTVARIABLE(UINT8 Cpu1P0) + CSICPUPRTVARIABLE(UINT8 Cpu1P1) + CSICPUPRTVARIABLE(UINT8 Cpu1P2) +#endif +#if MAX_SOCKET > 2 + CSICPUPRTVARIABLE(UINT8 Cpu2P0) + CSICPUPRTVARIABLE(UINT8 Cpu2P1) + CSICPUPRTVARIABLE(UINT8 Cpu2P2) +#endif +#if MAX_SOCKET > 3 + CSICPUPRTVARIABLE(UINT8 Cpu3P0) + CSICPUPRTVARIABLE(UINT8 Cpu3P1) + CSICPUPRTVARIABLE(UINT8 Cpu3P2) +#endif +#if (MAX_SOCKET > 4) + CSICPUPRTVARIABLE(UINT8 Cpu4P0) + CSICPUPRTVARIABLE(UINT8 Cpu4P1) + CSICPUPRTVARIABLE(UINT8 Cpu4P2) +#endif +#if (MAX_SOCKET > 5) + CSICPUPRTVARIABLE(UINT8 Cpu5P0) + CSICPUPRTVARIABLE(UINT8 Cpu5P1) + CSICPUPRTVARIABLE(UINT8 Cpu5P2) +#endif +#if (MAX_SOCKET > 6) + CSICPUPRTVARIABLE(UINT8 Cpu6P0) + CSICPUPRTVARIABLE(UINT8 Cpu6P1) + CSICPUPRTVARIABLE(UINT8 Cpu6P2) +#endif +#if (MAX_SOCKET > 7) + CSICPUPRTVARIABLE(UINT8 Cpu7P0) + CSICPUPRTVARIABLE(UINT8 Cpu7P1) + CSICPUPRTVARIABLE(UINT8 Cpu7P2) +#endif + + UINT8 QpiSetupNvVariableEndTag; // This must be the last one of the whole KTI Setup NV variable +} SOCKET_MP_LINK_CONFIGURATION; + +#pragma pack() + +#endif // __SOCKET_MP_LINK_CONFIG_DATA_H__ + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPciResourceData.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPciResourceData.h new file mode 100644 index 0000000000..7aa2ad7fc8 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPciResourceData.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ +#define __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketPciResourceDataGuid; +#define SOCKET_PCI_RESOURCE_CONFIGURATION_DATA_NAME L"SocketPciResourceConfigData" + +#pragma pack(1) +typedef struct { + // + // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options + // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook + // which updates the KTI resource map + // + UINT16 PciSocketIoBase[MAX_SOCKET]; + UINT16 PciSocketIoLimit[MAX_SOCKET]; + UINT32 PciSocketMmiolBase[MAX_SOCKET]; + UINT32 PciSocketMmiolLimit[MAX_SOCKET]; + UINT64 PciSocketMmiohBase[MAX_SOCKET]; + UINT64 PciSocketMmiohLimit[MAX_SOCKET]; + UINT16 PciResourceIoBase[TOTAL_IIO_STACKS]; + UINT16 PciResourceIoLimit[TOTAL_IIO_STACKS]; + UINT32 PciResourceMem32Base[TOTAL_IIO_STACKS]; + UINT32 PciResourceMem32Limit[TOTAL_IIO_STACKS]; + UINT64 PciResourceMem64Base[TOTAL_IIO_STACKS]; + UINT64 PciResourceMem64Limit[TOTAL_IIO_STACKS]; +} SOCKET_PCI_RESOURCE_CONFIGURATION_DATA; +#pragma pack() + +#endif // __SOCKET_PCI_RESOURCE_CONFIG_DATA_H__ + + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPowermanagementVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPowermanagementVariable.h new file mode 100644 index 0000000000..a6724ef0c3 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketPowermanagementVariable.h @@ -0,0 +1,224 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ +#define __SOCKET_POWERMANAGEMENT_CONFIGURATION_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketPowermanagementVarGuid; +#define SOCKET_POWERMANAGEMENT_CONFIGURATION_NAME L"SocketPowerManagementConfig" + +#define NUM_CST_LAT_MSR 3 + +#pragma pack(1) + +typedef struct { + UINT8 LOT26UnusedVrPowerDownEnable; + UINT8 WFRWAEnable; + UINT8 UFSDisable; // Allow Mailbox Command to PCU_MISC_CONFIG Bit[28] + UINT8 ProcessorEistEnable; // EIST or GV3 setup option + + // Config TDP + UINT8 ConfigTDP; + UINT8 ConfigTDPLevel; + + // Individual controls for ACPI sleep states + // ** These can be overridden by AcpiSleepState because these knobs are not available to CRB ** + // + UINT8 AcpiS3Enable; + UINT8 AcpiS4Enable; + + // + //HWPM starts + // + UINT8 ProcessorHWPMEnable; + UINT8 ProcessorAutonomousCstateEnable; + UINT8 ProcessorHWPMInterrupt; + UINT8 ProcessorEPPEnable; + UINT8 ProcessorEppProfile; + UINT8 ProcessorAPSrocketing; + UINT8 ProcessorScalability; + UINT8 ProcessorPPOBudget; + UINT8 ProcessorOutofBandAlternateEPB; + // + //HWPM ends + // + UINT8 PStateDomain; // P State Domain + UINT8 ProcessorEistPsdFunc; // EIST/PSD Function select option + UINT8 ProcessorSinglePCTLEn; // PCPS - SINGLE_PCTL select option + UINT8 ProcessorSPD; // PCPS - SPD select option + UINT8 BootPState; // Boot Performance Mode + + // + // Processor Control + // + UINT8 TurboMode; + UINT8 EnableXe; + + //OverClocking + UINT8 OverclockingLock; + + UINT8 TurboRatioLimitRatio[8]; + UINT8 TurboRatioLimitCores[8]; + + UINT8 C2C3TT; + UINT8 DynamicL1; // Enabling Dynamic L1 + UINT8 ProcessorCcxEnable; // Enabling CPU C states of processor + UINT8 PackageCState; // Package C-State Limit + UINT8 C3Enable; // Enable/Disable NHM C3(ACPI C2) report to OS + UINT8 C6Enable; // Enable/Disable NHM C6(ACPI C3) report to OS + UINT8 ProcessorC1eEnable; // Enabling C1E state of processor + UINT8 OSCx; // ACPI C States + + UINT8 CStateLatencyCtrlValid[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Valid + UINT8 CStateLatencyCtrlMultiplier[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Multiplier + UINT16 CStateLatencyCtrlValue[NUM_CST_LAT_MSR]; // C_STATE_LATENCY_CONTROL_x.Value + + UINT8 TStateEnable; // T states enable? + UINT8 OnDieThermalThrottling; // Throtte ratio + UINT8 ProchotLock; + UINT8 EnableProcHot; + UINT8 EnableThermalMonitor; + UINT8 ProchotResponse; + UINT8 EETurboDisable; + UINT8 SapmctlValCtl; + UINT8 PwrPerfTuning; + UINT8 AltEngPerfBIAS; + UINT8 PwrPerfSwitch; + UINT8 WorkLdConfig; + UINT16 EngAvgTimeWdw1; + + UINT8 ProchotResponseRatio; + UINT8 TCCActivationOffset; + + UINT8 P0TtlTimeLow1; + UINT8 P0TtlTimeHigh1; + + UINT8 PkgCLatNeg; + UINT8 LTRSwInput; + UINT8 SAPMControl; + UINT8 CurrentConfig; + UINT8 PriPlnCurCfgValCtl; + UINT8 Psi3Code; + UINT16 CurrentLimit; + + UINT8 Psi3Thshld; + UINT8 Psi2Code; + UINT8 Psi2Thshld; + UINT8 Psi1Code; + UINT8 Psi1Thshld; + + //Power Management Setup options + UINT8 PkgCstEntryValCtl; + + // PRIMARY_PLANE_CURRENT_CONFIG_CONTROL 0x601 + UINT8 PpcccLock; + + UINT8 SnpLatVld; + UINT8 SnpLatOvrd; + UINT8 SnpLatMult; + UINT16 SnpLatVal; + UINT16 NonSnpLatVld; + UINT8 NonSnpLatOvrd; + UINT8 NonSnpLatMult; + UINT16 NonSnpLatVal; + + // DYNAMIC_PERF_POWER_CTL (CSR 1:30:2:0x64) + UINT8 EepLOverride; + UINT8 EepLOverrideEn; + UINT8 ITurboOvrdEn; + UINT8 CstDemotOvrdEN; + UINT8 TrboDemotOvrdEn; + UINT8 UncrPerfPlmtOvrdEn; + UINT8 EetOverrideEn; + UINT8 IoBwPlmtOvrdEn; + UINT8 ImcApmOvrdEn; // unused + UINT8 IomApmOvrdEn; + UINT8 QpiApmOvrdEn; + UINT8 PerfPLmtThshld; + + // SAPMCTL_CFG (CSR 1:30:1:0xB0) + UINT8 Iio0PkgcClkGateDis[MAX_SOCKET]; //Bit[0] + UINT8 Iio1PkgcClkGateDis[MAX_SOCKET]; //Bit[1] + UINT8 Iio2PkgcClkGateDis[MAX_SOCKET]; //Bit[2] + UINT8 Kti01PkgcClkGateDis[MAX_SOCKET]; //Bit[3] + UINT8 Kti23PkgcClkGateDis[MAX_SOCKET]; //Bit[4] + UINT8 P0pllOffEna[MAX_SOCKET]; //Bit[16] + UINT8 P1pllOffEna[MAX_SOCKET]; //Bit[17] + UINT8 P2pllOffEna[MAX_SOCKET]; //Bit[18] + UINT8 Mc0pllOffEna[MAX_SOCKET]; //Bit[22] + UINT8 Mc1pllOffEna[MAX_SOCKET]; //Bit[23] + UINT8 Mc0PkgcClkGateDis[MAX_SOCKET]; //Bit[6] + UINT8 Mc1PkgcClkGateDis[MAX_SOCKET]; //Bit[7] + UINT8 Kti01pllOffEna[MAX_SOCKET]; //Bit[19] + UINT8 Kti23pllOffEna[MAX_SOCKET]; //Bit[20] + UINT8 SetvidDecayDisable[MAX_SOCKET]; //Bit[30]; + UINT8 SapmCtlLock[MAX_SOCKET]; //Bit[31]; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) + UINT8 PerfPLimitClip; + UINT8 PerfPLimitEn; + + // PERF_P_LIMIT_CONTROL (CSR 1:30:2:0xe4) >= HSX C stepping + UINT8 PerfPlimitDifferential; + UINT8 PerfPLimitClipC; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK2 (CSR 1:30:2:0x90) + UINT8 Kti0In[MAX_SOCKET]; + UINT8 Kti1In[MAX_SOCKET]; + UINT8 Kti2In[MAX_SOCKET]; + + // SKX: PKG_CST_ENTRY_CRITERIA_MASK (CSR 1:30:2:0x8c) + UINT8 PcieIio0In[MAX_SOCKET]; + UINT8 PcieIio1In[MAX_SOCKET]; + UINT8 PcieIio2In[MAX_SOCKET]; + UINT8 PcieIio3In[MAX_SOCKET]; + UINT8 PcieIio4In[MAX_SOCKET]; + UINT8 PcieIio5In[MAX_SOCKET]; + + UINT8 FastRaplDutyCycle; + UINT8 TurboPowerLimitLock; + UINT8 TurboPowerLimitCsrLock; + UINT8 PowerLimit1En; + UINT32 PowerLimit1Power; + UINT8 PowerLimit1Time; + UINT8 PkgClmpLim1; + UINT8 PowerLimit2En; + UINT32 PowerLimit2Power; + UINT8 PkgClmpLim2; + UINT8 PowerLimit2Time; + + UINT8 UsePmaxOffsetTable; + UINT8 PmaxSign; + UINT8 PmaxOffset; + + //XTU 3.0 + + UINT8 MaxEfficiencyRatio[MAX_SOCKET]; + UINT8 MaxNonTurboRatio[MAX_SOCKET]; + + // use SPT workarounds - B2P cmd MISC_WORKAROUND_ENABLE + UINT8 SPTWorkaround; + UINT8 VccSAandVccIOdisable; + +} SOCKET_POWERMANAGEMENT_CONFIGURATION; +#pragma pack() + +#endif + + + + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketProcessorCoreVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketProcessorCoreVariable.h new file mode 100644 index 0000000000..37c614bca2 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketProcessorCoreVariable.h @@ -0,0 +1,115 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ +#define __SOCKET_PROCESSORCORE_CONFIGURATION_DATA_H__ + + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" + +extern EFI_GUID gEfiSocketProcessorCoreVarGuid; +#define SOCKET_PROCESSORCORE_CONFIGURATION_NAME L"SocketProcessorCoreConfig" + +#pragma pack(1) + +typedef struct { + + UINT8 CpuidMaxValue; + UINT8 ExecuteDisableBit; + + UINT8 PchTraceHubEn; // PCH TRACE HUB + UINT8 C1AutoDemotion; // C1 Auto Demotion + UINT8 C3AutoDemotion; // C3 Auto Demotion + UINT8 ProcessorHyperThreadingDisable; // Hyper Threading [ALL] + UINT8 ProcessorLtsxEnable; // Enabling TXT + UINT8 ProcessorVmxEnable; // Enabling VMX + UINT8 ProcessorSmxEnable; // Enabling SMX + UINT8 ProcessorMsrLockControl; // MSR Lock Bit Control + UINT8 DebugInterface; // IA32_DEBUG_INTERFACE_MSR + UINT8 ThreeStrikeTimer; // Disable 3strike timer + UINT8 FastStringEnable; // Fast String + UINT8 MachineCheckEnable; // Machine Check + UINT8 MlcStreamerPrefetcherEnable; // Hardware Prefetch + UINT8 MlcSpatialPrefetcherEnable; // Adjacent Cache Line Prefetch + UINT8 DCUStreamerPrefetcherEnable; // DCU Streamer Prefetcher + UINT8 DCUIPPrefetcherEnable; // DCU IP Prefetcher + UINT8 DCUModeSelection; // DCU Mode Selection + UINT8 ProcessorX2apic; // Enable Processor XAPIC + UINT8 ForceX2ApicIds; // Force to use > 8bit ApicId + UINT8 BspSelection; // Select BSP + UINT8 IedSize; // IED size + UINT8 IedTraceSize; // IED trace size + UINT8 TsegSize; // TSEG size + UINT8 AllowMixedPowerOnCpuRatio; // Allow Mixed PowerOn CpuRatio + UINT8 CheckCpuBist; // check and disable BIST faile core or ignore + UINT8 ProcessorFlexibleRatio; // Non-Turbo Mode Processor Core Ratio Multiplier + UINT8 ProcessorFlexibleRatioOverrideEnable; // Non-Turbo Mode Processor Core Ratio Multiplier Enable + UINT8 MTRRDefTypeUncachable; // For changing UC to WB + UINT8 ForcePhysicalModeEnable; // Force physical destionation mode + UINT8 LlcPrefetchEnable; // LLC Prefetch + UINT8 ProcessorVirtualWireMode; + + UINT8 AesEnable; + UINT8 PpinControl; // PPIN Control MSR + UINT8 LockChipset; // Lock Chipset + UINT8 SkipStopPbet; // Skip StopPbet + + UINT8 BiosAcmErrorReset; // Disable LT-SX and reset system when BIOS ACM error occurs + UINT8 AcmType; // 0x80 = debug signed ACM; 0x40 = NPW production signed ACM; 0x00 = PW production signed ACM + + UINT32 CoreDisableMask[MAX_SOCKET]; // one for each CPU socket + // IOT/OCLA configs +#ifndef OCLA_TOR_ENTRY_MAX + #define OCLA_TOR_ENTRY_MIN 0 + #define OCLA_TOR_ENTRY_MAX 0x11 // 15 or 17 depending on Isoch on/off + #define OCLA_TOR_ENTRY_DEFAULT 1 + #define OCLA_WAY_MIN 0 + #define OCLA_WAY_MAX 8 // max 8 LLC ways out of 11 can be reserved for OCLA + #define OCLA_WAY_DEFAULT 1 +#endif + UINT8 IotEn[MAX_SOCKET]; + UINT8 OclaMaxTorEntry[MAX_SOCKET]; + UINT8 OclaMinWay[MAX_SOCKET]; + UINT32 IioLlcWaysMask; // MSR CBO_SLICE0_CR_IIO_LLC_WAYS bitmask. - Only Bits[22:0] are used + UINT32 ExpandedIioLlcWaysMask; // MSR INGRESS_SPARE[10:0] bitmask. - Only Bits[10:0] are used + UINT32 RemoteWaysMask; // MSR INGRESS_SPARE[26:16] bitmask. - Only Bits[10:0] are used + UINT32 QlruCfgMask_Lo; // MSR VIRTUAL_MSR_CR_QLRU_CONFIG bitmask - Lower 32-bit + UINT32 QlruCfgMask_Hi; // MSR VIRTUAL_MSR_CR_QLRU_CONFIG bitmask - Higher 32-bit + + + UINT8 PCIeDownStreamPECIWrite; + +// +// Targeted Smi Support +// + UINT8 TargetedSmi; +// +// eSMM Save State Mode +// + UINT8 eSmmSaveState; + + UINT8 PeciInTrustControlBit; //On Setup + + UINT8 Poison; + UINT8 Viral; + UINT8 EVMode; + UINT8 SmbusErrorRecovery; +} SOCKET_PROCESSORCORE_CONFIGURATION; +#pragma pack() + +#endif + + + + diff --git a/Silicon/Intel/PurleySktPkg/Include/Guid/SocketVariable.h b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketVariable.h new file mode 100644 index 0000000000..ac6c4dc0aa --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Include/Guid/SocketVariable.h @@ -0,0 +1,41 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef __SOCKET_CONFIG_DATA_H__ +#define __SOCKET_CONFIG_DATA_H__ + +#include <UncoreCommonIncludes.h> +#include "SocketConfiguration.h" +#include <Guid/SocketIioVariable.h> +#include <Guid/SocketCommonRcVariable.h> +#include <Guid/SocketPowermanagementVariable.h> +#include <Guid/SocketProcessorCoreVariable.h> +#include <Guid/SocketMpLinkVariable.h> +#include <Guid/SocketMemoryVariable.h> + +#pragma pack(1) + +typedef struct { + SOCKET_IIO_CONFIGURATION IioConfig; + SOCKET_COMMONRC_CONFIGURATION CommonRcConfig; + SOCKET_MP_LINK_CONFIGURATION CsiConfig; + SOCKET_MEMORY_CONFIGURATION MemoryConfig; + SOCKET_POWERMANAGEMENT_CONFIGURATION PowerManagementConfig; + SOCKET_PROCESSORCORE_CONFIGURATION SocketProcessorCoreConfiguration; +} SOCKET_CONFIGURATION; + + + +#pragma pack() +#endif + |