diff options
Diffstat (limited to 'Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib')
4 files changed, 427 insertions, 0 deletions
diff --git a/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h new file mode 100644 index 0000000000..e40505d880 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CpuCsrAccessDefine.h @@ -0,0 +1,62 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _CPU_CSR_ACCESS_DEFINE_H_ +#define _CPU_CSR_ACCESS_DEFINE_H_ + +#include <SysHost.h> +#include <MemHost.h>
+#include <Library/PcieAddress.h> + +#include <CsrToPcieAddress.h> +#include <CpuPciAccessCommon.h> + + +typedef enum { + BUS_CLASS = 0, + DEVICE_CLASS = 1, + FUNCTION_CLASS = 2 +} BDF_CLASS; + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ); + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType + ); + +UINT32 +GetCpuCsrAddress ( + UINT8 SocId, + UINT8 BoxInst, + UINT32 Offset, + UINT8 *Size + ); + +UINT32 +GetMmcfgAddress( + PSYSHOST host + ); + +VOID +GetCpuCsrAccessVar_RC ( + PSYSHOST host, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar + ); + +#endif // _CPU_CSR_ACCESS_DEFINE_H_ diff --git a/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf new file mode 100644 index 0000000000..ccdf763bef --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieDxeLib.inf @@ -0,0 +1,92 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CsrToPcieDxeLib
+ FILE_GUID = FF3C93E7-30DE-49DE-9C02-56C2BC077561
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CsrToPcieLib
+
+## {FF3C93E7-30DE-49DE-9C02-56C2BC077561}
+##{ 0xff3c93e7, 0x30de, 0x49de, { 0x9c, 0x2, 0x56, 0xc2, 0xbc, 0x7, 0x75, 0x61 } };
+
+
+[Sources]
+ CsrToPcieLib.c
+ ../ProcMemInit/Chip/Common/CpuPciAccessCommon.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleySktPkg/SocketPkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ UefiRuntimeServicesTableLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEfiIioUdsProtocolGuid
+
+[Guids]
+ gEfiCpRcPkgTokenSpaceGuid
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Depex]
+ gEfiIioUdsProtocolGuid
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr
+
+
+[BuildOptions.Ia32]
+ MSFT:*_*_*_CC_FLAGS = /W4 /Gs999999 /GF /GL- /wd4214 /wd4334 /wd4142 /wd4819 /DBUILDING_FOR_IA32 /DIA32 $(DSC_GLOBAL_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS = -DBUILDING_FOR_IA32 -DIA32 $(DSC_GLOBAL_BUILD_OPTIONS)
+
+[BuildOptions.X64]
+ MSFT:*_*_X64_CC_FLAGS = /W2 /Gs32768 /DKTI_HW_PLATFORM /DBUILDING_FOR_X64 /UIA32 /DRAS_FEATURES /wd4142 /wd4819 $(DSC_GLOBAL_BUILD_OPTIONS)
+ GCC:*_*_X64_CC_FLAGS = -DKTI_HW_PLATFORM -DBUILDING_FOR_X64 -UIA32 -DRAS_FEATURES $(DSC_GLOBAL_BUILD_OPTIONS)
diff --git a/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieLib.c b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieLib.c new file mode 100644 index 0000000000..d6b98f2aec --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPcieLib.c @@ -0,0 +1,185 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved.<BR> +This program and the accompanying materials are licensed and made available under +the terms and conditions of the BSD License that accompanies this distribution. +The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php. + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#include "CpuCsrAccessDefine.h" +#include "CpuPciAccess.h" + +CPU_CSR_ACCESS_VAR *gCpuCsrAccessVarPtr = NULL; +CPU_CSR_ACCESS_VAR gCpuCsrAccessVar; + + +UINT32 +GetSegmentNumber ( + IN USRA_ADDRESS *Address + ) +{ + return 0; +}; + +UINT32 +GetBDFNumber ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + IN UINT8 BDFType +// UINT8 SocId, +// UINT8 BoxType + ) +/*++ + +Routine Description: + Indetifies the bus number for given SocId & BoxType + +Arguments: + Address - A pointer of the address of the USRA Address Structure with Csr or CsrEx type + +Returns: + PCI bus number + +--*/ +{ + UINT32 Data32 =0 ; + UINT8 SocId; + UINT8 BoxType; + UINT8 BoxInst; + UINT8 FuncBlk; + PSYSHOST host; + + SocId = (UINT8)Address->Csr.SocketId; + BoxType = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.boxtype; + BoxInst = (UINT8)Address->Csr.InstId; + FuncBlk = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.funcblk; +#ifdef IA32 + host = (PSYSHOST)Address->Attribute.HostPtr; +#else + host = (PSYSHOST)NULL; +#endif + if(BDFType == BUS_CLASS){ + Data32 = GetBusNumber(host, SocId, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + } else if(BDFType == DEVICE_CLASS){ + Data32 = GetDeviceNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + } else { + Data32 = GetFunctionNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + } + return Data32; + +} + +VOID +GetBDF ( + IN USRA_ADDRESS *Address, + CPU_CSR_ACCESS_VAR *CpuCsrAccessVar, + USRA_PCIE_ADDR_TYPE *PcieAddress + ) +/*++ + +Routine Description: + Indetifies the bus number for given SocId & BoxType + +Arguments: + Address - A pointer of the address of the USRA Address Structure with Csr or CsrEx type + +Returns: + PCI bus number + +--*/ +{ + UINT8 SocId; + UINT8 BoxType; + UINT8 BoxInst; + UINT8 FuncBlk; + PSYSHOST host; + + SocId = (UINT8)Address->Csr.SocketId; + BoxType = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.boxtype; + BoxInst = (UINT8)Address->Csr.InstId; + FuncBlk = (UINT8)((CSR_OFFSET *)(&Address->Csr.Offset))->Bits.funcblk; +#ifdef IA32 + host = (PSYSHOST)Address->Attribute.HostPtr; +#else + host = (PSYSHOST)NULL; +#endif + PcieAddress->Bus = GetBusNumber(host, SocId, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + PcieAddress->Dev = GetDeviceNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + PcieAddress->Func = GetFunctionNumber(host, BoxType, BoxInst, FuncBlk, CpuCsrAccessVar); + PcieAddress->Seg = SocId; // Refcode and EFI data structure difference. Refcode treats this array as 1 entry per socket, and not per segment, thus we index by SocId for now.. +} +////////////////////////////////////////////////////////////////////////// +// +// USRA Silicon Address Library +// This Lib provide the way use platform Library instance +// +////////////////////////////////////////////////////////////////////////// + +/** + This Lib Convert the logical address (CSR type, e.g. CPU ID, Boxtype, Box instance etc.) into physical address + + @param[in] Global Global pointer + @param[in] Virtual Virtual address + @param[in] Address A pointer of the address of the USRA Address Structure + @param[out] AlignedAddress A pointer of aligned address converted from USRA address + + @retval NULL The function completed successfully. + @retval <>NULL Return Error +**/ +UINTN +EFIAPI +CsrGetPcieAlignAddress ( + IN VOID *Global, + IN BOOLEAN Virtual, + IN USRA_ADDRESS *Address, + OUT UINTN *AlignedAddress + ) +{ + CPU_CSR_ACCESS_VAR *pCpuCsrAccessVar; + USRA_ADDRESS UsraAddress; + INTN MmCfgBase; + + /********************************************************************************************************* + ToDo: + For now, this implementation only covers the Bus/Dev/Fun number generation for IVT and HSX CPUs. + Register offset and size information comes from the HSX style register offset passed to this function. + When the auto generation of header files using the new format is available, then we need to implement + the logic to translate the register pseudo offset into real offset. + *********************************************************************************************************/ + Address->Attribute.AccessWidth = (UINT8) (((((CSR_OFFSET *) &Address->Csr.Offset)->Bits.size) & 0x06) >> 1); + +#if defined (IA32) || defined (SIM_BUILD) || defined(KTI_SW_SIMULATION) || defined (HEADLESS_MRC) + CpuDeadLoop(); + pCpuCsrAccessVar = NULL; + +#else + gCpuCsrAccessVarPtr = &gCpuCsrAccessVar; + GetCpuCsrAccessVar_RC ((PSYSHOST)host, &gCpuCsrAccessVar); + + pCpuCsrAccessVar = &gCpuCsrAccessVar; +#endif // defined + + // + // Identify the PCI Bus/Device/Function number for the access + // + USRA_ZERO_ADDRESS_TYPE(UsraAddress, AddrTypePCIE); + GetBDF(Address, pCpuCsrAccessVar, &UsraAddress.Pcie); + + UsraAddress.Pcie.Offset = (UINT16)((CSR_OFFSET *) &Address->Csr.Offset)->Bits.offset; + UsraAddress.Attribute.HostPtr = Address->Attribute.HostPtr; + + MmCfgBase = GetPcieSegMmcfgBaseAddress(&UsraAddress); + *AlignedAddress = MmCfgBase + (UINTN)(UsraAddress.Attribute.RawData32[0] & 0x0fffffff); + +#if defined (IA32) || defined (SIM_BUILD) || defined(KTI_SW_SIMULATION) || defined (HEADLESS_MRC) + CpuDeadLoop(); +#endif + + return 0; +}; + diff --git a/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf new file mode 100644 index 0000000000..27616a22f4 --- /dev/null +++ b/Silicon/Intel/PurleySktPkg/Library/CsrToPcieLib/CsrToPciePeiLib.inf @@ -0,0 +1,88 @@ +### @file
+#
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials are licensed and made available under
+# the terms and conditions of the BSD License which accompanies this distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CsrToPciePeiLib
+ FILE_GUID = C18FB69B-D1A7-4EF0-988D-2A40FE2E96B0
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = CsrToPcieLib
+
+## {C18FB69B-D1A7-4EF0-988D-2A40FE2E96B0}
+##{ 0xc18fb69b, 0xd1a7, 0x4ef0, { 0x98, 0x8d, 0x2a, 0x40, 0xfe, 0x2e, 0x96, 0xb0 } };
+
+
+[Sources]
+ CsrToPcieLib.c
+ ../ProcMemInit/Chip/Common/CpuPciAccessCommon.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ PurleySktPkg/SocketPkg.dec
+ PurleyRcPkg/RcPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+
+[Protocols]
+
+[Guids]
+ gEfiCpRcPkgTokenSpaceGuid
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Depex]
+
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieSegmentSize
+ gEfiCpRcPkgTokenSpaceGuid.PcdPcieMmcfgTablePtr
+
+
+[BuildOptions.Ia32]
+ MSFT:*_*_*_CC_FLAGS = /W4 /Gs999999 /GF /GL- /wd4214 /wd4334 /wd4142 /wd4819 /DBUILDING_FOR_IA32 /DIA32 $(DSC_GLOBAL_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS = -DBUILDING_FOR_IA32 -DIA32 $(DSC_GLOBAL_BUILD_OPTIONS)
+
+[BuildOptions.X64]
+ MSFT:*_*_X64_CC_FLAGS = /W2 /Gs32768 /DKTI_HW_PLATFORM /DBUILDING_FOR_X64 /UIA32 /DRAS_FEATURES /wd4142 /wd4819 $(DSC_GLOBAL_BUILD_OPTIONS)
+ GCC:*_*_X64_CC_FLAGS = -DKTI_HW_PLATFORM -DBUILDING_FOR_X64 -UIA32 -DRAS_FEATURES $(DSC_GLOBAL_BUILD_OPTIONS)
|