diff options
Diffstat (limited to 'Silicon')
3 files changed, 28 insertions, 1 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h index 27cc50be1c..5c961e6a66 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/ScRegs/RegsSpi.h @@ -17,7 +17,7 @@ - Registers / bits of new devices introduced in a SC generation will be just named
as "_SC_" without <generation_name> inserted.
- Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -92,6 +92,7 @@ #define B_SPI_HSFS_FLOCKDN BIT15 ///< Flash Configuration Lock-Down
#define B_SPI_HSFS_FDV BIT14 ///< Flash Descriptor Valid
#define B_SPI_HSFS_FDOPSS BIT13 ///< Flash Descriptor Override Pin-Strap Status
+#define B_SPI_HSFS_WRSDIS BIT11 ///< Write Status Disable
#define B_SPI_HSFS_SCIP BIT5 ///< SPI Cycle in Progress
#define B_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) ///< Block/Sector Erase Size
#define V_SPI_HSFS_BERASE_256B 0//0x00 ///< Block/Sector = 256 Bytes
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c index 97a13fa0d7..722f297309 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/BaseScSpiCommonLib/SpiCommon.c @@ -601,6 +601,7 @@ SendSpiCmd ( UINT8 BiosCtlSave;
UINT32 SmiEnSave;
UINT16 ABase;
+ UINT32 HsfstsCtl;
Status = EFI_SUCCESS;
SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
@@ -653,6 +654,15 @@ SendSpiCmd ( goto SendSpiCmdEnd;
}
+
+ if (FlashCycleType == FlashCycleWriteStatus) {
+ HsfstsCtl = MmioRead32 (ScSpiBar0 + R_SPI_HSFS);
+ if ((HsfstsCtl & B_SPI_HSFS_WRSDIS) != 0) {
+ Status = EFI_ACCESS_DENIED;
+ goto SendSpiCmdEnd;
+ }
+ }
+
HardwareSpiAddr = Address;
if ((FlashCycleType == FlashCycleRead) ||
(FlashCycleType == FlashCycleWrite) ||
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c index 3fb37ead52..ebb424bd5e 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/ScInit/Dxe/ScInit.c @@ -639,6 +639,8 @@ ScOnEndOfDxe ( UINT16 Data16Or;
SI_POLICY_HOB *SiPolicyHob;
EFI_PEI_HOB_POINTERS HobPtr;
+ UINT16 Data16;
+ UINTN SpiBar0;
NumOfDevltrOverride = 0;
PciLpcRegBase = MmPciBase (
@@ -678,6 +680,20 @@ ScOnEndOfDxe ( (VOID *) (UINTN) (PmcBase + R_PMC_PMIR)
);
+ if (BxtSeries == BxtP){
+ SpiBar0 = MmioRead32 (PciSpiRegBase + R_SPI_BASE) &~(B_SPI_BAR0_MASK);
+
+ Data16 = (UINT16) (B_SPI_HSFS_FLOCKDN | B_SPI_HSFS_WRSDIS);
+ MmioWrite16 ((UINTN) (SpiBar0 + R_SPI_HSFS), Data16);
+ S3BootScriptSaveMemWrite (
+ EfiBootScriptWidthUint16,
+ (UINTN) (SpiBar0 + R_SPI_HSFS),
+ 1,
+ &Data16
+ );
+
+ }
+
Status = GetConfigBlock ((VOID *) mScPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
ASSERT_EFI_ERROR (Status);
if (LockDownConfig->GlobalSmi == TRUE) {
|