diff options
Diffstat (limited to 'Silicon')
| -rw-r--r-- | Silicon/Marvell/Documentation/PortingGuide.txt | 67 |
1 files changed, 50 insertions, 17 deletions
diff --git a/Silicon/Marvell/Documentation/PortingGuide.txt b/Silicon/Marvell/Documentation/PortingGuide.txt index 83ebe9df5b..25cb66b44b 100644 --- a/Silicon/Marvell/Documentation/PortingGuide.txt +++ b/Silicon/Marvell/Documentation/PortingGuide.txt @@ -57,35 +57,68 @@ Every ComPhy PCD has <Num> part where <Num> stands for chip ID (order is not important, but configuration will be set for first PcdComPhyChipCount chips). Every chip has 3 ComPhy PCDs and three of them comprise per-board lanes -settings for this chip. Their format is unicode string, containing settings -for up to 10 lanes. Setting for each one is separated with semicolon. -These PCDs together describe outputs of PHY integrated in simple cihp. -Below is example for the first chip (Chip0). +settings for this chip. Their format is array of up to 10 values reflecting +defined numbers for SPEED/TYPE/INVERT, whose description can be found in: - - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes - (Unicode string indicating PHY types. Currently supported are: + OpenPlatformPkg/Platforms/Marvell/Library/ComPhyLib/ComPhyLib.h - { L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", L"PCIE3", - L"SATA0", L"SATA1", L"SATA2", L"SATA3", L"SGMII0", - L"SGMII1", L"SGMII2", L"SGMII3", L"QSGMII", - L"USB3_HOST0", L"USB3_HOST1", L"USB3_DEVICE", - L"XAUI0", L"XAUI1", L"XAUI2", L"XAUI3", L"RXAUI0", - L"RXAUI1", L"KR" } ) + - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes + (Array of types - currently supported are: + + CP_UNCONNECTED 0x0 + CP_PCIE0 0x1 + CP_PCIE1 0x2 + CP_PCIE2 0x3 + CP_PCIE3 0x4 + CP_SATA0 0x5 + CP_SATA1 0x6 + CP_SATA2 0x7 + CP_SATA3 0x8 + CP_SGMII0 0x9 + CP_SGMII1 0xA + CP_SGMII2 0xB + CP_SGMII3 0xC + CP_QSGMII 0xD + CP_USB3_HOST0 0xE + CP_USB3_HOST1 0xF + CP_USB3_DEVICE 0x10 + CP_XAUI0 0x11 + CP_XAUI1 0x12 + CP_XAUI2 0x13 + CP_XAUI3 0x14 + CP_RXAUI0 0x15 + CP_RXAUI1 0x16 + CP_SFI 0x17 ) - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds - (Indicates PHY speeds in MHz. Currently supported are: - { 1250, 1500, 2500, 3000, 3125, 5000, 6000, 6250, 1031 } ) + (Array of speeds - currently supported are: + + CP_1_25G 0x1 + CP_1_5G 0x2 + CP_2_5G 0x3 + CP_3G 0x4 + CP_3_125G 0x5 + CP_5G 0x6 + CP_5_15625G 0x7 + CP_6G 0x8 + CP_6_25G 0x9 + CP_10_3125G 0xA ) - gMarvellTokenSpaceGuid.PcdChip0ComPhyInvFlags - (Indicates lane polarity invert) + (Array of lane inversion types - currently supported are: + + CP_NO_INVERT 0x0 + CP_TXD_INVERT 0x1 + CP_RXD_INVERT 0x2 + CP_ALL_INVERT 0x3 ) Example ------- #ComPhy gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 } - gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|L"SGMII1;USB3_HOST0;SFI;SATA1;USB3_HOST1;PCIE2" - gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|L"1250;5000;10310;5000;5000;5000" + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_SGMII1), $(CP_USB3_HOST0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) } + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) } PHY Driver configuration |