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2017-11-28Adjust default MemoryTypeInfo to avoid reset in first boot.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-28Remove DebugLib override for PlatformInitDxe.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-28Add Check for MemoryAttributeTable.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-28Fix typo - Funtional to FunctionalJiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-28TestPoint: avoid using ReportStatus code to make test point check as last one.Jiewen Yao
Use event signal instead. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-28Add GCD test for ACPI resource reporting.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-13Update TestPoint PCD based upon stage.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-13Add DMA protection check test point.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-13cleanup test point bit definition.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-13Add SMM test point according to the design.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-08Add trusted console and trusted storage.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-01Add VTD_INFO dependency to make sure IOMMU enabled before MRC.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-01move VTd to PreMem to support pre-mem DMA protection.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-01Install SiliconInitializedPpi in FspProcessHob to indicate silicon init is done.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-01Add SiliconInitializedPpi GUID.Jiewen Yao
This GUID is an indicator that the silicon is initialized. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-11-01Separate FspMT.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
2017-11-01Decouple Graphics Console Selection from MinPlatformPkgChen, Pai-chingX
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Pai-chingX Chen <pai-chingx.chen@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-10-31Add NULL check for GetPciSegmentInfo()Jiewen Yao
Suggested-by: Michael A Kubacki <michael.a.kubacki@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-10-31Rename PcdPlatformMemoryCheck to PcdPlatformMemoryCheckLevel.Jiewen Yao
Suggested-by: Michael A Kubacki <michael.a.kubacki@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-10-24Add TestPointStubDxe in DSC.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-24Clean up Checkpoint.Jiewen Yao
1) CheckPointLib interface to be feature based, instead of phase based. 2) Rename file from Dump to Check. 3) Add TestPointStub to help convert PEI/SMM info to DXE protocol. 4) Implement all check points. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-24Enable SmiHandlerProfile in DSC.Jiewen Yao
Enable SmiHandlerProfile in debug build. Disable SmiHandlerProfile in release build. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-24Enable SmiHandlerProfile in Silicon code.Jiewen Yao
Make SmiChildDispatch report the SMI handler information. As such, people can know how many SMI child handlers are installed. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-24Support SmiHandlerProfile.Jiewen Yao
Add PcdSmiHandlerProfileEnable in MinPlatform package to help the platform enable SMI handler profile feature. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-24Add memory test support.Jiewen Yao
Without memory test, the untested memory is reported as reserved memory in UEFI memory map. After this is added, we can see above 4GiB memory in UEFI memory map. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-24Performance improvement.Jiewen Yao
MemoryInit code will consume the DISB bit in PCH (DRAM Initialization Scratchpad Bit - GEN_PMCON_A[23]) to decide if it goes optimization path. With this change, the time of MemoryInit API is reduced from 10 seconad to 69 millisecond. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-24Add PciSegmentInfoLib in DSC file.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-24Add PciSegmentInfoLibSimple.Jiewen Yao
This instance will be consumed by TestPointCheckLib. It reports PCI segment information in PEI phase, to let TestPointCheckLib go through the PCI to check BME bit. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-24Add PcdSecSerialPortDebugEnable for SecLibJiewen Yao
Check PcdSecSerialPortDebugEnable to see if SerialPortInitialize () need to be skipped. Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-10-20PolicyInitLib fix build error.Jiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-10-09Fix iASL compiler report error.Jiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-09-28Rename gPlatformModuleTokenSpaceGuid to gMinPlatformModuleTokenSpaceGuid.Jiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-09-28Rename gPlatformModuleTokenSpaceGuid to gMinPlatformModuleTokenSpaceGuid.Jiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-09-28MinKabylake: Reorg FVJiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com> Reviewed-by: Isaac W Oram <isaac.w.oram@intel.com>
2017-09-28MinPlatform: Reorg FVJiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com> Reviewed-by: Isaac W Oram <isaac.w.oram@intel.com>
2017-09-18Resolve build issue with latest EDKII.Jiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-09-04new policy design for open board.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-09-04new policy design for silicon.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-09-04new policy design for min platform.Jiewen Yao
Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Brett Wang <brett.wang@intel.com> Cc: Daocheng Bu <daocheng.bu@intel.com> Cc: Isaac W Oram <isaac.w.oram@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael A Kubacki <michael.a.kubacki@intel.com> Reviewed-by: Amy Chan <amy.chan@intel.com>
2017-08-29Readme: Correct build step.Jiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Pai Ching Chen <pai-chingx.chen@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2017-08-14KabylakeSiliconPkg: Publish DMAR table at PciEnumDone.Jiewen Yao
As such, we can start DMA protection as early as possible. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
2017-08-14KabylakeOpenBoardPkg: Enable performance build.Jiewen Yao
Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
2017-08-14MinPlatformPkg: Enable performance build.Jiewen Yao
Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
2017-08-14MinPlatformPkg: fix build failure.Jiewen Yao
Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
2017-08-14KabylakeOpenBoardPkg: Add IntelVTd driver.Jiewen Yao
Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
2017-08-14KabylakeOpenBoardPkg: remove board reference.Jiewen Yao
Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Cc: Michael A Kubacki <michael.a.kubacki@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
2017-07-17Update comment for FspPolicyInit/Update.Jiewen Yao
Suggested-by: Pai-chingX Chen <pai-chingx.chen@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-07-01Fix some typo.Jiewen Yao
reviewed-by: Rangasai V Chaganty <rangasai.v.chaganty@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-06-29remove unused path in build bat.Jiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
2017-06-28Add initial document.Jiewen Yao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-19 10:25:44 +0000