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2017-05-05Use GP_CAMERASB10 as Board_ID3.devel-MinnowBoard3zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com> CC: Mang Guo <mang.guo@intel.com> CC: Shifei Lu <shifeix.a.lu@intel.com>
2017-05-05Clean up BOARD_ID identification code.zwei4
BOARD_ID bits and GPIO pins mapping: BOARD_ID0 GPIO_224(J45) BOARD_ID1 GPIO_213(M47) BOARD_ID2 GPIO_223(H48) BOARD_ID3 GP_CAMERASB10(R34) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com> CC: Mang Guo <mang.guo@intel.com> CC: Shifei Lu <shifeix.a.lu@intel.com>
2017-04-26Add script to build ResetVector.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-04-25Fix setup assert issueGuo Mang
Debug BIOS will assert if change setup and save. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-04-25Fix issue in PlatformSMMGuo Mang
Change code to set R_SMI_EN earlier in S3 boot path to make sure all SMI were detected. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-04-14Change BIOS versionLu, ShifeiX A
Change BIOS version to 0.63 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-04-14Configure GPIO.Lu, ShifeiX A
GPIO configuration for Low Speed Expander and System Feature Expander pins. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-04-13GPIO clean up.Lu, ShifeiX A
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-04-13GPIO clean up.Wei, David
Reviewed-by: zwei4 <david.wei@intel.com> Thanks, David Wei -----Original Message----- From: Lu, ShifeiX A Sent: Thursday, April 13, 2017 11:31 AM To: edk2-devel@lists.01.org Cc: Wei, David <david.wei@intel.com> Subject: [Patch][edk2-platforms/devel-MinnowBoard3] GPIO clean up. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-04-12Configure VBT table.zwei4
Add VBT for MIPI LFP; Change HDMI drive strength to 400mV 0dB. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-04-12Fix S3 resume failureGuo Mang
When restoring MSR for S3 setting, SmmStartupThisAp will return error if CPU index is BSP. This issue caused S3 resume failed sometimes. This patch is mainly fix this issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-04-12UefiCpuPkg/PiSmmCpuDxeSmm: Clear some semaphores on S3 boot pathJeff Fan
Some semaphores are not cleared on S3 boot path. For example, mSmmMpSyncData->CpuData[CpuIndex].Present. It may still keeps the value set at SMM runtime during S3 resume. It may causes BSP have the wrong judgement on SMM AP's present state. We have one related fix at e78a2a49ee6b0c0d7c6997c87ace31d7761cf636. But that is not completed. This fix is to clear Busy/Run/Present semaphores in InitializeMpSyncData(). Cc: Laszlo Ersek <lersek@redhat.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 56e4a7d72660b229be333bbb5e1b5790d3c17890)
2017-04-10Fix build failure.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-04-10Add code for IPC.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-04-10Merge branch 'devel-MinnowBoard3' of github.com:tianocore/edk2-platforms ↵zwei4
into devel-MinnowBoard3
2017-04-06Add SATA initialization.lushifex
Add additional SATA initialization code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-04-06Fix set variable issueGuo Mang
Change variable attribute to fix variable couldn't be set issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-04-06Fix get variable issueGuo Mang
Fix "AcpiGlobalVariable" couldn't be get issue. S3 memory info was saved in this variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-04-05Fix several issues of S3Guo Mang
1. Fix "AcpiGlobalVariable" couldn't be get issue. S3 memory info was saved in this variable. 2. Override PiSmmCpuDxeSmm to fix S3 failure issue. This override can be removed after upgrading core. 3. Fix set variable failure issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-03-22Add SSDT table tool.Lu, ShifeiX A
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-03-17Enable Processor Power Management.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-03-17Fix RAM size issueGuo Mang
RAM SIZE in frontpage is not correct. Pass correct DRAM density parameter to FSP to fix this issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-03-16Add OBB verification code.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-03-16Add PEI SPI library.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-03-16Add BPDT library.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-03-10Change BIOS versionGuo Mang
Change BIOS version to 0.62 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: Wei David <david.wei@intel.com>
2017-03-09Fix Graphic issueGuo, Mang
Fix Graphic driver not connect issue when boot to OS if fastboot enable. Set network default disable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: david.wei@intel.com
2017-03-06Adjust FVs size and base.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-03-02Enable fastbootGuo Mang
1. Unload UNDI if fastboot enable. 2. Optimized the FV decompressing process Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-03-01Reformat ReadMe.MDRebecca Cran
The formatting of ReadMe.MD on GitHub wasn't very nice, with steps running into one another. This change reformats the text to use GitHub Flavored Markdown. It also simplifies a few of the steps, for example combining the git clone and rename into a single command Signed-off-by: Rebecca Cran <rebecca@bluestop.org> Reviewed-by: Guo Mang <mang.guo@intel.com>
2017-02-22Enable Secure Boot.lushifex
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-02-16Fix MRC restore issueGuo Mang
MCR parameter restored in the second time of boot, so the boot time is less than the first time of boot. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-02-14Fixed Map-r issue.Lu, ShifeiX A
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-02-13SPI Flash Lock.zwei4
Cleanup code about locking SPI Flash; Change the default value of BIOS Lock setup option to FALSE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com>
2017-02-13Change DSC and FDF.zwei4
Add SPI and FirmwareUpdate modules into build meta-data files. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com>
2017-02-13Add SPI modules.lushifex
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Signed-off-by: David Wei <david.wei@intel.com>
2017-02-13Add FirmwareUpdate applicationzwei4
Add FirmwareUpdate application for Minnnowboard 3, which is for updating 8MB SPI NOR flash. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-02-08Change MRC parameterGuo Mang
These code cause HDMI cable of some vendor couldn't work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: lushifex <shifeix.a.lu@intel.com>
2017-02-08Change BIOS version to 0061Guo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: Shifei Lu <shifeix.a.lu@intel.com>
2017-02-04Fix MRC parameters restore failure issueGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-01-22Add USB peripheral modeGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
2017-01-20Set TPM to Disabled.Lu, ShifeiX A
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-01-20Enable Mor.Lu, ShifeiX A
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-01-18Restore P2SB MMIO resourcezwei4
Restore P2SB's, as well as GPIO controllers', MMIO resources to original values which have been overridden by PCI bus driver. Signed-off-by: zwei4 <david.wei@intel.com> Cc: Mike Wu <mike.wu@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Mang Guo <mang.guo@intel.com> Cc: Shifei Lu <shifeix.a.lu@intel.com> Cc: Ruth Li <ruth.li@intel.com> Cc: Junjie He <junjie.he@intel.com>
2017-01-18Merge branch 'devel-MinnowBoard3' of ↵zwei4
https://github.com/tianocore/edk2-platforms into devel-MinnowBoard3
2017-01-18Enable SD card.zwei4
Fixed the issue that SD card cannot be detected by BIOS. Add SD host and device drivers. Signed-off-by: zwei4 <david.wei@intel.com> Cc: Mike Wu <mike.wu@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Mang Guo <mang.guo@intel.com> Cc: Shifei Lu <shifeix.a.lu@intel.com> Cc: Ruth Li <ruth.li@intel.com>
2017-01-17Enable SD card.zwei4
Fixed the issue that SD card cannot be detected by BIOS. Add SD host and device drivers. Signed-off-by: zwei4 <david.wei@intel.com> Cc: Mike Wu <mike.wu@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Mang Guo <mang.guo@intel.com> Cc: Shifei Lu <shifeix.a.lu@intel.com> Cc: Ruth Li <ruth.li@intel.com>
2017-01-12Remove platform policyzwei4
Remove silicon platform policy which is not used by any silicon code. Signed-off-by: zwei4 <david.wei@intel.com> Reviewed-by: Mang Guo <mang.guo@intel.com> Cc: Mike Wu <mike.wu@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Mang Guo <mang.guo@intel.com> Cc: Shifei Lu <shifeix.a.lu@intel.com>
2017-01-12Fix build error.Wei, David
Reviewed-by: zwei4 <david.wei@intel.com> Thanks, David Wei -----Original Message----- From: Lu, ShifeiX A Sent: Monday, January 09, 2017 9:39 AM To: edk2-devel@lists.01.org Cc: Wei, David <david.wei@intel.com> Subject: [Patch][edk2-platforms/devel-MinnowBoard3] Fix build error. Fix build error for latest VS2015 compiler with IA32 tip. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-01-12Remove platform policies which are not used.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-24 03:44:24 +0000