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2016-11-21SecurityPkg SmmTcg2PhysicalPresenceLib: Enable Storage actions.Eric Dong
After enable storage related actions in the TcgPhysicalPresenceStorageLib, use this library to support storage related actions in this library. Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com>
2016-11-21SecurityPkg DxeTcgPhysicalPresenceLib: Enable Storage actions.Eric Dong
After enable storage related actions in the TcgPhysicalPresenceStorageLib, use this library to support storage related actions in this library. Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com>
2016-11-21SecurityPkg DxeTcg2PhysicalPresenceLib: Enable Storage actions.Eric Dong
After enable storage related actions in the TcgPhysicalPresenceStorageLib, use this library to support storage related actions in this library. Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com>
2016-11-21SecurityPkg: Add SmmTcgPhysicalPresenceStorageLib.Eric Dong
Tcg Physical Presence spec defined some actions used for storage device. Add Smm version library to handles these actions. Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com>
2016-11-21SecurityPkg: Add DxeTcgPhysicalPresenceStorageLib.Eric Dong
Tcg Physical Presence spec defined some actions used for storage device. Add Dxe version library to handles these actions. Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com>
2016-11-21SecurityPkg: Add header file for TcgPhysicalPresenceStorageLib.Eric Dong
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com>
2016-11-21SecurityPkg: Add definition for Physical Presence storage flag.Eric Dong
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com>
2016-11-21SecurityPkg Tcg2Pei: Add comments into LogHashEvent()Star Zeng
Add comments into LogHashEvent() to describe the usage of GetDigestListSize (DigestList). Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-21SecurityPkg Tcg2Dxe: Get correct digest list sizeStar Zeng
Current code uses GetDigestListSize(DigestList) to get digest list size, that is incorrect. The code should get digest list size of digests copied into event2 log, those digests are compacted, so GetDigestListBinSize() should be used. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-21SecurityPkg Tcg2Dxe: Filter inactive digest in event2 log from PEI HOBStar Zeng
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by : Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-21SecurityPkg TPM2: Update desc for param Buffer of GetDigestListSize()Star Zeng
To make the description more clear, update the description for parameter Buffer of GetDigestListSize() to "Buffer to hold copied TPML_DIGEST_VALUES compact binary.". Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by : Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-21SecurityPkg TPM2: Add GetHashMaskFromAlgo() into Tpm2CommandLibStar Zeng
Add GetHashMaskFromAlgo() into Tpm2CommandLib for coming consumer. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by : Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-21SecurityPkg TPM2: Make IsHashAlgSupportedInHashAlgorithmMask externalStar Zeng
Current IsHashAlgSupportedInHashAlgorithmMask is only an internal function, this patch makes it external for coming consumer. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by : Chao Zhang <chao.b.zhang@intel.com>
2016-11-21SecurityPkg TPM2: Assign real copied count in CopyDigestListToBuffer()Star Zeng
In CopyDigestListToBuffer() of Tpm2CommandLib, the count in returned Buffer should be real copied DigestList count. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-21MdePkg BaseLib: API PathRemoveLastItem not handle root paths properlyHao Wu
https://bugzilla.tianocore.org/show_bug.cgi?id=239 When the input path for API PathRemoveLastItem() is a root path like 'fs0:\', the API will return TRUE (indicating a directory or file was removed from the path) and modifies the path to 'fs0:'. In fact, there's no directory or file removed in the above case. This commit adds additional check to resolve this issue and modifies the API's description to make it more straightforward. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-11-18NetworkPkg: Check for the max DHCP packet length before use it.Fu Siyuan
This patch updates the PXE and HTTP boot driver to drop the input DHCP packet if it exceed the maximum length. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-By: Wu Jiaxin <jiaxin.wu@intel.com>
2016-11-18MdeModulePkg: Check for the max DHCP packet length before use it.Fu Siyuan
This patch updates the PXE driver to drop the input DHCP packet if it exceed the maximum length. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-By: Wu Jiaxin <jiaxin.wu@intel.com>
2016-11-18MdePkg Base.h: Add add comments on __ prefix in enum VERIFY_UINTXX_ENUM_SIZELiming Gao
Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-18BaseTools gitignore: Ignore VS intermediate files *.obj and *.pdbLiming Gao
In V2, ignore .exe and .ilk files Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-11-18OvmfPkg: Add 4K PE alignment to enable SMM page level protection.Jiewen Yao
Tested boot with below configuration: IA32 IA32X64 X64 Tested boot with XD enabled/disabled. Requested-by: Laszlo Ersek <lersek@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-11-18UefiCpuPkg/PiSmmCpu: Check XdSupport before set NX.Jiewen Yao
When XD is not supported, the BIT63 is reserved. We should not set BIT63 in the page table. Test OVMF IA32/IA32X64 with XD enabled/disabled. Analyzed-by: Laszlo Ersek <lersek@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-11-18MdeModulePkg/BdsDxe: Avoid overwriting PlatformRecovery####Ruiyu Ni
Current implementation always creates PlatformRecovery0000 pointing to \EFI\BOOT\BOOT$(ARCH).efi but it may overwrite PlatformRecovery#### created before (maybe by a DXE driver). The patch only uses the smallest unused option number for the \EFI\BOOT\BOOT$(ARCH).efi PlatformRecovery#### to avoid overwriting already-created PlatformRecovery####. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jie Lin <jie.lin@intel.com> Reviewed-by: Sunny Wang <sunnywang@hpe.com>
2016-11-18MdeModulePkg/BdsDxe: Fix bug to run non-first PlatformRecovery####Ruiyu Ni
The implementation doesn't check the LoadOptions[Index].Status but only depends on the Status returned from EfiBootManagerProcessLoadOption(), which results only the first PlatformRecovery#### runs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jie Lin <jie.lin@intel.com> Reviewed-by: Sunny Wang <sunnywang@hpe.com>
2016-11-18MdeModulePkg/UefiBootManagerLib: Refine the debug messageRuiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Sunny Wang <sunnywang@hpe.com>
2016-11-18PcAtChipsetPkg/PcRtc: Handle NULL table entry in RSDT/XSDTRuiyu Ni
The ACPI code may reserve the first entry for a certain table (might be FACS) to help with OS compatible issues. We need to skip the NULL table entry in RSDT/XSDT. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-11-18UefiCpuPkg/SecCore: Correct print format for stack informationJeff Fan
v2: Per Laszlo and Andrew's comments at https://lists.01.org/pipermail/edk2-devel/2016-November/004759.html SecCoreData->StackBase is VOID * type. We should use %p to dump VOID * type. SecCoreData->StackSize is UINTN type, but %x only could print unsinged-int type. We will cast it to UINT32 firstly and then use %x to print it. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-11-18MdeModulePkg/PiSmmCpuDxeSmm: Check RegisterCpuInterruptHandler statusJeff Fan
Once platform selects the incorrect instance, the caller could know it from return status and ASSERT(). Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-18MdeModulePkg/CpuExceptionHanderLibNull: RegisterCpuInterruptHandler()Jeff Fan
Current CpuExceptionHanderLibNull instance returns EFI_SUCCESS for all three services. If platform does not want to hook the Exception vector for some modules (For example DxeCore), it could select this NULL instance in DSC file for those module. But some modules that want to consume RegisterCpuInterruptHandler() cannot use NULL instance. If platform does not select the correct library instance, it will does work. But the caller does not recognize it. This update is to return EFI_UNSUPPORTED on RegisterCpuInterruptHandler() in NULL instance instead of return EFI_SUCCESS. Once platform selects this NULL instance, the caller could know it from return status. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-11-17UefiCpuPkg/PiSmmCpuDxeSmm: Add volatile to mNumberToFinishMichael Kinney
Add volatile qualifier to mNumberToFinish to prevent GCC 5.4 compiler from optimizing away required logic in ACPI S3 resume. Cc: Liming Gao <liming.gao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17UefiCpuPkg/PiSmmCpuDxeSmm: TransferApToSafeState() use UINTN paramsMichael Kinney
Update TransferApToSafeState() use UINTN params to reduce the number of type casts required in these calls. Also change the NumberToFinish parameter from UINT32* to UINTN NumberToFinishAddress to resolve issues with conversion from a volatile pointer to a non-volatile pointer. The assembly code that receives the NumberToFinishAddress value must treat that memory location as a volatile to track the number of APs. Cc: Liming Gao <liming.gao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17IntelSiliconPkg: Add DxeSmbiosDataHobLibGiri P Mudusuru
Added NULL Library constructor DxeSmbiosDataHobLib which adds SMBIOS records from gIntelSmbiosDataHobGuid HOB to SMBIOS table using SMBIOS protocol. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-17MdePkg/BaseSynchronizationLib: Fix function names in function headersMichael Kinney
Some of the function names in function header comment blocks in assembly files do not match the symbol name in the assembly sources. Update function header comment blocks to match symbol name. Cc: Liming Gao <liming.gao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-11-17MdePkg/BaseSynchronizationLib: Add volatile Interlocked*() APIsMichael Kinney
The SpinLock functions in the SynchronicationLib use volatile parameters to keep compiler from optimizing these functions too much. The volatile keyword is missing from the Interlocked*() functions in this same library instance. Update the library instance to consistently use volatile on all functions in the SynchronizationLib class. Cc: Liming Gao <liming.gao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-11-17MdePkg/Include: Add volatile to SynchronizationLib parametersMichael Kinney
The SpinLock functions in the SynchronicationLib use volatile parameters to keep compiler from optimizing these functions too much. The volatile keyword is missing from the Interlocked*() functions in this same library class. Update the library class to consistently use volatile on all functions in this class. Cc: Liming Gao <liming.gao@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-11-18SignedCapsulePkg Universal: Init local variables before using themHao Wu
Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-18SignedCapsulePkg IniParsingLib: ASSERT to ensure 'Value' is not NULLHao Wu
Function GetStringFromDataFile() ensures its fourth (output) parameter will not be NULL when the return status is EFI_SUCCESS. This commit adds ASSERT as warnings for the case that will not happen. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-18BaseTools/BuildEnv: Do not modify the env 'PACKAGES_PATH' in BuildEnvHao Wu
https://bugzilla.tianocore.org/show_bug.cgi?id=236 The script 'BuildEnv' modifies the value of the environment variable 'PACKAGES_PATH' (line 44). The script will substitute the ':' symbol (separating multiple paths) with a space. This is not supposed to happen since users might later use 'PACKAGES_PATH' during the code-building process under a multiple-workspace scenario. Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-11-17CorebootPayloadPkg/CbSupportPei: Fix the memory map issueMaurice Ma
When coreboot reports memory range across 1MB, the current code cannot handle it properly. In this case the range should be adjusted to start from 1MB instead since the memory resource below 1MB has been preprocessed by CbSupportPei module. This patch fixed the coreboot + UEFI payload hang issue when running on QEMU due to incorrect memory map. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
2016-11-17CorebootPayloadPkg: Allow PciLib instance selectionMaurice Ma
On old platform without PCIe express support, the PciLib needs to be mapped to PciLibCf8 instance to make it work. On new platform with PCIe express support, the PciLib needs to be mapped to PciLibPciExpress to allow access to extended PCIe configuration space. This patch allows to select the PciLib instance between PciLibCf8 and PciLibPciExpress using the PCIE_BASE macro through build command line. Cc: Prince Agyeman <prince.agyeman@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Maurice Ma <maurice.ma@intel.com> Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
2016-11-17MdePkg/BaseMemoryLib: Fix VS2015 build errorMichael Kinney
https://bugzilla.tianocore.org/show_bug.cgi?id=237 Make the smallest change possible to workaround a VS2015 build error. The change is to the loop that handles the case where neither the source nor the destination are 64-bit or 32-bit aligned and the logic falls through to a loop that performs the copy as bytes. Only the loop that copies bytes backwards needs to be updated to avoid the VS2015 build error. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-11-17IntelSiliconPkg/IntelSiliconPkg.dec: drop bogus semicolon from GUID defLaszlo Ersek
The DEC spec doesn't allow the trailing semicolon: 2.6 [Guids] Usage GuidCName = {C Format Guid Value} # Comment Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-11-17UefiCpuPkg/MpInitLib: support 64-bit AP stack addressesLaszlo Ersek
The cached "CPU_INFO_IN_HOB.ApTopOfStack" field currently has type UINT32. This is not ideal because the AP stacks are located within "CpuMpData->Buffer", which is allocated with a plain AllocatePages() call in MpInitLibInitialize(): platform CpuMpPei included PEI RAM > 4GB result -------- ----------------- ------------- ------ Ia32 * n/a good Ia32X64 no n/a BAD Ia32X64 yes n/a good X64 no * BAD X64 yes no good X64 yes yes BAD - If we are on an Ia32X64 or X64 platform that does not include CpuMpPei, then CpuDxe cannot reuse the CPU_INFO_IN_HOB structures preallocated by CpuMpPei (through the CpuInitMpLib GUID HOB), and then AllocatePages() -- invoked first in 64-bit DXE -- could return an address outside of 32-bit address space. - If we are on an X64 platform where the permanent PEI RAM extends above the 32-bit address space, then the same issue can surface even if CpuMpPei is included: even the original allocation of the CPU_INFO_IN_HOB structures, by CpuMpPei, could be satisfied from above 4GB. The original "AP init" branch in "X64/MpFuncs.nasm" correctly considers a 64-bit stack start: the "MP_CPU_EXCHANGE_INFO.StackStart" field has type UINTN, and the code uses QWORD addition and movement to set RSP from it. Adapt the "GetApicId" branch of "X64/MpFuncs.nasm": - change the type of "CPU_INFO_IN_HOB.ApTopOfStack" to UINT64, - remove the explicit truncation to UINT32 in InitializeApData(), - update the "GetNextProcNumber" iteration size to the new size of "CPU_INFO_IN_HOB", - set RSP with a QWORD movement from "CPU_INFO_IN_HOB.ApTopOfStack". Because the same CPU_INFO_IN_HOB structure is used by "Ia32/MpFuncs.nasm", we have to update the "GetNextProcNumber" iteration size there as well. The ESP setting can be preserved as a DWORD movement from the original offset (decimal 12), since our integers are little endian. Cc: Jeff Fan <jeff.fan@intel.com> Fixes: 845c5be1fd9bf7edfac4a103dfab70829686978f Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17UefiCpuPkg/MpInitLib/X64/MpFuncs.nasm: fix fatal typoLaszlo Ersek
The recent patch "UefiCpuPkg/MpInitLib: Program AP stack in fixed address" inadvertently broke the first startup of APs during X64 PEI, because in the TestLock section of the code, it replaced the access to the NumApsExecuting counter with an access to the unrelated InitFlag field. Cc: Jeff Fan <jeff.fan@intel.com> Fixes: 845c5be1fd9bf7edfac4a103dfab70829686978f Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17UefiCpuPkg/MpInitLib/X64/MpFuncs.nasm: remove superfluous instructionLaszlo Ersek
At this point, ESI still has the value from EBX. Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17UefiCpuPkg/DxeMpInitLib: remove duplicate HobLib class dependencyLaszlo Ersek
Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17MdeModulePkg/Include: Add PiSmmMemoryAttributesTable.hJiewen Yao
This table describes the SMM memory attributes. The new GUID gEdkiiPiSmmMemoryAttributesTableGuid and its associated structure are based on the EFI_MEMORY_ATTRIBUTES_TABLE and GUID from the UEFI Specification. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> [lersek@redhat.com: update commit message as requested by Michael Kinney] Signed-off-by: Laszlo Ersek <lersek@redhat.com>
2016-11-17MdeModulePkg HiiDatabase: Remove extra memory initialization.Eric Dong
The memory will be set to background color after success allocate the data, so not need to call AllocateZeroPool. Related bugz: https://bugzilla.tianocore.org/show_bug.cgi?id=223 Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-11-17QuarkPlatformPkg/dsc: enable Smm paging protection.Jiewen Yao
Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Kelly Steele <kelly.steele@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2016-11-17UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection.Jiewen Yao
PiSmmCpuDxeSmm consumes SmmAttributesTable and setup page table: 1) Code region is marked as read-only and Data region is non-executable, if the PE image is 4K aligned. 2) Important data structure is set to RO, such as GDT/IDT. 3) SmmSaveState is set to non-executable, and SmmEntrypoint is set to read-only. 4) If static page is supported, page table is read-only. We use page table to protect other components, and itself. If we use dynamic paging, we can still provide *partial* protection. And hope page table is not modified by other components. The XD enabling code is moved to SmiEntry to let NX take effect. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2016-11-17UefiCpuPkg/dec: Add PcdCpuSmmStaticPageTable.Jiewen Yao
If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory. The page table size depend on 2 things: 1) The 1G paging capability. 2) The whole system memory/MMIO addressing capability. A) If the system only supports 2M paging, When the whole memory/MMIO is 32bit, we only need 1+1+4=6 pages for 4G. When the whole memory/MMIO is 39bit, we need 1+1+256 pages (~ 1M) When the whole memory/MMIO is 48bit, we need 1+256+256*256 pages (~ 257M) B) If the system supports 1G paging. When the whole memory/MMIO is 32bit, we only need 1+1+4=6 pages for 4G. (We still generate 2M page for maintenance consideration.) When the whole memory/MMIO is 39bit, we still need 6 pages. (We setup 1G paging for >1G.) When the whole memory/MMIO is 48bit, we need 1+256 pages (~ 1M). Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-01 09:27:14 +0000