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2015-05-05EmbeddedPkg/FdtPlatformDxe: Run FDT installation process at TPL_APPLICATION ↵Olivier Martin
level The current mechanism relies on EndOfDxe event that runs at TPL_CALLBACK level. It prevents some protocols to run as excepted because they require TPL_CALLBACK (eg: TFTP transfer). This change moves FDT installation in the driver entrypoint (that is called at TPL_APPLICATION level). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Ronald Cron <Ronald.Cron@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17298 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05ArmPkg/BdsLib: Exposed ShutdownUefiBootServices() in the BdsLib interfaceOlivier Martin
Other libraries/modules could use it (eg: EFI Shell command `runaxf`). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Ronald Cron <Ronald.Cron@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17297 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05ArmPlatformPkg/Scripts/Makefile: Added support to automatically update the FIPOlivier Martin
Some ARM development platforms use ARM Trusted Firmware to boot. ARM Trusted Firmware encapsulates UEFI into the FIP (Firmware Image Package) binary. This change allows to update the FIP binary after building UEFI. Example to build UEFI for FVP Base model: $ make -f ArmPlatformPkg/Scripts/Makefile \ EDK2_DSC=ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.dsc \ EDK2_ARCH=AARCH64 EDK2_TOOLCHAIN=GCC49 \ FIP_BIN=~/arm-trusted-firmware/build/fvp/release/fip.bin Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Ronald Cron <Ronald.Cron@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17296 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05MdePkg: Add UEFI2.5 USB Function I/O protocol definitionsFeng Tian
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17295 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05MdePkg: Add UEFI2.5 Smart Card Edge protocol definitionsFeng Tian
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17294 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05MdePkg: Add UEFI2.5 Smart Card Reader protocol definitionsFeng Tian
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17293 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05MdePkg: Add UEFI2.5 Inline Cryptographic Interface definitionFeng Tian
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17292 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05Fixed SOURCE_DEBUG_ENABLE build error. Shifei Lu
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com> Reviewed-by: David Wei <david.wei@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17291 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05IntelFrameworkModulePkg: Modify IsaSerialDxe to follow driver rulesHao Wu
IsaSerialDxe creates child handles and wishes to retrieve the name for those child controllers. However, in the IsaSerialComponentNameGetControllerName() function, it directly return EFI_UNSUPPORTED when ChildHandle != NULL. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17289 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05Add UEFI2.5 HASH protocol implementation.Yao, Jiewen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Long, Qin" <Qin.Long@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17288 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-05Add UEFI2.5 HASH protocol definition.Yao, Jiewen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Long, Qin" <Qin.Long@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17287 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-04MdeModulePkg/NvmExpressDxe: Expose EFI_NVM_EXPRESS_PASS_THRU protocolFeng Tian
This patch produces a EFI_NVM_EXPRESS_PASS_THRU protocol instance on device handle to provide upper user a way to send cmd to NVMe device. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17286 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-04MdePkg: Add UEFI2.5 EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL definitionsFeng Tian
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17285 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-01enhancement to tool to generate the comments along with offsets in the .h file.Mudusuru, Giri P
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17282 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-01Fix FSP GCC error on FspApiCallingCheck().Yao, Jiewen
Add comment for ASM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17281 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-30MdePkg/BaseLib: Preserve EBX register and fix stack offset to LinearAddress ↵Michael Kinney
in AsmFlushCacheLine() The value of EBX must be preserved to follow IA32 cdecl calling convention in the assembly implementation of AsmFlushCacheLine(). The CPUID instruction modifies the EBX register. The EBX register value is saved onto the stack before CPUID and restored from the stack after CPUID. The update to the inline assembly implementation of AsmFlushCacheLine() changed the location of the LinearAddress parameter value on the stack. The hardcoded lookup using [esp + 4] is not correct. Use the parameter name LinearAddress instead of the hard coded [esp + 4] stack location to prevent this issue from occurring again if there are changes to the inline assembly in the future. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17279 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-30Add IPV6 support from UNDIYe Ting
Add new information block ‘IPV6 support from UNDI’ in AIP protocol and provide sample implementation in UNDI driver. Update PXE driver to get ‘Ipv6Available’ of PXE BC Mode data from UNDI driver, if unsupported then not to start PXE over IPv6 path. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ye Ting <ting.ye@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17275 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-30Add FSP_FSPP_SIGNATURE in 1.1.Yao, Jiewen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17273 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-30Clean update API name for ASM function.Yao, Jiewen
Add FSP_INFO_HEADER_SIGNATURE and FSP_INFO_EXTENDED_HEADER_SIGNATURE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17271 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29MdeModulePkg: Update comments for PcdMemoryProfileMemoryTypeLiming Gao
PcdMemoryProfileMemoryType also includes EfiPersistentMemory. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17267 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29ShellPkg: Update CopyRight to 2015Liming Gao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17266 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29Remove duplicate DAD entry in IP6 driver to fix DAD fail issue.Fu Siyuan
The IP6 driver may create duplicate IP6_DAD_ENTRY in DupAddrDetectList in some situation like: 1. Address policy switch but not clear the delay node list, OR 2. Set manual address repeatedly before the previous DAD is finished. The NS sent out by duplicate DAD entry will mix up with the loop back multicast packet, result in DAD fail. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com> Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17263 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29MdeModulePkg: PI1.4 DxeCore GetMemoryMap() updateLiming Gao
PI1.4: Updates DxeCore to add all EfiGcdMemoryTypeReserved memory into UEFI memory map. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17253 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29EdkCompatibilityPkg: Add PersistentMemory definitionLiming Gao
Include this definition to make sure EfiMaxMemoryType be same value in EDKII and ECP code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17252 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29Add dual FSP binaries support.Ma, Maurice
There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version) TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17249 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29Add dual FSP binaries support.Ma, Maurice
There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version) TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version. Also update FSP specification version to v1.1. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17248 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29MdeModulePkg: fix some issues in ScsiDisk to co-work with UFS stackFeng Tian
The changes in ScsiDisk include: 1. Add UFS disk info support. 2. Remove the wrong block size calculation. 3. Get sense data for TEST_UNIT_READY cmd immediately rather than sending a REQUEST_SENSE cmd again. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17247 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29MdeModulePkg: Add UFS (Universal Flash Storage) StackFeng Tian
It includes 4 drivers: 1. UfsPassThruDxe, which is a UEFI driver and consumes EFI_UFS_HOST_CONTROLLER_PROTOCOL and produces EFI_EXT_SCSI_PASS_THRU_PROTOCOL 2. UfsPciHcDxe, which is specific for pci-based UFS HC implementation and is a UEFI driver to produce EFI_UFS_HOST_CONTROLLER_PROTOCOL. 3. UfsBlockIoPei, which is a PEI driver and consumes EFI_UFS_HOST_CONTROLLER_PPI and produces EFI_PEI_VIRTUAL_BLOCK_IO_PPI. 4. UfsPciHcPei, which is specific for pci-based UFS HC implementation and is a PEI driver to produce EFI_UFS_HOST_CONTROLLER_PPI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17246 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29MdePkg: Add UFS (Universal Flash Storage) related definitionsFeng Tian
These definitions are defined in UEFI2.5/PI1.4 spec. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17245 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29IntelFrameworkModulePkg: Add UEFI2.5 PersistentMemory support in LegacyBiosLiming Gao
LegacyBiosDxe converts EfiPersistentMemory to E820 EfiAddressRangePersistentMemory. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17244 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29ShellPkg: Update Shell MemMap command to show PersistentMemory rangeLiming Gao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17243 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29MdeModulePkg: Add support for UEFI2.5 and PI1.4 PersistentMemory featureLiming Gao
Update DxeCore to collect PersistentMemory resource and report them in EFI memory map. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17242 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29MdePkg: Add UEFI2.5 and PI1.4 PersistentMemory definitionLiming Gao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17241 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-28MdePkg: Trim trailing whitespaces for ESRT related filesHao Wu
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17236 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-28MdePkg: Add ESRT Interface DefinitionsHao Wu
Add EFI System Resource Table (ESRT) interface (API only). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Chao Zhang <chao.b.zhang@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17235 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-28MdePkg: Add the header file for UEFI PI Multi-processor PPIHao Wu
The MP Services PPI is installed by some platform or chipset-specific PEIM that abstracts handling multiprocessor support. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17234 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-28MdePkg: Add PI 1.4 Graphics HOB and PPI header filesHao Wu
The PeiGraphicsPpi is the main interface exposed by the Graphics PEIM to be used by the other firmware modules. When graphics capability is included in PEI, it produces a EFI_PEI_GRAPHICS_INFO_HOB which provides information about the graphics mode and the framebuffer. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17233 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-28Move microcode to offset 0 of BIOS region.Mang Guo
Move microcode, whose address is fixed by SEC binary, to offset 0 of BIOS region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mang Guo <mang.guo@intel.com> Reviewed-by: David Wei <david.wei@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17224 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-28Replace SetPower2 by EDKII baselib - GetPowerOfTwo64.Yao, Jiewen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Ma, Maurice" <Maurice.Ma@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17222 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27UefiCpuPkg/CpuExceptionHandlerLib: Support IA32 processors without DE or ↵Michael Kinney
FXSAVE/FXRESTOR Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions. Do not enable those features in CR4 if they are not supported. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17221 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27SourceLevelDebugPkg/DebugAgent: Support IA32 processors without DE or ↵Michael Kinney
FXSAVE/FXRESTOR Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions. Do not enable those features in CR4 if they are not supported. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17220 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27SourceLevelDebugPkg/PeCoffExtraActionLibDebug: Support IA32 processors ↵Michael Kinney
without debug extensions Use CPUID Leaf 01 to detect support for debug extensions. Force use of software breakpoints if debug extensions are not supported. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17219 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27MdePkg/DebugAgent: Support IA32 processors without MSR_IA32_APIC_BASE_ADDRESSMichael Kinney
Avoid use of Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS) if there is only 1 CPU present. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17218 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27MdePkg/BaseXApicX2ApicLib: Support IA32 processors without ↵Michael Kinney
MSR_IA32_APIC_BASE_ADDRESS Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS). If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17217 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27MdePkg/BaseXApicLib: Support IA32 processors without MSR_IA32_APIC_BASE_ADDRESSMichael Kinney
Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS). If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17216 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27MdePkg/BaseSerialPortLib16550: Support UARTs with a register stride greater ↵Michael Kinney
than 1 byte. Add stride PCD to MdeModulePkg to support 16550 UARTs with a register stride that is not 1 byte. The default value is 1 byte. Quark SoC uses a stride of 4 bytes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17215 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27MdePkg/BaseMemoryLibRepStr: Support IA32 processors without CMOVxMichael Kinney
Remove use of CMOVx instruction from IA32 assembly files in BaseMemoryLibRepStr. This matches compiler flags for all supported C compilers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17214 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27MdePkg/BaseLib: Support IA32 processors without CMOVxMichael Kinney
Remove use of CMOVx instruction from IA32 assembly files in BaseLib. This matches compiler flags for all supported C compilers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17213 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27MdePkg/BaseLib: Support IA32 processors without CLFLUSHMichael Kinney
Use CPUID Leaf 01 to detect support for CLFLUSH instruction. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17212 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-27MdePkg/BaseCacheMaintenanceLib: Support IA32 processors without CLFLUSHMichael Kinney
Use CPUID Leaf 01 to detect support for CLFLUSH instruction. If CLFLUSH is supported, use CPUID to determine the cache line size to use with CLFLUSH. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17211 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 13:39:18 +0000