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The MP Services PPI is installed by some platform or chipset-specific PEIM
that abstracts handling multiprocessor support.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17234 6f19259b-4bc3-4df7-8a09-765794883524
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The PeiGraphicsPpi is the main interface exposed by the Graphics PEIM to
be used by the other firmware modules.
When graphics capability is included in PEI, it produces a
EFI_PEI_GRAPHICS_INFO_HOB which provides information about the graphics
mode and the framebuffer.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17233 6f19259b-4bc3-4df7-8a09-765794883524
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Move microcode, whose address is fixed by SEC binary, to offset 0 of BIOS region.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mang Guo <mang.guo@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17224 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Ma, Maurice" <Maurice.Ma@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17222 6f19259b-4bc3-4df7-8a09-765794883524
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FXSAVE/FXRESTOR
Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions.
Do not enable those features in CR4 if they are not supported.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17221 6f19259b-4bc3-4df7-8a09-765794883524
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FXSAVE/FXRESTOR
Use CPUID Leaf 01 to detect support for debug extensions and FXSAVE/FXRESTOR instructions.
Do not enable those features in CR4 if they are not supported.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17220 6f19259b-4bc3-4df7-8a09-765794883524
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without debug extensions
Use CPUID Leaf 01 to detect support for debug extensions.
Force use of software breakpoints if debug extensions are not supported.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17219 6f19259b-4bc3-4df7-8a09-765794883524
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Avoid use of Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS) if there is only 1 CPU present.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17218 6f19259b-4bc3-4df7-8a09-765794883524
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MSR_IA32_APIC_BASE_ADDRESS
Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS).
If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17217 6f19259b-4bc3-4df7-8a09-765794883524
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Use Family from CPUID 01 to detect support for the Local APIC Base Address MSR (MSR_IA32_APIC_BASE_ADDRESS).
If this MSR is not supported, then use Local APIC Base Address from the PCD PcdCpuLocalApicBaseAddress.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17216 6f19259b-4bc3-4df7-8a09-765794883524
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than 1 byte.
Add stride PCD to MdeModulePkg to support 16550 UARTs with a register stride that is not 1 byte.
The default value is 1 byte.
Quark SoC uses a stride of 4 bytes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17215 6f19259b-4bc3-4df7-8a09-765794883524
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Remove use of CMOVx instruction from IA32 assembly files in BaseMemoryLibRepStr.
This matches compiler flags for all supported C compilers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17214 6f19259b-4bc3-4df7-8a09-765794883524
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Remove use of CMOVx instruction from IA32 assembly files in BaseLib.
This matches compiler flags for all supported C compilers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17213 6f19259b-4bc3-4df7-8a09-765794883524
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Use CPUID Leaf 01 to detect support for CLFLUSH instruction.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17212 6f19259b-4bc3-4df7-8a09-765794883524
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Use CPUID Leaf 01 to detect support for CLFLUSH instruction.
If CLFLUSH is supported, use CPUID to determine the cache line size to use with CLFLUSH.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17211 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17210 6f19259b-4bc3-4df7-8a09-765794883524
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Add missing parentheses due to typo.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17209 6f19259b-4bc3-4df7-8a09-765794883524
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The number of the Prp lists and the number of the entries in last Prp list may be calculated wrongly.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Baban Devkate <baban.devkate@seagate.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17208 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Baraneedharan Anbazhagan <anbazhagan@hp.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17207 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17206 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Baraneedharan Anbazhagan <anbazhagan@hp.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17205 6f19259b-4bc3-4df7-8a09-765794883524
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Clear EFLAGS.IF before executing Stepping command and save original
value in DEBUG_AGENT_FLAG. It could avoid pending interrupt issued
during executing Stepping command. Restore EFLAGS.IF after Stepping
command execution finished.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17204 6f19259b-4bc3-4df7-8a09-765794883524
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Add InterruptFlag field in DEBUG_AGENT_FLAG. This field is used to
save/restore EFLAGS.IF across Stepping command execution.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17203 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Baraneedharan Anbazhagan <anbazhagan@hp.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17202 6f19259b-4bc3-4df7-8a09-765794883524
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The run time service 'QueryVariableInfo' is not proper to be used to get the variable name size. This patch refine the logic about allocating memory for variable name and data.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17201 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17200 6f19259b-4bc3-4df7-8a09-765794883524
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commands installed
The list of handles needs to be freed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17199 6f19259b-4bc3-4df7-8a09-765794883524
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Add a comment for GetHandleListByProtocol and GetHandleListByProtocolList to tell the caller they are responsible for freeing the returned memory.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17198 6f19259b-4bc3-4df7-8a09-765794883524
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-- Add BootLoaderTolumSize support
-- Fix LibraryClasses declaration in DEC file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17197 6f19259b-4bc3-4df7-8a09-765794883524
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-- Add BootLoaderTolumSize support
-- Extend FspApiCallingCheck with ApiParam for BootLoaderTolumSize
-- Rename all Bootloader to BootLoader as official name
-- Rename Ucode to Microcode
-- Remove FspSelfCheck API, because it is merged into SecPlatformInit
-- Add GetFspVpdDataPointer() in FspCommonLib.h
-- Document FspSecPlatformLib.h
-- Reorg FSP_PLAT_DATA data structure to let it match FSP spec.
-- Move helper function in FspSecCore to reduce platform enabling effort
-- Fix LibraryClasses declaration in DEC file.
-- Enhance PatchFv to check if it is valid FSP bin.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com>
Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17196 6f19259b-4bc3-4df7-8a09-765794883524
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BlockIo protocol instance.
Media->IoAlign field of BlockIo protocol instance installed by this driver should be set to the value of ScsiIo->IoAlign.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17195 6f19259b-4bc3-4df7-8a09-765794883524
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Some protocols still had this at the end of protocol name. remove to standardize.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Tapan Shah <tapandshah@hp.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17194 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hot Tian <hot.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17193 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Liming Gao" <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17192 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
Reviewed-by: "Liming Gao" <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17191 6f19259b-4bc3-4df7-8a09-765794883524
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It will avoid that exception issued by Debug Agent itself was skipped.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17190 6f19259b-4bc3-4df7-8a09-765794883524
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for QuestionConfig part.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17189 6f19259b-4bc3-4df7-8a09-765794883524
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and update it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17188 6f19259b-4bc3-4df7-8a09-765794883524
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Configure .gitignore file to ignore Bin/Win32 and Lib directory.
Those two directories are generated when BaseTools are compiled at Windows.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17187 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17186 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qiu Shumin <shumin.qiu@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17185 6f19259b-4bc3-4df7-8a09-765794883524
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If this function fails in release build then the error was
not handled and SourceHandle was not valid.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17184 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17183 6f19259b-4bc3-4df7-8a09-765794883524
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ACPI_DISPLAY_ADR().
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Tested-by: Olivier Martin <Olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17182 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shumin Qiu <shumin.qiu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17181 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shumin Qiu <shumin.qiu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17180 6f19259b-4bc3-4df7-8a09-765794883524
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- SVN r14866:
MdePkg and MdeModulePkg Pcd: Add the new EFI_GET_PCD_INFO_PROTOCOL and
EFI_GET_PCD_INFO_PPI support for PI 1.2.1 compliance.
added the "DataBase" local variable to PcdPeimInit(), and both set it and
used it.
- SVN r14869:
MdeModulePkg and Nt32Pkg Pcd: Add the new EFI_GET_PCD_INFO_PROTOCOL and
EFI_GET_PCD_INFO_PPI support for PI 1.2.1 compliance.
changed the PcdPeimInit() function, but "DataBase" remained both set and
used.
- SVN r17173:
MdeModulePkg Pcd: Check the input SkuId in SetSku()
changed the function again; and this time "DataBase" became
set-but-unused. It triggers the following build error, when building
ArmVirtualizationQemu.dsc with gcc-4.8:
MdeModulePkg/Universal/PCD/Pei/Pcd.c:150:21: error: variable 'DataBase'
set but not used [-Werror=unused-but-set-variable]
PEI_PCD_DATABASE *DataBase;
^
cc1: all warnings being treated as errors
Fix the error by removing the DataBase variable, restoring the pre-r14866
state locally, when the BuildPcdDatabase() function was called, but its
return value was thrown away.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17179 6f19259b-4bc3-4df7-8a09-765794883524
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In order to prevent memory corruption issues caused by the fact that,
under virtualization, the guest is incoherent with the hypervisor's view
of memory until it enables its caches and MMU, this patch reshuffles the
init sequence so that the Xen shared memory regions are not touched
before the caches and MMU are enabled.
In addition, the loaded image itself is invalidated by virtual address,
to ensure that any runtime changes (such as the applied relocations) will
not suddenly become invisible once we turn the caches on.
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17178 6f19259b-4bc3-4df7-8a09-765794883524
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This updates ArmVirtualizationMemoryInitPeiLib so that the PEI memory
region, i.e., the region that is used both before and after the MMU
and caches are enabled, is invalidated by virtual address before
enabling the MMU.
This prevents issues where data we modified with the caches and MMU
off may be shadowed by clean cachelines in system caches or in lower
level caches on other CPUs, resulting in the this data to become
invisible once we turn the MMU and caches on.
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17177 6f19259b-4bc3-4df7-8a09-765794883524
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This removes the range size threshold for virtual address based cache
maintenance instructions that operate on VA ranges to be 'promoted' to
use set/way instructions.
Doing so is unsafe: set/way operations are fundamentally different
from VA operations, and really only suitable for cleaning or invalidating
a cache when turning it on or off.
To quote the ARM ARM (DDI0487A_d G3.4):
"""
Since the set/way instructions are performed only locally, there is no
guarantee of the atomicity of cache maintenance between different PEs,
even if those different PEs are each performing the same cache maintenance
instructions at the same time. Since any cacheable line can be allocated
into the cache at any time, it is possible for [a] cache line to migrate
from an entry in the cache of one PE to the cache of a different PE in a
manner that the cache line avoids being affected by set/way based cache
maintenance. Therefore, ARM strongly discourages the use of set/way
instructions to manage coherency in coherent systems.
"""
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17176 6f19259b-4bc3-4df7-8a09-765794883524
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