summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2016-03-13UefiCpuPkg/Include: Add Core Solo/Duo MSR include fileMichael Kinney
Add Core Solo/Duo MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium 4 MSR include fileMichael Kinney
Add Pentium 4 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon Phi MSR include fileMichael Kinney
Add Xeon Phi MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Skylake MSR include fileMichael Kinney
Add Skylake MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon Processor D MSR include fileMichael Kinney
Add Xeon Processor D MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Broadwell MSR include fileMichael Kinney
Add Broadwell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell-E MSR include fileMichael Kinney
Add Haswell-E MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell MSR include fileMichael Kinney
Add Haswell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Ivy Bridge MSR include fileMichael Kinney
Add Ivy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Sandy Bridge MSR include fileMichael Kinney
Add Sandy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon E7 MSR include fileMichael Kinney
Add Xeon E7 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon 5600 MSR include fileMichael Kinney
Add Xeon 5600 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Nehalem MSR include fileMichael Kinney
Add Nehalem MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Silvermont MSR include fileMichael Kinney
Add Silvermont MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Atom MSR include fileMichael Kinney
Add Atom MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Core 2 MSR include fileMichael Kinney
Add Core 2 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Architectural MSR include fileMichael Kinney
Add Architectural MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-11CryptoPkg/OpensslLib: Upgrade OpenSSL version to 1.0.2gQin Long
OpenSSL 1.0.2g was released with several severity fixes at 01-Mar-2016(https://www.openssl.org/news/secadv/20160301.txt). Upgrade the supported OpenSSL version in CryptoPkg/OpensslLib to catch the latest release 1.0.2g. (NOTE: RT4175 from David Woodhouse was included in 1.0.2g. The new-generated patch will remove this part. And the line endings were still kept as before in this version for consistency) CC: Ting Ye <ting.ye@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Qin Long <qin.long@intel.com> Reviewed-by: David Woodhouse <David.Woodhouse@intel.com>
2016-03-11CryptoPkg/OpensslLib: Convert saved opensslconf.h to DOS line endingsDavid Woodhouse
Until we fix the git repository to store line endings properly and then just check them out in the appropriate form for the platform, let's make process_files.sh convert the opensslconf.h to DOS line endings when it creates it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Reviewed-by: Qin Long <qin.long@intel.com>
2016-03-11ArmVirtPkg/VirtFdtDxe: set /chosen/linux,pci-probe-only to 1 in DTBArd Biesheuvel
Unlike Linux on x86, which typically honors the PCI configuration performed by the firmware, Linux on ARM assumes that the PCI subsystem needs to be configured from scratch. This is not entirely unreasonable given the historical background of embedded systems using very basic bootloaders, but is no longer tenable with Linux on arm64 moving to UEFI and ACPI in the server space. For this reason, PCI support in the arm64 kernel running under ACPI is likely to move to the x86 model of honoring the PCI configuration done by the firmware. So let's align with that in our DT based configuration as well, and set the /chosen/linux,pci-probe-only property to 1 in the Device Tree before we hand it to the OS. In case we are exposing an emulated VGA PCI device to the guest, which may subsequently get exposed via the Graphics Output protocol and driven as an efifb by the OS, this ensures the PCI resource allocations for the framebuffer are not overridden, since that would cause the framebuffer to stop working. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-03-11SecurityPkg: Clear LocalAuthSession content after use.Jiewen Yao
Some commands in DxeTcg2PhysicalPresenceLib accept AuthSession as input parameter and copy to local command buffer. After use, this AuthSession content should be zeroed, because there might be some secrete there. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com>
2016-03-11SecurityPkg: Add Tpm2 prefix to lib to avoid conflict.Jiewen Yao
Tpm2Ptp.c is library, but it miss Tpm2 prefix for IsPtpPresence() and GetPtpInterface(). There might be risk as name symbol conflict. This patch adds Tpm2 prefix for them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com> Tested-by: "Wu, Hao A" <hao.a.wu@intel.com>
2016-03-11SecurityPkg: Fix Tcg2 SubmitRequestToPreOSFunction() fail in second times.Jiewen Yao
Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction() has check if current request is same as previous. But it forget check RequestParameter, which causes second request fail to process, if RequestParameter is different. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com>
2016-03-11BaseTools: update the mail address for stack trace infoYonghong Zhu
Update the mail address from edk2-devel@lists.sourceforge.net to edk2-devel@lists.01.org. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Andrew Fish <afish@apple.com>
2016-03-11SecurityPkg: SecureBootConfigDxe: Update coding styleZhang, Chao B
Update code to follow EDK2 coding style. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chao Zhang<chao.b.zhang@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
2016-03-11NetworkPkg: Refine the code of shell app under networkPkg.Zhang, Lubo
refine the code of ifconfig6 and ping6 application. Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Wu Jiaxin <jiaxin.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Zhang Lubo <lubo.zhang@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
2016-03-11MdeModulePkg: Add missing pcd description to MdeModulePkg.uniDandan Bi
Since PcdHiiOsRuntimeSupport has added in the MdeModulePkg.dec file, now add the usage information in the uni file. Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
2016-03-11NetworkPkg: Fix IpsecConfig GCC build failure issueJiaxin Wu
This issue is caused by the string token ID for help message, which is defined in the internal head file. This head file is used for reference more than once. So, multiple definition for the string token ID error will be enrolled. Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Zhang Lubo <lubo.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Zhang, Lubo <lubo.zhang@intel.com>
2016-03-10OvmfPkg: PciHostBridgeLib: permit access to the full extended config spaceLaszlo Ersek
By now OVMF makes MdeModulePkg/Bus/Pci/PciHostBridgeDxe go through MMCONFIG (when running on Q35). Enable the driver to address each B/D/F's config space up to and including offset 0xFFF. Cc: Gabriel Somlo <somlo@cmu.edu> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Michał Zegan <webczat_200@poczta.onet.pl> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Michał Zegan <webczat_200@poczta.onet.pl>
2016-03-10OvmfPkg: match PCI config access to machine type (if not USE_OLD_PCI_HOST)Laszlo Ersek
If USE_OLD_PCI_HOST is FALSE, then we switch all executable module types supported by DxePciLibI440FxQ35 to the following library instance stack: BasePciSegmentLibPci [class: PciSegmentLib] DxePciLibI440FxQ35 [class: PciLib] BasePciCf8Lib [class: PciCf8Lib] BasePciExpressLib [class: PciExpressLib] Every module will select 0xCF8 vs. ECAM based on the OVMF platform type (i440fx or Q35). Notably, MdeModulePkg/Bus/Pci/PciHostBridgeDxe is among the affected drivers. The BasePciExpressLib instance is where the PcdPciExpressBaseAddress PCD fills its original role. Cc: Gabriel Somlo <somlo@cmu.edu> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Michał Zegan <webczat_200@poczta.onet.pl> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Michał Zegan <webczat_200@poczta.onet.pl>
2016-03-10OvmfPkg: add DxePciLibI440FxQ35Laszlo Ersek
This library is a trivial unification of the following two PciLib instances (and the result is easily diffable against each): - MdePkg/Library/BasePciLibCf8 - MdePkg/Library/BasePciLibPciExpress The PCI config access method is determined in the constructor function, from the dynamic PCD "PcdOvmfHostBridgePciDevId" that is set by PlatformPei. The library instance is usable in DXE phase or later modules: the PciLib instances being unified have no firmware phase / client module type restrictions, and here the only PCD access is made in the constructor function. That is, even before a given client executable's entry point is invoked. The library instance depends on PlatformPei both for setting the PCD mentioned above, and also for enabling MMCONFIG on Q35. PEI and earlier phase modules are not expected to need extended config access even on Q35. Cc: Gabriel Somlo <somlo@cmu.edu> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Michał Zegan <webczat_200@poczta.onet.pl> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Michał Zegan <webczat_200@poczta.onet.pl>
2016-03-10OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG / ECAM) on Q35Laszlo Ersek
The comments in the code should speak for themselves; here we note only two facts: - The PCI config space writes (to the PCIEXBAR register) are performed using the 0xCF8 / 0xCFC IO ports, by virtue of PciLib being resolved to BasePciLibCf8. (This library resolution will permanently remain in place for the PEI phase.) - Since PCIEXBAR counts as a chipset register, it is the responsibility of the firmware to reprogram it at S3 resume. Therefore PciExBarInitialization() is called regardless of the boot path. (Marcel recently posted patches for SeaBIOS that implement this.) This patch suffices to enable PCIEXBAR (and the dependent ACPI table generation in QEMU), for the sake of "PCIeHotplug" in the Linux guest: ACPI: MCFG 0x000000007E17F000 00003C (v01 BOCHS BXPCMCFG 00000001 BXPC 00000001) PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0x80000000-0x8fffffff] (base 0x80000000) PCI: MMCONFIG at [mem 0x80000000-0x8fffffff] reserved in E820 acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] In the following patches, we'll equip the core PCI host bridge / root bridge driver and the rest of DXE as well to utilize ECAM on Q35. Cc: Gabriel Somlo <somlo@cmu.edu> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Michał Zegan <webczat_200@poczta.onet.pl> Ref: https://github.com/tianocore/edk2/issues/32 Ref: http://thread.gmane.org/gmane.comp.bios.coreboot.seabios/10548 Suggested-by: Marcel Apfelbaum <marcel@redhat.com> Reported-by: Michał Zegan <webczat_200@poczta.onet.pl> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Tested-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Michał Zegan <webczat_200@poczta.onet.pl> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-10OvmfPkg: PlatformPei: lower the 32-bit PCI MMIO base to 2GB on Q35Laszlo Ersek
Gerd has advised us that long term support Q35 machine types have no low RAM above 2GB, hence we should utilize the [2GB, 3GB) gap -- that we currently leave unused -- for MMIO. (Plus, later in this series, for the PCIEXBAR too.) Cc: Gabriel Somlo <somlo@cmu.edu> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Michał Zegan <webczat_200@poczta.onet.pl> Ref: https://github.com/tianocore/edk2/issues/32 Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/8707/focus=8817 Suggested-by: Gerd Hoffmann <kraxel@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Michał Zegan <webczat_200@poczta.onet.pl> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-10OvmfPkg: IndustryStandard/Q35MchIch9.h: add PCIEXBAR macrosLaszlo Ersek
Section 5.1.16 ("PCIEXBAR -- PCI Express Register Range Base Address") in Intel document #316966-002 (already referenced near the top of this header file) describes the Q35 DRAM Controller register that configures the memory-mapped PCI config space (also known as MMCONFIG, and ECAM / Enhanced Configuration Access Method). In this patch we add the macros we'll need later. We'll only support the 256 MB memory-mapped config space -- enough for buses [0, 255]. Cc: Gabriel Somlo <somlo@cmu.edu> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Michał Zegan <webczat_200@poczta.onet.pl> Ref: https://github.com/tianocore/edk2/issues/32 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Tested-by: Gabriel Somlo <somlo@cmu.edu> Tested-by: Michał Zegan <webczat_200@poczta.onet.pl>
2016-03-10BaseTools ConvertMasmToNasm: Support Python 3Jordan Justen
The script is updated to support both python 2.7 and python 3. v2: * Use io.open() rather than open() (Jaben) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Erik Bjorge <erik.c.bjorge@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
2016-03-10BaseTools ConvertMasmToNasm: Fix exception when no arguments are givenJordan Justen
Convert to use the argparse library rather than optparse. As part of the conversion, the script will now give an error message if no arguments are given. Previously the script would give an exception when no arguments were given. Fixes: https://github.com/tianocore/edk2/issues/65 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-10BaseTools ConvertMasmToNasm: Fix running script outside of a git treeJordan Justen
The script previously would hit an exception if it was run outside of a git tree. The exception looked like: edk2/BaseTools/Scripts/ConvertMasmToNasm.py Version 0.01 Traceback (most recent call last): File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 986, in <module> ConvertAsmApp() File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 984, in __init__ ConvertAsmFile(src, dst, self) File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 209, in __init__ CommonUtils.__init__(self, clone) File "edk2/BaseTools/Scripts/ConvertMasmToNasm.py", line 69, in __init__ self.gitemail = clone.gitemail AttributeError: ConvertAsmApp instance has no attribute 'gitemail' Fixes: https://github.com/tianocore/edk2/issues/63 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-10BaseTools: Update ARM/AArch64 GenFv vector processing for encapsulated FVsCohen, Eugene
Instead of only handling SEC Core or PEI Core instances in the outer FV, the GenFv tool will now recurse into FV image FFS files to look for instances in encapsulated FVs so the vector area can be updated appropriately. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-10BaseTools: report warning if VOID* PCD with {} value is not 8-byte alignedYonghong Zhu
For VOID* Pcd with {} value, If platform developer wants to put in a specific hex offset value that is not 8-byte aligned for VOID * then we allow it with a warning message. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-10BaseTools: Change source files to DOS format.Liming Gao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-03-10NetworkPkg: Use the New Functions from HttpLibGhazi Belaam
After submitting changes for HttpLib, other modules should be able to use those functions 1 remove the private function and their calls 2 update it with the functions from httpLib Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ghazi Belaam <Ghazi.belaam@hpe.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Samer EL-Haj-Mahmoud <elhaj@hpe.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
2016-03-10ModulePkg/DxeHttpLib: Adding Functions to HttpLibGhazi Belaam
There some usefull functions in edk2 private modules that could be used, so we added them to the httpLib Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ghazi Belaam <Ghazi.belaam@hpe.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Samer EL-Haj-Mahmoud <elhaj@hpe.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
2016-03-10NetworkPkg: Convert UNI file to UTF8 format.Fu Siyuan
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
2016-03-10UefiCpuPkg/Application/Cpuid: Remove unnecessary code checkJeff Fan
gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> UefiCpuPkg/Application/Cpuid: Remove unnecessary code check gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> UefiCpuPkg/Application/Cpuid: Remove unnecessary code check gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-10UefiCpuPkg/Application/Cpuid: Add check for gMaximumBasicFunctionJeff Fan
Add check for gMaximumBasicFunction in CpuidVersionInfo () back. Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-09ShellPkg: Use DOS format end of line.Qiu Shumin
Use DOS format end of line(CR, LF). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
2016-03-09BaseTools: Add Multiple Workspaces support for custom Makefiles.Marvin Haeuser
This patch makes sure the MODULE_DIR variable points to the correct location when multiple workspaces are used. Currently, it is always prefixed with $(WORKSPACE), which only works as long as the package is in the Workspace. Code modules were not effected because the required paths were valid, but for custom Makefiles, the MODULE_DIR variable is used. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marvin Haeuser <Marvin.Haeuser@outlook.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-03-08MdeModulePkg: Increase the maximum number of PEI performance log entriesCinnamon Shia
The maximum number of PEI performance log entries is 255. Add a new PCD, PcdMaxPeiPerformanceLogEntries16, to increase the maximum number of PEI performance log entries. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Cinnamon Shia <cinnamon.shia@hpe.com> Reviewed-by: Samer EL-Haj-Mahmoud <elhaj@hpe.com> Reviewed-by: Joseph Shifflett <joseph.shifflett@hpe.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-03-08OvmfPkg: Enable Network2 Shell Commands for IPv6Gary Lin
Enable the network2 commands when NETWORK_IP6_ENABLE is TRUE, so we would have Ping6 and Ifconfig6. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Ching-Pang Lin <glin@suse.com> [lersek@redhat.com: added the word "Shell" to the subject] Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-03-08ShellPkg/UefiDpLib: Support execution breakCinnamon Shia
Support UEFI shell execution break. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Cinnamon Shia <cinnamon.shia@hpe.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Samer EL-Haj-Mahmoud <elhaj@hpe.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-01 02:43:38 +0000