summaryrefslogtreecommitdiff
path: root/ArmPkg/Drivers/CpuDxe
AgeCommit message (Collapse)Author
2017-09-05Remove core packages since we can get them from edk2 repositoryGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2015-07-06ArmPkg/CpuDxe: Fixed AArch64 MMUOlivier Martin
When the function that determines the size of a contiguous region was returning from a sub-level table scanning it was forgetting to move to the next entry of its own level table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <Olivier.Martin@arm.com> Reviewed-by: Ronald Cron <Ronald.Cron@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17832 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19ARM Packages: Removed trailing spacesRonald Cron
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19ARM Packages: Corrected non-DOS line endingsRonald Cron
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15832 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/CpuDxe: Fixed some typo issues in the AArch64 exception codeOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15710 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-15ARM Packages: Force the SEC modules to be 2K aligned for AArch64Olivier Martin
The AArch64 Vector Table must be aligned on a 2K boundary. The FDF specification does not support 2K alignment but support 4K. A clear comment has been added to help integrator to understand why the assertion fails when porting to a new AArch64 platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-01ArmPkg/CpuDxe/ArmV6: Return error status when ExceptionHandlersStart is not ↵Olivier Martin
32-byte aligned The function should detect and return the error in non-debug builds when the ASSERT does nothing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15606 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-20ARM Packages: Fixed missing braces (the warning was disabled by GCC)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15578 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt ↵Olivier Martin
handling See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in "Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions" Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-14ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-levelOlivier Martin
If the first entry of the memory map is in the third level (case when the region at 0x0 is smaller than 4KB) then its descriptor type would be TT_TYPE_BLOCK_ENTRY_LEVEL3 (=0x3) which has the same value as TT_TYPE_TABLE_ENTRY (=0x3). The first condition in GetFirstPageAttribute() needed the table level to not mix these two descriptor types. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15526 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: Use .8byte instead of .dword for pointersBrendan Jackman
Clang doesn't recognise .dword Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15510 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ArmPkg/CpuDxe/AArch64: use STUR instruction for signed offsetBrendan Jackman
The AARCH64 LDR and STR instructions only support signed offsets for post- and pre-indexed addressing. For normal signed offset addressing, the mnemonic is STUR. GNU As automatically assembles STR with signed offset as STUR, but Clang's integrated assembler doesn't. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15508 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ArmPkg/CpuDxe/AArch64/ExceptionSupport.S: Fix immediate syntaxBrendan Jackman
GNU as assembles instructions without the '#' before immediates. Clang doesn't. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15507 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: use GCC_ASM_EXPORT to export functionsBrendan Jackman
This ensures the .type directive is used to mark them as function symbols Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: Remove GCC filter for AARCH64 assembly filesBrendan Jackman
Some non-GCC toolchain might support the GNU assembly language. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15504 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-23ArmPkg/CpuDxe: Restore AArch64 system registers before returning from exceptionoliviermartin
Current EDK2 source code does actually trigger nested interrupted (even if the PI spec says interrupt should not be nested). This issue has highlighted the lack of restoring ELR_EL2/ELR_EL1 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15481 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01ArmPkg: Tidy assembler codeOlivier Martin
- Fixed typo - Removed unreachable 'dead' loop Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15277 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg/CpuDxe: Removed LR adjustement for SVC callOlivier Martin
The Link Register (LR) does not need adjustement when receiving a Supervisor Call (SVC). Note: SVC might be generated by debuggers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14911 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-14ArmPkg/CpuDxe: Fixed confusion in AArch64 Table descriptor typesOlivier Martin
Table Descriptor and Level-3 Block entry descriptors have the same translation table type value (ie: 0x3). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14771 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-23ArmPkg/CpuDxe: Fixed the condition that checks if the level-1 descriptor ↵Olivier Martin
points to a level-2 page table Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14700 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-16ArmPkg/CpuDxe: Fixed attribute setting in GetNextEntryAttribute()Olivier Martin
The wrong attribute was used to set the region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14676 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-10ArmPkg/CpuDxe: Exception Handling SP AdjustEugene Cohen
The exception handling support code appears to adjust the stack pointer in the wrong direction. It decrements the stack pointer by 0x60, but this should be an increment (add) for the downward-growing stack. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14646 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/CpuDxe: Fixed calculation of the Page Table Index (Level 2 Descriptor)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14617 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Added support to not set a memory region with the same attributeOlivier Martin
Changing the attribute implies some cache management (clean & invalidate). Preventing the cache management should improve the performance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14568 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Added ConvertSectionAttributesToPageAttributes()Olivier Martin
This helper function converts the section attributes into their page equivalents. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Fixed AArch64 MMU/GCD synchronizationOlivier Martin
- Fix the length used to set the GCD Memory Space attribute - Print a warning message if the given length of a memory space region is not 4KB-aligned Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14562 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: AArch64: Fix wrong comparison of exception typeGirish K S
During the interrupt registration comparison is made against max value of exception types for ARMV7, but in the common handling function the check is made against max value of exceptions types for ARMV8. This can lead to undefined behaviour during registration of interrupts. This patch modifies the registration function to handle only AArch64 exceptions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14561 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg,ArmPlatformPkg: Free memory allocated by Get.*SpaceMap()Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14507 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg: Added Aarch64 supportHarry Liebel
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg/CpuDxe: Moved memory mapping functions that are not architecture ↵Olivier Martin
specific to 'CpuMmuCommon.c' Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14482 6f19259b-4bc3-4df7-8a09-765794883524
2013-03-12ArmPkg: Moved ARMv7 specific files to a 'Arm' subdirectoryoliviermartin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14180 6f19259b-4bc3-4df7-8a09-765794883524
2013-01-25ARM Packages: Fixed line endingsoliviermartin
This large code change only modifies the line endings to be CRLF to be compliant with the EDK2 coding convention document. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
2012-09-28ARM Packages: Moved ARM assembly files to 'Arm' subdirectoryoliviermartin
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13772 6f19259b-4bc3-4df7-8a09-765794883524
2012-09-27ARM Packages: Minor typo, mispellings and coding style changesoliviermartin
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13752 6f19259b-4bc3-4df7-8a09-765794883524
2012-07-04ARM Packages: Fixed mispellingsoliviermartin
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13502 6f19259b-4bc3-4df7-8a09-765794883524
2012-02-14ArmPkg: Changed ARM CPU SetMemoryAttributes to always use strongly ordered ↵oliviermartin
for the EFI_MEMORY_UC attribute Changed ARM CPU SetMemoryAttributes to always use strongly ordered for the EFI_MEMORY_UC attribute. Signed-off-by: Reviewed-by: eugenecohen Reviewed-by: yanivtal git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13011 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-27ARM Packages: Fixed Build failings/warnings/EDK2 coding conventionoliviermartin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12458 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-27ArmPkg/ArmLib: Clean ArmV7Liboliviermartin
- Move the non specific ArmV7 functions to ArmLib. - Clean the ARM Platform common components to not depend on ArmV7 if not required git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12453 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-22ArmPkg: Create MpCoreInfo PPI and HOB to describe CPU Cores on a MPCore platformoliviermartin
These info are: - ClusterId, CoreId - MailBox Set/Get/Clear address git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12423 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-22Arm Packages: Fixed coding style/Line endings to follow EDK2 coding conventionoliviermartin
Arm Packages: Fixed mispelling Arm Packages: Reduced warnings all over the code git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12407 6f19259b-4bc3-4df7-8a09-765794883524
2011-07-06ArmPlatformPkg: Remove PcdStandalone from Sec module and Introduce ↵oliviermartin
ArmPlatformSecExtraAction() The PcdStandalone is a PCD ARM Ltd uses to make the difference between a standalone UEFI (boot from cold boot to Boot Manager without user intervention) and a Debug UEFI firmware (the firmware engineer has to copy the Normale World image into the DRAM to enable his/her firmware). By coping the firmware into DRAM in the non standalone version it is much faster than reflashing the NOR Flash after each build. ArmPlatformSecExtraAction() function is called just before the Sec module jump to normal world. The platform firmware can run extra actions at this stage. The 'ARM Standalone' concept has moved to the implementation of ArmPlatformSecExtraAction() for the ARM development boards (in ArmPlatformPkg/Library/DebugSecExtraActionLib). ArmPlatformPkg: Enable DebugAgentLib in Sec and PrePeiCore ArmPlatformPkg: Fix line endings in some source files Use CR+LF line endings as defined by the EDK2 coding convention git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11991 6f19259b-4bc3-4df7-8a09-765794883524
2011-07-04ArmPkg/BdsLib: Linux kernel supports either FDT or ATAGoliviermartin
If a FDT blob is passed to the kernel it is required we can load it. If we fail to load the binary then we must abort the Linux booting process. ArmPkg/CpuDxe: Ensure the reset vector passed to the CP15 VBAR register is aligned on the right boundary git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11968 6f19259b-4bc3-4df7-8a09-765794883524
2011-07-01ArmPkg/CpuDxe: ZeroMem the gExceptionHandlers[] arrayoliviermartin
Prevent an IRQ (or any other exceptions) to make a call to an undefined handler when the interrupt handler has not been registered yet. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11965 6f19259b-4bc3-4df7-8a09-765794883524
2011-06-20ArmPkg/CpuDxe: Register a callback for the gIdleLoopEventGuid eventoliviermartin
This gIdleLoopEventGuid event signals the Cpu that it should go into the idle state waiting for any events. CpuSleep() is used in this implementation to make the Cpu wait for the next interrupt (WFI instruction). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11863 6f19259b-4bc3-4df7-8a09-765794883524
2011-06-20ArmPkg/CpuDxe: Change chain of dependency for CpuDxe and PL390Gicoliviermartin
Previously the CPU driver had a dependency on the GIC driver. But by design is should be the opposite. The CPU driver installs the CPU protocol that exposes the exception registration function. And then, the interrupt controller registers its IRQ handler through this interface. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11860 6f19259b-4bc3-4df7-8a09-765794883524
2011-06-03ArmPkg: Introduce ArmSetLowVectors/ArmSetHighVectors functionsoliviermartin
These functions set/clear the SCTLR.V bit that controls the location of the Vector Table. This commit also forces the SCTLR.V to be clear when the VBAR register is set. Note: The original fix has been proposed by Eugene Cohen (HP). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11739 6f19259b-4bc3-4df7-8a09-765794883524
2011-06-03Armkg: Fix EDK2 coding styleoliviermartin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11734 6f19259b-4bc3-4df7-8a09-765794883524
2011-06-03ArmPkg: Introduce the PCD PcdDebuggerExceptionSupportoliviermartin
The Exception Vector can be set before installing the CPU DXE driver to add debugger support at the early stage of the firmware initialization. If no one has touched the exception vector prior to the CPU DXE then the Vector might contain non zero data. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11733 6f19259b-4bc3-4df7-8a09-765794883524
2011-03-31Fix Xcode compile bug. It looks like these two arguments had an extra level ↵andrewfish
of indirection that was in error. Good thing about extra compilers is we catch this kind of thing for almost free. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11491 6f19259b-4bc3-4df7-8a09-765794883524
2011-03-31ArmPkg/CpuDxe: Replace SIZE_4KB by TT_DESCRIPTOR_PAGE_SIZEoliviermartin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11468 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-14 01:35:23 +0000