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The aim is to make this driver follows the ARM GIC specifications and
be implementation independent.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14810 6f19259b-4bc3-4df7-8a09-765794883524
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when Uniprocessor
When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero).
So the previous assertion was not correct.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14480 6f19259b-4bc3-4df7-8a09-765794883524
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CPU ID retrieved from the GIC
The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first
registers of the GIC CPU Target Registers.
The first GIC Distributor Target registers correspond to the SGIs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
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This constant allows to reduce architecture difference in the position
of the IRQ in the exception table.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14099 6f19259b-4bc3-4df7-8a09-765794883524
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This large code change only modifies the line endings to be CRLF to be
compliant with the EDK2 coding convention document.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13752 6f19259b-4bc3-4df7-8a09-765794883524
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(Cluster0,Cpu0)
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13488 6f19259b-4bc3-4df7-8a09-765794883524
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ArmGicGetMaxNumInterrupts()
The maximum number of interrupts can be retrieve through the GIC distributor.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13244 6f19259b-4bc3-4df7-8a09-765794883524
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interrupt)
Cleaning a special interrupt has an unpredictable behaviour.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13129 6f19259b-4bc3-4df7-8a09-765794883524
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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13040 6f19259b-4bc3-4df7-8a09-765794883524
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This library is the interface for the ARM Generic Interrupt Controller
Architecture Specification.
ARM Platform can use any GIC controller (not necessary PL390 GIC).
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12411 6f19259b-4bc3-4df7-8a09-765794883524
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interrupt handler
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12135 6f19259b-4bc3-4df7-8a09-765794883524
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Previously the CPU driver had a dependency on the GIC driver.
But by design is should be the opposite. The CPU driver installs the
CPU protocol that exposes the exception registration function.
And then, the interrupt controller registers its IRQ handler through
this interface.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11860 6f19259b-4bc3-4df7-8a09-765794883524
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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11789 6f19259b-4bc3-4df7-8a09-765794883524
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interrupt
Sporadic interrupts must not be handled by any interrupt handlers.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11469 6f19259b-4bc3-4df7-8a09-765794883524
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BdsUnixLib.h and fixed a lot of issues with Xcode building.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11293 6f19259b-4bc3-4df7-8a09-765794883524
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