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2017-02-22ArmPkg/ArmLib: AARCH64: allow the stack aligment (SA) bit to be managedArd Biesheuvel
In preparation of enabling stack alignment checking, which is mandated by the UEFI spec for AARCH64, add the code to manage this bit to ArmLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-01-20ArmPkg/ArmLib: remove indirection layer from timer register accessorsArd Biesheuvel
The generic timer support libraries call the actual system register accessor function via a single pair of functions ArmArchTimerReadReg() and ArmArchTimerWriteReg(), which take an enum argument to identify the register, and return output values by pointer reference. Since these functions are never called with a non-immediate argument, we can simply replace each invocation with the underlying system register accessor instead. This is mostly functionally equivalent, with the exception of the bounds check for the enum (which is pointless given the fact that we never pass a variable), the check for the presence of the architected timer (which only makes sense for ARMv7, but is highly unlikely to vary between platforms that are similar enough to run the same firmware image), and a check for enum values that refer to the HYP view of the timer, which we never referred to anywhere in the code in the first place. So get rid of the middle man, and update the ArmGenericTimerPhyCounterLib and ArmGenericTimerVirtCounterLib implementations to call the system register accessors directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
2016-07-28ArmPkg: Add Cortex-A72 CPU typeJeremy Linton
Add the Cortex-A72 CPU type which is used in JunoR2. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeremy Linton <jeremy.linton@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-07-13ArmPkg/ArmMmuLib: avoid type promotion in TCR_EL1 assignmentArd Biesheuvel
Commit fafb7e9c110e ("ArmPkg: correct TTBR1_EL1 settings in TCR_EL1") introduced a symbolic constant TCR_TG1_4KB which resolves to (2 << 30), and ORs it into the value to be written into TCR_EL1 (if executing at EL1). Since the constant is implicitly typed as signed int, and has the sign bit set, the promotion that occurs when casting to UINT64 results in a TCR value that has bits [63:32] all set, which includes mostly RES0 bits but also the TBIn, AS and IPS fields. So explicitly redefine all TCR related constants as 'unsigned long' types, using the UL suffix. To avoid confusion in the future, the inappropriately named VTCR_EL23_xxx constants have the leading V removed, and the actual VTCR_EL2 related constants are dropped, given that we never configure stage 2 translation in UEFI. Reported-by: Vishal Oliyil Kunnil <vishalo@qti.qualcomm.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com>
2016-03-16ArmPkg/ArmLib: add ArmReadHcr to enable read-modify-write of HCRCohen, Eugene
Add ArmReadHcr() to ArmLib to enable read-modify-write of the HCR system register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2015-12-16ArmPkg: rewrite vector table population macrosArd Biesheuvel
Unfortunately, Clang does not support the use of symbol references in .org directives, and bails with the following error message when it encounters them: <...>:error: expected assembly-time absolute expression .org DebugAgentVectorTable + 0x000 So replace the .org arguments with absolute values, and move the whole vector table into a subsection with the appropriate alignment, and starting at .org 0x0. This gives the same protection with respect to entries that exceed 128 bytes, in a way that Clang supports as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19303 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-19ArmPkg/ArmPlatformPkg: position vectors relative to baseMark Rutland
We currently rely on .align directives to ensure that each exception vector entry is the appropriate offset from the vector base address. This is slightly fragile, as were an entry to become too large (greater than 32 A64 instructions), all following entries would be silently shifted until they meet the next alignment boundary. Thus we might execute the wrong code in response to an exception. To prevent this, introduce a new macro, VECTOR_ENTRY, that uses .org directives to position each entry at the precise required offset from the base of a vector. A vector entry which is too large will trigger a build failure rather than a runtime failure which is difficult to debug. For consistency, the base and end of each vector is similarly annotated, with VECTOR_BASE and VECTOR_END, which provide the necessary alignment and symbol exports. The now redundant directives and labels are removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18904 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-19ArmPkg: correct TTBR1_EL1 settings in TCR_EL1Mark Rutland
As EDK2 runs in an idmap, we do not use TTBR1_EL1, nor do we configure it. TTBR1_EL1 may contain UNKNOWN values if it is not programmed since reset. Prior to enabling the MMU, we do not set TCR_EL1.EPD1, and hence the CPU may make page table walks via TTBR1_EL1 at any time, potentially using UNKNOWN values. This can result in a number of potential problems (e.g. the CPU may load from MMIO registers as part of a page table walk). Additionally, in the presence of Cortex-A57 erratum #822227, we must program TCR_EL1.TG1 == 0b1x (e.g. 4KB granule) regardless of the value of TCR_EL1.EPD1, to ensure that EDK2 can make forward progress under a hypervisor which makes use of PAR_EL1. This patch ensures that we program TCR_EL1.EPD1 and TCR_EL1.TG1 as above to avoid these issues. TCR_EL1.TG1 is set to 4K for all targets, as any CPU capable of running EDK2 must support this granule, and given TCR_EL1.EPD1, programming the field is not detrimental in the absence of the erratum. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18903 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18ArmPkg/ArmV7Lib: take MP extensions into account when programming TTBRArd Biesheuvel
Bits 0 and 6 of the TTBRx system registers have different meanings depending on whether a system implements the Multiprocessing Extensions. So use separate memory attribute definitions for MP and non-MP. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18899 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18ArmPkg/ArmV7Lib: fix definition of TTBR_NON_INNER_CACHEABLEArd Biesheuvel
The definition of TTBR_NON_INNER_CACHEABLE should be bit 0 cleared, not bit 0 set. Furthermore, the name is inconsistent with the other definitions so rename it to TTBR_INNER_NON_CACHEABLE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18898 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18ArmPkg/ArmV7Mmu: make cached translation table accesses shareableArd Biesheuvel
To align with the way normal cacheable memory is mapped, set the shareable bit for cached accesses performed by the page table walker. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18ArmPkg/ArmV7Mmu: fix write-through translation table accessesArd Biesheuvel
The definition TTBR_WRITE_THROUGH_NO_ALLOC makes little sense, since a) its meaning is unclear in the context of TTBRx, since write through always implies Read-Allocate and no Write-Allocate b) its definition equals the definition of TTBR_WRITE_BACK_ALLOC So instead, rename it to TTBR_WRITE_THROUGH and update the definition to reflect the name. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18893 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18ArmPkg/Mmu: set required XN attributes for device mappingsArd Biesheuvel
To prevent speculative intruction fetches from MMIO ranges that may have side effects on reads, the architecture requires device mappings to be created with the XN or UXN/PXN bits set (for the ARM/EL2 and EL1&0 translation regimes, respectively.) Note that, in the ARM case, this involves moving all accesses to a client domain since permission attributes like XN are ignored from a manager domain. The use of a client domain is actually mandated explicitly by the UEFI spec. Reported-by: Heyi Guo <heyi.guo@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18891 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18ArmPkg/AArch64Mmu: remove unused GcdAttributeToArmAttribute()Ard Biesheuvel
The function GcdAttributeToArmAttribute() is not used anywhere in the code base, and is only defined for AARCH64 and not for ARM. It also fails to set the bits for shareability and non-executability that we require for correct operation. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18888 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-12ArmPkg/ArmLib: mark all cached mappings as (inner) shareableArd Biesheuvel
Mark all cached memory mappings as shareable (or inner shareable on AArch64) so that our view of memory is kept coherent by the hardware. This is relevant for things like coherent DMA and virtualization (where a guest may migrate to another core) but in general, since UEFI on ARM is mostly used in a context where the secure firmware and possibly a secure OS are already up and running, it is best to refrain from using any non-shareable mappings. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18778 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-09ArmPkg/ArmLib: remove unused ARM9 supportArd Biesheuvel
The ARM9 ArmLib implementation is not referenced anywhere in the tree, and unlikely to be useful going forward, considering that ARM9 outdates even ARMv6. So remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18750 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-06ArmPkg: Purge unused/unneeded CPU-specific header filesLeif Lindholm
In ArmPkg/Include/Chipset, several CPU-specific header files reside. Most of these provide no actual, or very little, use. ARM1176JZ-S.h is not used at all (and unusable since SVN r18237). ArmAemV8.h simply includes AArch64.h. ArmCortexA15.h defines one processor-specific configuration bit and then includes ArmV7.h. Delete these include files, and update their sole users to function without them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18736 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-08ArmPkg/AArch64Mmu: use architecturally correct definitions for XN/UXNArd Biesheuvel
The non-privileged execute never (UXN) page table bit defined for the EL1&0 translation regime and the execute never (XN) bit defined for the EL2 and EL3 translation regimes happen to share the same bit position, but they are in fact defined distinctly by the architecture. So define both bits explicitly, and add comments in places where we take advantage of the fact that they share the same bit position. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18585 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-27ArmPkg: Expand AArch64 address width to 48 bitsHeyi Guo
The VA address space has a maximum address width of 48 bits in AArch64 state; 48 bits address width limit will provide better compatibility than 40 bits for future CPU. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Olivier Martin <Olivier.Martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17526 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-26ArmPlatformPkg/ArmJunoDxe: Set the platform dependent FDT device pathRonald Cron
The MIDR register of the CPU on which the UEFI firmware is running on is used to infer if the platform is a Juno r0 or a Juno r1. The right device path to the platform FDT is then stored in the "gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths" dynamic PCD. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16939 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19ARM Packages: Removed trailing spacesRonald Cron
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/AArch64.h: Added Exception Syndrome Register definitionsOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15709 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/AArch64: Added ARM_HCR_TSC definitionOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15708 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPkg/AArch64.h: Added SPSR and Timer register definitionsOlivier Martin
These timer register definitions are AArch64 specific. It is the reason why they are into this file and not into Chipset/ArmArchTimer.h. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15706 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03ArmPkg: Added new ARM Processor Feature Register definitionsOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15552 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26ArmPkg/ArmCortexA5x: Declared the helper functions to access the CPU ↵Olivier Martin
Extended Control Register This register is A5x specific. It is the reason why the code moved from ArmLib to ArmCpuLib/ArmCortexA5xLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15397 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26ArmPkg/Chipset: Added ARMv8 CPU's PartNumOlivier Martin
PartNum is the field of MIDR that returns the CPU name. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15395 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10ArmPkg/AArch64Mmu.h: Fix 'Shift is >= width of type'Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14956 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg: Move definition of ArmIsArchTimerImplemented / ArmReadIdPfrN to ArmLibOlivier Martin
These functions are not chipset specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14908 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-15ArmPkg/Include/Chipset: Fix translation table address calculations for AARCH64Garrett Kirkendall
TT_ADDRESS_* macros were not casting immediate values to UINTN. This causes shift operations to be off by 32-bits when calculating addresses above 4GB. Any address above 4GB was being improperly calculated. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14777 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Added ConvertSectionAttributesToPageAttributes()Olivier Martin
This helper function converts the section attributes into their page equivalents. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmV7Mmu.h: Added masks to extract attributes from Section and Page ↵Olivier Martin
entries Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14566 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Introduced TT_LAST_BLOCK_ADDRESS()Olivier Martin
This macro return the address of the last entry of a translation table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14565 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-06ArmPkg/ArmV7Mmu.h: Fixed XN bit conversion from section to small/large page ↵Olivier Martin
format Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14523 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-06ARM: Remove NSACR from the common codeOlivier Martin
NSACR (Non-Secure Access Control Register) is AArch32 specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg: Added Aarch64 supportHarry Liebel
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
2013-01-25ArmPkg/ArmV7.h: Introduced ARM_ARCH_EXCEPTION_IRQoliviermartin
This constant allows to reduce architecture difference in the position of the IRQ in the exception table. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14099 6f19259b-4bc3-4df7-8a09-765794883524
2013-01-25ArmPlatformPkg/PrePi: Removed magic valuesoliviermartin
Introduced CPSR (Coprocessor Status Register) definitions Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14097 6f19259b-4bc3-4df7-8a09-765794883524
2012-09-26ArmPkg/include: Added macro ARM_VECTOR_TABLE_ALIGNMENToliviermartin
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13744 6f19259b-4bc3-4df7-8a09-765794883524
2012-05-02ArmPkg/ArmCpuLib: Fixed SMP Cortex-A9 and Cortex-A15oliviermartin
Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13261 6f19259b-4bc3-4df7-8a09-765794883524
2012-05-02ARM Packages: Fixed th 'NS' (Non Secure) bit in the MMU page Table Descriptoroliviermartin
The 'NS' bit must only be set in Secure world to define the Non-Secure region of the Non-Secure World. This bit must not be set in Non-Secure World. Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13252 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-27ArmPkg: Add ARM Architectural Timer supportoliviermartin
ARM Architectural Timer support is defined by the ARM Generic Timer Specification. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12455 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-27ArmPkg/ArmLib: Update Arm11 portoliviermartin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12454 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-27ArmPkg/ArmLib: Clean ArmV7Liboliviermartin
- Move the non specific ArmV7 functions to ArmLib. - Clean the ARM Platform common components to not depend on ArmV7 if not required git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12453 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-27ArmPkg: Introduce ArmCpuLib to abstract ARM Cpu specific initialization (2)oliviermartin
Missed new files. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12450 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-22ArmPkg/ArmV7: Move the MMU specific macros into 'Chipset/ArmV7Mmu.holiviermartin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12426 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-22Arm Packages: Fixed coding style/Line endings to follow EDK2 coding conventionoliviermartin
Arm Packages: Fixed mispelling Arm Packages: Reduced warnings all over the code git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12407 6f19259b-4bc3-4df7-8a09-765794883524
2011-06-11ArmPkg: Fix coding style to follow EDK2 coding conventionoliviermartin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11789 6f19259b-4bc3-4df7-8a09-765794883524
2011-06-03ArmPkg: Implement PeiServicesTablePointerLib using TPIDRURW registeroliviermartin
This implementation use the Tpidrurw software context register to store the PEI Services Table Pointer. The author of this patch is Eugene Cohen (HP). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11750 6f19259b-4bc3-4df7-8a09-765794883524
2011-03-31ArmPkg/ArmV7: Fix TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK maskoliviermartin
The value for this mask was not correct. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11470 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-01 07:14:07 +0000