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2014-03-01ArmPkg: Tidy assembler codeOlivier Martin
- Fixed typo - Removed unreachable 'dead' loop Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15277 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01ArmPkg/ArmLib: Rationalise ArmReadMidr and cognate functions.Olivier Martin
The function ArmReadMidr has been recently added, but that functionality was already present under other names such as Cp15IdCode and ArmMainIdCode. This change removes redundant code and moves the function to the Common library. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15276 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01ArmPkg/ArmLib: Fix compilation error with -O3 switchOlivier Martin
A warning is reported because ArmArchTimerReadReg may theoretically result in an unititialised value. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15275 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01ArmPkg/ArmLib: ArmReadVBar implementation missing in AArch64Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15274 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01ArmPkg: Replace single dead loop.Olivier Martin
Several assembler macros use a loop at the label "dead" to trap an error. This is difficult to debug as there is no indication of how one arrived at the loop. This change replaces dead with distinct loops locally in the macro, which means the cause of the hang is detectable to the debugger. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15273 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01ArmPkg/ArmLib: Move common definitions from ArmV7Lib.h & AArch64Lib.h to ↵Olivier Martin
ArmLib.h Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15272 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-24ArmPkg/AsmMacroIoLibV8.h: Correct 32 bit accesses in asm macrosOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15257 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-24ARM Packages: Include 'AsmMacroIoLibV8.h' instead of the 32bit versionOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15256 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-24ArmPkg/BdsLib: Support ignoring EfiReservedMemoryType when updating the FDT.Garrett Kirkendall
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15255 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12ARM Packages: CRLF fixupLeif Lindholm
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15241 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12ArmPkg/ArmLib: Added ArmReadMidr()Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15240 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12ArmPkg/BdsLib: Removed unused MachineType argument (AArch64)Olivier Martin
MachineType was used on 32-bit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15239 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-12ArmPkg: Removed unused header 'BdsUnixLib.h'Olivier Martin
This header contains a function that does not exist. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15238 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-05ArmPkg/ArmLib: VBAR_ELx not written correctly when handler above 4GBOlivier Martin
The function ArmWriteVBar had a UINT32 parameter. Need to change it to UINT. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15208 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-24ArmPkg/ArmLib: Fix AARCH64 page table entry filling overrunGarrett Kirkendall
Update the LastBlockEntry return value when allocating a new page table block and the parent page table entry is not valid. Discovered when producing page table entries for a memory region that spans multiple page table entries of a parent page table block. Not very memory space efficient because the rest of the code could calculate a required page level that is deeper than some blocks of the memory region might require. Case that found the problem: MemoryRegion->VirtualBase = 0 MemoryRegion->Length = 0x7F000000 This fix will create an un-needed level of page table for address range 0 -> 0x40000000 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15177 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-15ArmPkg/CompilerIntrinsicsLib: Make __aeabi_memcpy the same as memcpyOlivier Martin
This code also removed some redundant instructions. __aeabi_memcpy doesn't require preservation of r0 (as memcpy does), which could save a push, but the code has been left to keep things consistent. The reason __aeabi_memcpy has been added to the .S file is so it will be available to toolchains that use the GCC assembler but the full ARM EABI (i.e. current LLVM) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15124 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-10ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64Olivier Martin
The System Memory region might be out of the 32-bit memory space. This change has been validated on the FVP AArch64 model using 4GB of DRAM at 0x8_0000_0000: - # System Memory (2GB) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000 + # System Memory (4GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000 EFI Shell and Linux kernel boot successfully. Note: This change has not been validated on AArch32. I expect some early assembly code to not work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10ARM Packages: Removed 'inline' keywordOlivier Martin
'inline' keyword is not supported by the C89 (version used by EDK2). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14957 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10ArmPkg/AArch64Mmu.h: Fix 'Shift is >= width of type'Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14956 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10ArmPkg/ArmDisassemblerLib: Fixed logical/bitwise operator confusionOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14955 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10ArmPkg/ArmMpCoreInfo.h: Fixed macro definitionOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14954 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg/BdsLib: Fixed the alignment of the relocated Device TreeOlivier Martin
When the Device Tree was loaded above the 32bit address space the operation: *RelocatedFdt = ALIGN ((UINT64)*RelocatedFdt, (UINT32)FdtAlignment); was returning an incorrect address. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14915 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg/DebugPeCoffExtraActionLib: Fixed the printing of the location of the ↵Olivier Martin
EFI modules When loaded above the 32-bit address space the address requires more than 8 characters. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14913 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg/CpuDxe: Removed LR adjustement for SVC callOlivier Martin
The Link Register (LR) does not need adjustement when receiving a Supervisor Call (SVC). Note: SVC might be generated by debuggers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14911 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg: Move definition of ArmIsArchTimerImplemented / ArmReadIdPfrN to ArmLibOlivier Martin
These functions are not chipset specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14908 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPlatformPkg/ArmVExpressPkg: Removed unused PCDs declaration from INF fileOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14907 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-29ARM Packages: Renamed PL390Gic driver into ArmGic driverOlivier Martin
The aim is to make this driver follows the ARM GIC specifications and be implementation independent. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14810 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-24ArmPkg/PL390Gic: Fixed setting of the Interrupt Processor Targets Registers ↵Olivier Martin
when Uniprocessor When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero). So the previous assertion was not correct. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-15ArmPkg/Include/Chipset: Fix translation table address calculations for AARCH64Garrett Kirkendall
TT_ADDRESS_* macros were not casting immediate values to UINTN. This causes shift operations to be off by 32-bits when calculating addresses above 4GB. Any address above 4GB was being improperly calculated. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14777 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-14ArmPkg/CpuDxe: Fixed confusion in AArch64 Table descriptor typesOlivier Martin
Table Descriptor and Level-3 Block entry descriptors have the same translation table type value (ie: 0x3). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14771 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-23ArmPkg/ArmLib: Revert change 'Fixed field shifting in CLIDR_EL1 (AArch64)'Olivier Martin
The shift by 1 on the left was expected. It eases the access to CSSELR and set/way operations where the cache level field is at the BIT1 position. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14704 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-23SemihostFs: Fix check for read-only file or file-openOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14703 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-23ArmPkg/CpuDxe: Fixed the condition that checks if the level-1 descriptor ↵Olivier Martin
points to a level-2 page table Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14700 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-16ArmPkg/ArmLib: Fixed field shifting in CLIDR_EL1 (AArch64)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14677 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-16ArmPkg/CpuDxe: Fixed attribute setting in GetNextEntryAttribute()Olivier Martin
The wrong attribute was used to set the region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14676 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-10ArmPkg/CpuDxe: Exception Handling SP AdjustEugene Cohen
The exception handling support code appears to adjust the stack pointer in the wrong direction. It decrements the stack pointer by 0x60, but this should be an increment (add) for the downward-growing stack. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14646 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-03ArmPkg/CpuPei: Remove unused functions from the driverRoy Franz
The ConfigureMmu() function is unused - the only call to it is commented out, and the functionality has been moved to InitMmu() in MemoryInitPeiLib.c. This change also removes the unused definitions from the file. Change-Id: Ice795bfee25c403142d0c078533f8a46d04f82e9 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Roy Franz <roy.franz@linaro.org> Signed-off-by:: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14621 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/ArmDmaLib: Fixed the calculation of the Base Address of the BufferOlivier Martin
The former calculation 'ALIGN_VALUE(*DeviceAddress - BASE_4KB - 1,BASE_4KB)' did not return the lowest aligned address. Example: *DeviceAddress = 0xB000C001; *DeviceAddress - BASE_4KB - 1 = 0xB000B000; Aligned value = 0xB000B000 + ((0x1000 - 0xB000B000)) & 0xFFF) = 0xB000B000 ... while we where expected 0xB000C000. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14618 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/CpuDxe: Fixed calculation of the Page Table Index (Level 2 Descriptor)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14617 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/ArmLib: Change comment to match code for setting of V bit in SCTLR ↵Roy Franz
register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Roy Franz <roy.franz@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14616 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-21ArmPkg/ArmGicLib.h: Added macro to retrieve the information from the ICCIDROlivier Martin
These macros are helper functions to get the information from the GIC CPU Interface Identification register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14582 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-21ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3Olivier Martin
This is already taken care by Sec when PcdTrustzoneSupport = TRUE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Added support to not set a memory region with the same attributeOlivier Martin
Changing the attribute implies some cache management (clean & invalidate). Preventing the cache management should improve the performance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14568 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Added ConvertSectionAttributesToPageAttributes()Olivier Martin
This helper function converts the section attributes into their page equivalents. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmV7Mmu.h: Added masks to extract attributes from Section and Page ↵Olivier Martin
entries Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14566 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Introduced TT_LAST_BLOCK_ADDRESS()Olivier Martin
This macro return the address of the last entry of a translation table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14565 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Fixed AArch64 MMU/GCD synchronizationOlivier Martin
- Fix the length used to set the GCD Memory Space attribute - Print a warning message if the given length of a memory space region is not 4KB-aligned Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14562 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: AArch64: Fix wrong comparison of exception typeGirish K S
During the interrupt registration comparison is made against max value of exception types for ARMV7, but in the common handling function the check is made against max value of exceptions types for ARMV8. This can lead to undefined behaviour during registration of interrupts. This patch modifies the registration function to handle only AArch64 exceptions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14561 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-06ArmPkg/ArmV7Mmu.h: Fixed XN bit conversion from section to small/large page ↵Olivier Martin
format Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14523 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-06ARM: Remove NSACR from the common codeOlivier Martin
NSACR (Non-Secure Access Control Register) is AArch32 specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524
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