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2015-02-28ArmPkg: allow patchable PCDs for memory, FD and FV addressesArd Biesheuvel
In order to allow a runtime self relocating PrePi instance, change the allowable PCD types for the following PCDs: gArmTokenSpaceGuid.PcdSystemMemoryBase gArmTokenSpaceGuid.PcdSystemMemorySize gArmTokenSpaceGuid.PcdFdBaseAddress gArmTokenSpaceGuid.PcdFvBaseAddress to include PcdsPatchableInModule. This makes the build system correctly distinguish fixed PCDs from PCDs whose value may be different from the assigned value at compile time. Note that this only affects platforms that explicitly mark these PCDs as PatchableInModule in the DSC. All existing platforms that use FixedPcd will not be affected by this change. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16954 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-28ArmPkg: allow HYP timer interrupt to be omittedArd Biesheuvel
The DT binding for the ARM generic timer describes the secure, non-secure, virtual and hypervisor timer interrupts, respectively. However, under virtualization, only the virtual timer is usable, and the device tree may omit the hypervisor timer interrupt. (Other timer interrupts cannot be omitted simply due to the fact that the virtual timer is listed third) Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16953 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-26ArmPlatformPkg/Bds: Remove any use of the "Fdt" UEFI variableRonald Cron
Remove the option to update the "Fdt" UEFI variable in the ARM BDS as the "setfdt" EFI Shell command provides this service from now. Remove the use of this variable in the legacy kernel boot loader and use the FDT installed in the configuration table instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16940 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-26ArmPlatformPkg/ArmJunoDxe: Set the platform dependent FDT device pathRonald Cron
The MIDR register of the CPU on which the UEFI firmware is running on is used to infer if the platform is a Juno r0 or a Juno r1. The right device path to the platform FDT is then stored in the "gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths" dynamic PCD. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16939 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-26ArmPlatformPkg/ArmVExpressDxe: Load FDT into the EFI Configuration TableRonald Cron
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16937 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-25ArmPkg/BdsLib: Added support to change the given DevicePath of a Boot EntryOlivier Martin
Some boot entries might not have a EFI Device Path FilePath attached to it (eg: EFI device Path for removable device path). This patch allows a support loader to edit the EFI Device Path and for instance add \EFI\BOOT\BOOT(ARM|AA64).EFI Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16930 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-25ArmPkg/ArmGic: Fix GICv3 in GICv2 legacy modeOlivier Martin
- GIC distributor needs to be programmed to target interrupts on the boot CPU using the Interrupt Processor Targets Registers - Enabling the GIC Distributor is different following the value of GICD_CTLR.ARE_NS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16926 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-16ArmPkg/ArmGic: enable ARE bit before driving GICv3 in native modeArd Biesheuvel
The GICv3 driver must use native mode to drive a GICv3 due to the fact that v2 compatibility is optional in the v3 spec. However, if v2 compatibility is implemented, it is the default and needs to be disabled first by setting the Affinity Routing Enable (ARE) bit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> [added PCD that allows forcing the GICv3 driver to drive the GIC in v2 mode] Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16875 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-16ArmPkg/ArmGic: Use the GIC Redistributor instead of GIC Distributor for GICv3Olivier Martin
GICv3 controller with no GICv2 legacy support must use the GIC Redistributor registers instead of the GIC Distributor registers for some operations (eg: enable/disable interrupts). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16874 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-16ArmPkg/ArmGic: Function to locate the current CPU GIC redistributorOlivier Martin
CPU GIC Registributors are located next to each other in the GIC Redistributor space. The CPU GIC Redistributor is identified by its CPU affinity Aff3.Aff2.Aff1.Aff0. This function returns the base address of the GIC Redistributor of the calling CPU. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16873 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-16ArmPkg/ArmGic: Added GICv3 specific definitionsOlivier Martin
ARM GICv3 specification introduces some new components and registers. This patch adds their definitions. The most important GICv3 component is the GIC Redistributor. It supports LPIs (Locality-specific peripheral Interrupt), 8+ CPU configuration. Some GIC distributor registers have moved to the GIC redistributor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16872 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-16ArmPkg/ArmLib.h: Add CPU Affinity definitionsOlivier Martin
The CPU affinity fields are defined by MPIDR/MPIDR_EL1. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Tested-by: Ard Biesheuvel <ard@linaro.org> Reviewed-by: Ard Biesheuvel <ard@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16871 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-03*/Contributions.txt: Update example email addressJordan Justen
Use the example.com domain as recommended in RFC 2606. NOTE: This does not modify the wording of the "TianoCore Contribution Agreement 1.0" section Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Bruce Cran <bruce.cran@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16724 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-02ArmPkg: ArmArchTimerLib: conditionally rebase to actual timer frequencyLaszlo Ersek
Allow a platform to set PcdArmArchTimerFreqInHz to zero, and consider it a request to use the actual timer frequency. No global variable is introduced, so that the library can be used in PEIMs that execute from flash. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16691 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-02ArmPkg: ArmArchTimerLib: use edk2-conformant (UINT64 * UINT32) / UINT32Laszlo Ersek
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16690 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-02ArmPkg: ArmArchTimerLib: clean up commentsLaszlo Ersek
In the next patch we'll slightly reorganize TimerConstructor(). Let's improve the comments first. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Olivier Martin <Olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16689 6f19259b-4bc3-4df7-8a09-765794883524
2015-01-06ArmPkg/BdsLib: Close file after reading an ImageRonald Cron
When loading an image from a file, close the file after reading from it. Use OpenProtocol instead of HandleProtocol to retrieve the simple file system protocol interface. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16586 6f19259b-4bc3-4df7-8a09-765794883524
2015-01-06ArmPkg/BdsLib: Fix DHCP4 configurationRonald Cron
Fix DHCP4 configuration as part of TFTP boot process to get the IP address of the gateway and the subnet mask from the DHCP server. Fix a memory leak when the download from the TFTP server fails as well. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16582 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12ArmPkg/AsmMacroIoLib: Fixed the global variables initializationOlivier Martin
The top of the stack always points to 'stack_base + stack_size'. But the stack pointer is decremented before writing to the stack. It means the top byte of the stack is actually 'stack_base + stack_size - 1'. The initialization should also decrement the stack pointer before zero'ing the memory (pre-indexed addressing). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16518 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12ArmPkg/BdsLib: Update the size of the Device Tree before booting LinuxOlivier Martin
The memory reserved to load the device tree is over-allocated when UEFI loads the blob to update the device tree with additional information such as the command line, the initrd, etc. This change ensures the total size declared by the device tree matches the actual data (and not the over-allocated size value). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16517 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12ArmPkg/BdsLib: Rework TFTP bootRonald Cron
Rework the downloading of an image from a TFTP server to do not depend on any "PXE specific" setting of the DHCP server. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16516 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12ArmPkg/GenericWatchdogDxe: Set up the watchdog timeout relatively to the ↵Ronald Cron
system counter Use the system counter to compute the watchdog compare value as the watchdog compare value is compared to the system counter to check if the watchdog timeout expired or not. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16513 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12ArmPlatformPkg/ArmJunoPkg: Move the watchdog generic driver to ArmPkg/DriversRonald Cron
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <Ronald.Cron@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16512 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-12ArmPlatformPkg: The toolchain family name can be omitted if the options are ↵Olivier Martin
common Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16508 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-13ArmPkg/ArmGicLib: select GICv2 mode if SRE is present but unavailableArd Biesheuvel
Even if the CPU id registers indicate hardware support for the System Register interface to the GIC, higher exception levels may disable that interface and only allow access through MMIO. So move the enabling of the SRE bit to the GIC version detection routine: if we trigger an exception, we would have anyway at a later stage, so the net effect is the same. However, if setting the bit doesn't stick, it means we can switch to MMIO and proceed normally otherwise. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16344 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-13ArmPkg/ArmGic: Removed 'GCC' toolchain to build assembly filesOlivier Martin
ARMCC6 toolchain (LLVM based) understands the GNU assembly language. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16343 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11ArmPkg/ArmArchTimerLib: Promotes 32bit value to prevent overflowOlivier Martin
Both MicroSeconds and PcdArmArchTimerFreqInHz are 32-bit values on AArch32 so their multiplication produces 32-bit result that might cause wrong calculation. Example: With MicroSeconds = 200 us, PcdArmArchTimerFreqInHz = 24MHz. 200*24000000 = 0x1_1E1A_3000 => So 0x1E1A_3000 when the type is UINT32. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16329 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11ArmPkg/CompilerIntrinsicesLib: Fixed memmove() and memset()Olivier Martin
- Fixed memmove when going backward: the copy started one byte after the end of the region to copy - memset: - removed unused register - fixed arguments size and character arguments were actually reversed - Added memmove() to ARM32 GCC Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16328 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11ArmPkg: Ensured the stack is always quad-word alignedOlivier Martin
From the AArch64 Procedure Call Standard (ARM IHI 0055B): 5.2.2.1 Universal stack constraints At all times the following basic constraints must hold: - SP mod 16 = 0. The stack must be quad-word aligned. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16327 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11ArmPlatformPkg: Increase more ARM address Pcd entries to 64-bit.Leif Lindholm
Some AArch64 platforms have RAM and flash devices >4GB. Update some additional Pcd entries to 64-bit, and change the corresponding PcdGet32 calls to PcdGet64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16325 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-31EDK II Contributions.txt: Update patch format informationJordan Justen
Update to show what the patch looks like in email form. NOTE: This does not modify the wording of the "TianoCore Contribution Agreement 1.0" section Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16297 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmLib: Removed duplicated invalidate TLB functionOlivier Martin
ArmInvalidateInstructionAndDataTlb() was doing the same thing as ArmInvalidateTlb(). Both invalidate Data and Instruction TLBs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16253 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/SemihostFs: Implement SetInfo() and handle seeking past the end of a fileRonald Cron
Implement the resizing of the file with SetInfo(). Implement the renaming of a file with SetInfo(). Allow to seek past the end of a file. The support of file resizing implies a rework of the read, write and close functions. So does the support of seeking past the end of a file. That why those two changes are done in the same patch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16244 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/SemihostFs: Fix open file issues revealed by SCTRonald Cron
Fix return codes in case of errors. Fix translation from EFI open mode to semi-hosting open mode to avoid the truncate to zero length of an already existing file opened in read/write or read/write/create mode. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16241 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/SemihostLib: Add library functionsRonald Cron
Add library functions to rename a file and get a temporary name for a file through the semi-hosting interface. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16238 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/Semihostlib: Rename semi-hosting open optionRonald Cron
Change mnemonic SEMIHOST_FILE_MODE_CREATE with mnemonic SEMIHOST_FILE_MODE_UPDATE. The bit referred to by this mnemonic is for the semi-hosting open mode code the equivalent of the + in the ISO C fopen mode terminology. This allows to select the so called update mode for which both read and write are allowed on the open file. The mnemonic SEMIHOST_FILE_MODE_UPDATE is more in line with the ISO C fopen mode terminology. A description of the ISO C fopen modes can be found here : http://pubs.opengroup.org/onlinepubs/009695399/functions/fopen.html. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16237 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmGic: Added GicV3 support to ArmGicDxeOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16234 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmGic: Added GicV3 support to ArmGicLibOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16233 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmGic: Added GicV3 detectionOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16232 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-27ArmPkg/ArmGic: Introduced ArmGicGetSupportedArchRevision()Olivier Martin
This function returns the revision of the GIC Architecture. Some GICv3 controllers can work in GICv2 mode. Switching to an older GIC revision is driven by the higher level exception level. This function allows code to support any GIC revision at runtime. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16231 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10ArmPkg/ArmLib/AArch64: Initialize the new N+1-level page table before ↵Olivier Martin
registering it Prior to this change, when a new page table was created at level N+1, the reference to the table was added to the level N translation table, before being initialized. It means if virtual addresses were in the address range defined by this new table the CPU would crash as the address range was not initialized. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16206 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10ArmPkg/UncachedMemoryAllocationLib: Track uncached memory allocationsOlivier Martin
Keeping track of uncached memory allocations prevents doing expensive cache operations (eg: clean & invalidate) on newly allocated regions by reusing regions where possible Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16205 6f19259b-4bc3-4df7-8a09-765794883524
2014-10-10ArmPkg/ArmPsciResetSystemLib: Made the library only using SMCOlivier Martin
Only ArmVirtualizationPkg based platforms are expected to use the dynamic method to choose between SMC and HVC to invoke PSCI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16204 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-18ArmPkg/TimerDxe: add workaround for KVM timer interrupt handlingArd Biesheuvel
KVM on ARM currently masks the timer interrupt on the timer side when delivering an interrupt to the guest. This itself is a workaround for an issue where the interrupt is reraised and trapped by the host as soon as the guest is entered, resulting in the guest being starved. Work around this by calling ArmGenericTimerEnable () after servicing each interrupt. The virtual version of ArmGenericTimerCounterLib will then make sure to unmask the interrupt again. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16144 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-16ArmPsciResetSystemLib: read PSCI method in constructorArd Biesheuvel
As this library is used in the implementation of a Runtime Service, make sure to access dynamic PCDs only in the constructor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16108 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg/TimerDxe: Read timer frequency from CPUArd Biesheuvel
The PCD gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz is used in the SEC phase (if applicable) to write the platform's counter frequency to the CNTFRQ system register, as this needs to be done by the highest exception level implemented. Under virtualization, we should be able to rely on the host to have initialized this register to a sane value, as we run at EL1 and only use the virtual timer, so the PcdArmArchTimerFreqInHz PCD has little meaning here. So in either case, by the time we enter the DXE phase, we can use the CNTFRQ system register to read the frequency instead of looking at the PCD. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16090 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg: Introduced ArmPsciResetSystemLibArd Biesheuvel
This implementation of EfiResetSystemLib uses ARM PSCI calls to perform reboot and poweroff, using either HVC or SMC calls. Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16089 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg: Add ArmHvcLibArd Biesheuvel
This is a utility library closely modeled after ArmSmcLib, that allows hypervisor call (HVC) instructions to be issued from C code. Change-Id: I5f5c65f83e910ff98dbb2f5b031dad8c4f663daa Contributed-under: TianoCore Contribution Agreement 1.0 Acked-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16088 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg: Add PSCI 0.2 constants for system poweroff and resetArd Biesheuvel
Change-Id: I683a603300812578c15cf3c1e0ccb7574fdb5caf Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16087 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-10ArmPkg/ArmSmcLib: fix stack handling in .asm version of SMC wrapperArd Biesheuvel
This fixes a bug in the stack handling in the RVCT .asm version of the SMC wrapper. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16086 6f19259b-4bc3-4df7-8a09-765794883524
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