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2013-09-16ArmPkg/ArmLib: Fixed field shifting in CLIDR_EL1 (AArch64)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14677 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-16ArmPkg/CpuDxe: Fixed attribute setting in GetNextEntryAttribute()Olivier Martin
The wrong attribute was used to set the region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14676 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-10ArmPkg/CpuDxe: Exception Handling SP AdjustEugene Cohen
The exception handling support code appears to adjust the stack pointer in the wrong direction. It decrements the stack pointer by 0x60, but this should be an increment (add) for the downward-growing stack. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14646 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-03ArmPkg/CpuPei: Remove unused functions from the driverRoy Franz
The ConfigureMmu() function is unused - the only call to it is commented out, and the functionality has been moved to InitMmu() in MemoryInitPeiLib.c. This change also removes the unused definitions from the file. Change-Id: Ice795bfee25c403142d0c078533f8a46d04f82e9 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Roy Franz <roy.franz@linaro.org> Signed-off-by:: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14621 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/ArmDmaLib: Fixed the calculation of the Base Address of the BufferOlivier Martin
The former calculation 'ALIGN_VALUE(*DeviceAddress - BASE_4KB - 1,BASE_4KB)' did not return the lowest aligned address. Example: *DeviceAddress = 0xB000C001; *DeviceAddress - BASE_4KB - 1 = 0xB000B000; Aligned value = 0xB000B000 + ((0x1000 - 0xB000B000)) & 0xFFF) = 0xB000B000 ... while we where expected 0xB000C000. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14618 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/CpuDxe: Fixed calculation of the Page Table Index (Level 2 Descriptor)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14617 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/ArmLib: Change comment to match code for setting of V bit in SCTLR ↵Roy Franz
register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Roy Franz <roy.franz@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14616 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-21ArmPkg/ArmGicLib.h: Added macro to retrieve the information from the ICCIDROlivier Martin
These macros are helper functions to get the information from the GIC CPU Interface Identification register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14582 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-21ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3Olivier Martin
This is already taken care by Sec when PcdTrustzoneSupport = TRUE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Added support to not set a memory region with the same attributeOlivier Martin
Changing the attribute implies some cache management (clean & invalidate). Preventing the cache management should improve the performance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14568 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Added ConvertSectionAttributesToPageAttributes()Olivier Martin
This helper function converts the section attributes into their page equivalents. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmV7Mmu.h: Added masks to extract attributes from Section and Page ↵Olivier Martin
entries Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14566 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Introduced TT_LAST_BLOCK_ADDRESS()Olivier Martin
This macro return the address of the last entry of a translation table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14565 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Fixed AArch64 MMU/GCD synchronizationOlivier Martin
- Fix the length used to set the GCD Memory Space attribute - Print a warning message if the given length of a memory space region is not 4KB-aligned Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14562 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: AArch64: Fix wrong comparison of exception typeGirish K S
During the interrupt registration comparison is made against max value of exception types for ARMV7, but in the common handling function the check is made against max value of exceptions types for ARMV8. This can lead to undefined behaviour during registration of interrupts. This patch modifies the registration function to handle only AArch64 exceptions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14561 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-06ArmPkg/ArmV7Mmu.h: Fixed XN bit conversion from section to small/large page ↵Olivier Martin
format Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14523 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-06ARM: Remove NSACR from the common codeOlivier Martin
NSACR (Non-Secure Access Control Register) is AArch32 specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg/ArmLib: Fixed TBLs invalidation in EL1Olivier Martin
'tlb alle1' was used to invalidate the TLBs in EL1. Expect this instruction can only be invoked from EL2. The correct instruction to invalidate TLBs in EL1 is 'tlbi vmalle1' - it invalidates the TLBs of the current VMID. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14509 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg/Library: AArch64 MMU EL1 supportOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14508 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg,ArmPlatformPkg: Free memory allocated by Get.*SpaceMap()Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14507 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg/ArmLib/AArch64: Use the appropriate macros and update commentsOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14506 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-24ArmPkg: Update the AArch64 Image File Machine Type to match the PE/COFF specOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14502 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-24ArmPkg/BdsLib: AArch64 MPCore Linux 'spin-table' boot cache fixHarry Liebel
Clean data cache after initialising mailboxes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14501 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-24ArmPkg/ArmLib/AArch64: Fixed the calculation of the last entry in the ↵Olivier Martin
Translation Table Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14500 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg: Added AArch64 support (missing files)Harry Liebel
Some missing files from the initial AArch64 commit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14488 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg/BdsLib: Added Aarch64 support for booting LinuxHarry Liebel
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14487 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg: Added Aarch64 supportHarry Liebel
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg/CpuDxe: Moved memory mapping functions that are not architecture ↵Olivier Martin
specific to 'CpuMmuCommon.c' Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14482 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-17ArmPkg: Removed the non-used PCD PcdGicPrimaryCoreIdOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14480 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-17ArmPkg/PL390Gic: Populate the GIC Distributor Target Register with the GIC ↵Olivier Martin
CPU ID retrieved from the GIC The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first registers of the GIC CPU Target Registers. The first GIC Distributor Target registers correspond to the SGIs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-16ArmPkg/UncachedMemoryAllocationLib: Removed unused header (Protocol/Cpu.h)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14469 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-15ArmPkg: Fix UncachedFreeAlignedPages in UncachedMemoryAllocationLibEugene Cohen
Route both the setting and restoring of cacheability through DXE Services/GCD and stop using the CPU AP directly. The patch also removes all references to the CPU AP which eliminates the need for a library constructor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Senthil Ramakrishnan <senthil.ramakrishnan@hp.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14468 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-27ArmPkg/BdsLib: Fixed manipulation of the Memory Map returned by GetMemoryMap()Olivier Martin
The UEFI specification mandates that software uses the DescriptorSize returned by the GetMemoryMap() function to find the start of each EFI_MEMORY_DESCRIPTOR in the MemoryMap array. This allows for future expansion of the EFI_MEMORY_DESCRIPTOR. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14447 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-27ArmPkg/ArmLib: Marked functions as 'STATIC' if not exposed outside of the ↵Olivier Martin
scope of the source file Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14446 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-27ArmPkg: Made ArmConfigureMmu() returns a status codeOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14445 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-19ArmPkg/ArmLib: Removed ArmInvalidateTlb when disabling cache as ↵Olivier Martin
ArmDisableMmu() already does it Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14436 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-19ArmPkg: Moved PcdArmLinuxAtagMaxOffset to be ARM specificOlivier Martin
ATAG is specific to 32bit ARM architecture. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14435 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-19ArmPkg/BdsLib: Update FDT CPU node formatOlivier Martin
- Based on Doc here: Repo: http://www.linux-arm.org/git?p=linux-2.6-lp.git Branch: dt-cpus-bindings File: Documentation/devicetree/bindings/arm/cpus.txt Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14434 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-19ArmPkg/Drivers/TimerDxe: Improve Timer initialisation.Olivier Martin
- Registering a interrupt handler implicitly enables said interrupt. This is in the UEFI Spec. No need to enable the interrupts a second time. - Make sure the Timer is completely disabled before configuring it. Only enable after configuration is complete. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14433 6f19259b-4bc3-4df7-8a09-765794883524
2013-05-12ArmPkg/BdsLinuxFdt.c: Fix creation of 'cpu' and 'psci' device tree nodes.oliviermartin
* Fix name of 'device_type' and 'migrate' properties. * Fix 'reg' property. It is supposed to contain the CPU MPIDR of the CPU being described. * Fix byte ordering of data in 'psci' node. * Fix some problems regarding the size of data. In a number of places it was assumed data would be 32-bits wide. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14351 6f19259b-4bc3-4df7-8a09-765794883524
2013-05-12ArmPkg/BdsLinuxFdt.c: Introduce cpu_to_fdtn() function.oliviermartin
Introduce cpu_to_fdtn() function which will call the appropriate 32-bit or 64-bit version based on the size of a native integer. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14350 6f19259b-4bc3-4df7-8a09-765794883524
2013-05-12ArmPkg/BdsLinuxFdt.c: Split PrepareFdt() into several functions.oliviermartin
PrepareFdt() function was getting pretty fat and big functions are more complex to understand and find the information one is looking for. This patch extracts some code from PrepareFdt() function and put it in some new functions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14349 6f19259b-4bc3-4df7-8a09-765794883524
2013-05-10ARM Packages: Replaced the macro GetCorePositionFromMpId() by the ↵oliviermartin
ArmPlatformGetCorePosition() Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14346 6f19259b-4bc3-4df7-8a09-765794883524
2013-05-10ArmPlatformPkg/ArmPlatformLib: Added support for ArmPlatformIsPrimaryCore()oliviermartin
Checking if a core if the primary/boot core used to be done with the macro IS_PRIMARY_CORE(). Some platforms exposes configuration registers to change the primary core. Replacing the macro IS_PRIMARY_CORE() by ArmPlatformIsPrimaryCore() allows some flexibility in the way to check the primary core. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14344 6f19259b-4bc3-4df7-8a09-765794883524
2013-04-14ArmPkg/BdsLib: Added support for FDT alignment through PcdArmLinuxFdtAlignmentoliviermartin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14274 6f19259b-4bc3-4df7-8a09-765794883524
2013-04-14ArmPkg: Delete PCD value PcdArmLinuxKernelFixedOffset.oliviermartin
PcdArmLinuxKernelFixedOffset is supposed to indicate the offset from the beginning of the system memory at which the kernel will be loaded. However, this PCD value is not used at all. Instead the kernel is loaded just below a certain limit indicated by PCD value PcdArmLinuxKernelMaxOffset. This patch deletes PCD value PcdArmLinuxKernelFixedOffset to avoid any confusion. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14273 6f19259b-4bc3-4df7-8a09-765794883524
2013-04-14ArmPkg/BdsLib: Fix uInitrd detectionoliviermartin
This patch corrects a problem detecting uInitrd signature when booting with FDT. BdsBootLinuxFdt was attempting to read the signature from InitrdImage which is zero at this point in the code. The code now reads the signature from InitrdImageBase. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14272 6f19259b-4bc3-4df7-8a09-765794883524
2013-04-14ArmPkg/BdsLib: Do not create additional 'cpu' nodes if the 'cpus' node ↵oliviermartin
already exist UEFI must not add additional 'cpu' nodes if the 'cpus' node was already present. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14271 6f19259b-4bc3-4df7-8a09-765794883524
2013-04-14ArmPkg/BdsLib: Replace ARM magic value by a proper defined value.oliviermartin
"ARMH" is the Four-Letter unique identifier used by ARM in the context of the fast SMC identification interface. This patch properly defines this value in a header file instead of using the numeric value directly in the code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14268 6f19259b-4bc3-4df7-8a09-765794883524
2013-04-14ArmPkg/PL390Gic: Do not try to clear spurious interrupts.oliviermartin
If we have a pending spurious interrupt we should not try to clear it, just ignore. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14265 6f19259b-4bc3-4df7-8a09-765794883524
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