summaryrefslogtreecommitdiff
path: root/ArmPkg
AgeCommit message (Collapse)Author
2013-12-10ARM Packages: Removed 'inline' keywordOlivier Martin
'inline' keyword is not supported by the C89 (version used by EDK2). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14957 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10ArmPkg/AArch64Mmu.h: Fix 'Shift is >= width of type'Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14956 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10ArmPkg/ArmDisassemblerLib: Fixed logical/bitwise operator confusionOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14955 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-10ArmPkg/ArmMpCoreInfo.h: Fixed macro definitionOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14954 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg/BdsLib: Fixed the alignment of the relocated Device TreeOlivier Martin
When the Device Tree was loaded above the 32bit address space the operation: *RelocatedFdt = ALIGN ((UINT64)*RelocatedFdt, (UINT32)FdtAlignment); was returning an incorrect address. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14915 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg/DebugPeCoffExtraActionLib: Fixed the printing of the location of the ↵Olivier Martin
EFI modules When loaded above the 32-bit address space the address requires more than 8 characters. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14913 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg/CpuDxe: Removed LR adjustement for SVC callOlivier Martin
The Link Register (LR) does not need adjustement when receiving a Supervisor Call (SVC). Note: SVC might be generated by debuggers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14911 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg: Move definition of ArmIsArchTimerImplemented / ArmReadIdPfrN to ArmLibOlivier Martin
These functions are not chipset specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14908 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPlatformPkg/ArmVExpressPkg: Removed unused PCDs declaration from INF fileOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14907 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-29ARM Packages: Renamed PL390Gic driver into ArmGic driverOlivier Martin
The aim is to make this driver follows the ARM GIC specifications and be implementation independent. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14810 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-24ArmPkg/PL390Gic: Fixed setting of the Interrupt Processor Targets Registers ↵Olivier Martin
when Uniprocessor When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero). So the previous assertion was not correct. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-15ArmPkg/Include/Chipset: Fix translation table address calculations for AARCH64Garrett Kirkendall
TT_ADDRESS_* macros were not casting immediate values to UINTN. This causes shift operations to be off by 32-bits when calculating addresses above 4GB. Any address above 4GB was being improperly calculated. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14777 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-14ArmPkg/CpuDxe: Fixed confusion in AArch64 Table descriptor typesOlivier Martin
Table Descriptor and Level-3 Block entry descriptors have the same translation table type value (ie: 0x3). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14771 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-23ArmPkg/ArmLib: Revert change 'Fixed field shifting in CLIDR_EL1 (AArch64)'Olivier Martin
The shift by 1 on the left was expected. It eases the access to CSSELR and set/way operations where the cache level field is at the BIT1 position. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14704 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-23SemihostFs: Fix check for read-only file or file-openOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14703 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-23ArmPkg/CpuDxe: Fixed the condition that checks if the level-1 descriptor ↵Olivier Martin
points to a level-2 page table Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14700 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-16ArmPkg/ArmLib: Fixed field shifting in CLIDR_EL1 (AArch64)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14677 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-16ArmPkg/CpuDxe: Fixed attribute setting in GetNextEntryAttribute()Olivier Martin
The wrong attribute was used to set the region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14676 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-10ArmPkg/CpuDxe: Exception Handling SP AdjustEugene Cohen
The exception handling support code appears to adjust the stack pointer in the wrong direction. It decrements the stack pointer by 0x60, but this should be an increment (add) for the downward-growing stack. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14646 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-03ArmPkg/CpuPei: Remove unused functions from the driverRoy Franz
The ConfigureMmu() function is unused - the only call to it is commented out, and the functionality has been moved to InitMmu() in MemoryInitPeiLib.c. This change also removes the unused definitions from the file. Change-Id: Ice795bfee25c403142d0c078533f8a46d04f82e9 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Roy Franz <roy.franz@linaro.org> Signed-off-by:: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14621 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/ArmDmaLib: Fixed the calculation of the Base Address of the BufferOlivier Martin
The former calculation 'ALIGN_VALUE(*DeviceAddress - BASE_4KB - 1,BASE_4KB)' did not return the lowest aligned address. Example: *DeviceAddress = 0xB000C001; *DeviceAddress - BASE_4KB - 1 = 0xB000B000; Aligned value = 0xB000B000 + ((0x1000 - 0xB000B000)) & 0xFFF) = 0xB000B000 ... while we where expected 0xB000C000. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14618 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/CpuDxe: Fixed calculation of the Page Table Index (Level 2 Descriptor)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14617 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/ArmLib: Change comment to match code for setting of V bit in SCTLR ↵Roy Franz
register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Roy Franz <roy.franz@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14616 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-21ArmPkg/ArmGicLib.h: Added macro to retrieve the information from the ICCIDROlivier Martin
These macros are helper functions to get the information from the GIC CPU Interface Identification register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14582 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-21ArmPlatformPkg/Sec: Remove SCR and CPTR initialization from SetupExceptionLevel3Olivier Martin
This is already taken care by Sec when PcdTrustzoneSupport = TRUE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14580 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Added support to not set a memory region with the same attributeOlivier Martin
Changing the attribute implies some cache management (clean & invalidate). Preventing the cache management should improve the performance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14568 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Added ConvertSectionAttributesToPageAttributes()Olivier Martin
This helper function converts the section attributes into their page equivalents. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmV7Mmu.h: Added masks to extract attributes from Section and Page ↵Olivier Martin
entries Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14566 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Introduced TT_LAST_BLOCK_ADDRESS()Olivier Martin
This macro return the address of the last entry of a translation table. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14565 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Fixed AArch64 MMU/GCD synchronizationOlivier Martin
- Fix the length used to set the GCD Memory Space attribute - Print a warning message if the given length of a memory space region is not 4KB-aligned Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14562 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: AArch64: Fix wrong comparison of exception typeGirish K S
During the interrupt registration comparison is made against max value of exception types for ARMV7, but in the common handling function the check is made against max value of exceptions types for ARMV8. This can lead to undefined behaviour during registration of interrupts. This patch modifies the registration function to handle only AArch64 exceptions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14561 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-06ArmPkg/ArmV7Mmu.h: Fixed XN bit conversion from section to small/large page ↵Olivier Martin
format Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14523 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-06ARM: Remove NSACR from the common codeOlivier Martin
NSACR (Non-Secure Access Control Register) is AArch32 specific. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14522 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg/ArmLib: Fixed TBLs invalidation in EL1Olivier Martin
'tlb alle1' was used to invalidate the TLBs in EL1. Expect this instruction can only be invoked from EL2. The correct instruction to invalidate TLBs in EL1 is 'tlbi vmalle1' - it invalidates the TLBs of the current VMID. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14509 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg/Library: AArch64 MMU EL1 supportOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14508 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg,ArmPlatformPkg: Free memory allocated by Get.*SpaceMap()Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14507 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg/ArmLib/AArch64: Use the appropriate macros and update commentsOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14506 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-24ArmPkg: Update the AArch64 Image File Machine Type to match the PE/COFF specOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14502 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-24ArmPkg/BdsLib: AArch64 MPCore Linux 'spin-table' boot cache fixHarry Liebel
Clean data cache after initialising mailboxes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14501 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-24ArmPkg/ArmLib/AArch64: Fixed the calculation of the last entry in the ↵Olivier Martin
Translation Table Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14500 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg: Added AArch64 support (missing files)Harry Liebel
Some missing files from the initial AArch64 commit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14488 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg/BdsLib: Added Aarch64 support for booting LinuxHarry Liebel
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14487 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg: Added Aarch64 supportHarry Liebel
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg/CpuDxe: Moved memory mapping functions that are not architecture ↵Olivier Martin
specific to 'CpuMmuCommon.c' Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14482 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-17ArmPkg: Removed the non-used PCD PcdGicPrimaryCoreIdOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14480 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-17ArmPkg/PL390Gic: Populate the GIC Distributor Target Register with the GIC ↵Olivier Martin
CPU ID retrieved from the GIC The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first registers of the GIC CPU Target Registers. The first GIC Distributor Target registers correspond to the SGIs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-16ArmPkg/UncachedMemoryAllocationLib: Removed unused header (Protocol/Cpu.h)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14469 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-15ArmPkg: Fix UncachedFreeAlignedPages in UncachedMemoryAllocationLibEugene Cohen
Route both the setting and restoring of cacheability through DXE Services/GCD and stop using the CPU AP directly. The patch also removes all references to the CPU AP which eliminates the need for a library constructor. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Senthil Ramakrishnan <senthil.ramakrishnan@hp.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14468 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-27ArmPkg/BdsLib: Fixed manipulation of the Memory Map returned by GetMemoryMap()Olivier Martin
The UEFI specification mandates that software uses the DescriptorSize returned by the GetMemoryMap() function to find the start of each EFI_MEMORY_DESCRIPTOR in the MemoryMap array. This allows for future expansion of the EFI_MEMORY_DESCRIPTOR. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14447 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-27ArmPkg/ArmLib: Marked functions as 'STATIC' if not exposed outside of the ↵Olivier Martin
scope of the source file Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14446 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 01:10:44 +0000