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2017-04-27ArmPlatformPkg: Remove unused PackageGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-04-06ArmPlatformPkg/PL111LcdArmVExpressLib: use write-combine mapping for VRAMArd Biesheuvel
Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Instead of manipulating the memory attributes directly, use the SetMemorySpaceAttributes() DXE services, which validates the attributes against the capabilities of the region before making the actual change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-04-06ArmPlatformPkg/HdLcdArmVExpressLib: use write-combine mapping for VRAMArd Biesheuvel
Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Instead of manipulating the memory attributes directly, use the SetMemorySpaceAttributes() DXE services, which validates the attributes against the capabilities of the region before making the actual change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-04-06ArmPlatformPkg/PL111LcdArmVExpressLib: fix incorrect FreePool () callArd Biesheuvel
When we fail to modify the memory attributes for the VRAM allocation, the allocation - which was made using AllocatePages() - is freed using FreePool(). This is incorrect by itself, but it masks a second bug, i.e., that the address of the allocation is not in VramBaseAddress but in *VramBaseAddress. So fix both issues. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-04-06ArmPlatformPkg/HdLcdArmVExpressLib: fix incorrect FreePool () callArd Biesheuvel
When we fail to modify the memory attributes for the VRAM allocation, the allocation - which was made using AllocatePages() - is freed using FreePool(). This is incorrect by itself, but it masks a second bug, i.e., that the address of the allocation is not in VramBaseAddress but in *VramBaseAddress. So fix both issues. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-04-06ArmPlatformPkg/FVP: map motherboard VRAM as uncached memoryArd Biesheuvel
The VRAM of the PL111 on the FVP Base/Foundation models is described as device memory rather than uncached memory, which is not an accurate description of the nature of the region (i.e., a framebuffer), and may result in problems when using accelerated string routines to access the region, since this may legally involve unaligned accesses or DC ZVA instructions, which are not allowed on device mappings. So split of the 8 MB VRAM region into a separate region, and map it using memory attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-01-26ArmPlatformPkg/TZASC: Allow specifying subregions to be disabledBhupesh Sharma
ARM TZASC-380 IP provides a mechanism to split memory regions being protected via it into eight equal-sized sub-regions. A bit-setting allows the corresponding subregion to be disabled. Several NXP/FSL SoCs support the TZASC-380 IP block and allow the DDR connected via the TZASC to be partitioned into regions having different security settings and also allow subregions to be disabled. This patch enables this support and can be used for SoCs which support such a partition of DDR regions. Details of the 'subregion_disable' register can be viewed here: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0431c/CHDIGDCI.html Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Bhupesh Sharma <bhupesh.sharma@nxp.com> [bhupesh.linux@gmail.com : Added gmail ID as NXP one is no longer valid] Signed-off-by: Bhupesh Sharma <bhupesh.linux@gmail.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-11-25ArmPlatformPkg: Fix VE RTSM mem map descriptor countSami Mujawar
The number of memory map entries used exceeded the allocated count, thereby causing memory corruption. Fixed the number of Virtual Memory Map Descriptors allocated in describing the RTSM Memory Map. Also added an assert to confirm that the descriptor count has not been exceeded, in the hope that it may help highlight the problem should a new entry be added. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-11-25ArmPlatformPkg: Reformat VE Memory Map codeEvan Lloyd
This change is purely cosmetic, with no functional impact, and only exists to isolate cosmetic changes from a functional fix. Some indentation is adjusted. Overlength lines are re-flowed. alignment on = is adjusted as some lines exceeded 80 columns. if statement converted to conditional assignment. Redundant re-calculation of CacheAttributes removed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-09-08ArmPlatformPkg: remove EFI_MEMORY_UC attribute from normal memoryArd Biesheuvel
On ARM systems, mapping normal memory as device memory may have unintended side effects, given that unaligned accesses or loads and stores with special semantics (e.g., load/store exclusive) may fault or may not work as expected. Similarly, DC ZVA instructions are only supported on normal memory, not device memory. So remove the EFI_MEMORY_UC attribute that we set by default on system RAM. If any region requires this attribute, it is up to the driver to set this attribute, and to ensure that no offending operations are performed on it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-08ArmPkg ArmPlatformPkg ArmVirtPkg: ARM GICv2/v3 Base Address width fix-upDennis Chen
According to the ACPI 6.0/6.1 spec, the physical base address of GICC, GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC base address PCDs to 64-bit, and fix up all users. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Dennis Chen <dennis.chen@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-08-11ArmPlatformPkg/ArmVExpressPkg: switch to ASM_FUNC() asm macroArd Biesheuvel
Annotate functions with ASM_FUNC() so that they are emitted into separate sections. While we're at it, replace some inefficient uses of LoadConstantToReg() Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-08-11ArmPlatformPkg RVCT: drop dependency on GCC macro libraryArd Biesheuvel
The RVCT .asm files include AsmMacroIoLib.h only for the definition of LoadConstantToReg (), which makes it tedious to make change to that file without the risk of making the RVCT assembler unhappy. So simply replace LoadConstantToReg() with mov32, which does the right thing in all cases. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2015-12-14ArmPlatformPkg/RTSM: use declared PPI rather than module local varArd Biesheuvel
We can refer to gArmMpCoreInfoPpiGuid directly if we declare it under [Ppis] in the library's .inf so there is no need to copy it into a module local variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19243 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-14ArmPlatformPkg/CTA9x4: use declared PPI rather than module local varArd Biesheuvel
We can refer to gArmMpCoreInfoPpiGuid directly if we declare it under [Ppis] in the library's .inf so there is no need to copy it into a module local variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19242 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-14ArmPlatformPkg/CTA15-A7: use declared PPI rather than module local varArd Biesheuvel
We can refer to gArmMpCoreInfoPpiGuid directly if we declare it under [Ppis] in the library's .inf so there is no need to copy it into a module local variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19241 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-18ArmVExpressPkg/ArmVExpressLibRTSM: map NOR flash as normal memoryArd Biesheuvel
Some users of this library (i.e., FVP-AArch64 and RTSM-A15_MPCore) may be built to execute straight from NOR flash. Since device mappings should have the XN attribute set (according to the architecture), mapping the NOR flash as a device may prevent it from being executable. Since the NOR flash DXE driver is perfectly capable of setting the correct attributes for the region it needs to write to, and since we will be executing from DRAM by that time anyway, we can simply map the NOR flash as normal memory initially. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18890 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-06ArmPlatformPkg/RTSM: remove obsolete Foundation model librariesArd Biesheuvel
These are no longer used by any platform in the tree, nor are they of any significance to any out of tree platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18571 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-10ArmPlatformPkg/ArmVExpressPkg: add ArmPlatformSysConfigLib for runtimeArd Biesheuvel
This adds a ArmPlatformSysConfigLib implementation that is usable by DXE_RUNTIME_DRIVER modules. Since the system registers that this library encapsulates are not usable at runtime, this driver allows access to those registers only at boot time. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17925 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-08ArmVExpressPkg: restrict ArmVExpressSysConfigLib to SEC and DXE_DRIVERArd Biesheuvel
Since ArmVExpressSysConfigLib cannot be supported at runtime, restrict its use to the types of modules that are currently using it legally. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17382 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-25ArmPlatformPkg/ArmVExpressPkg: Added support to differentiate ARMv8 FVP variantsOlivier Martin
There are three FVP variants for the Base and Foundation models: - model with GICv2 legacy memory map (same location as the Versatile Express model) - model with GICv2 and Base model memory map - model with GICv3 and Base model memory map The new code detects the variants to load the appropriate device tree. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16932 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-25ArmPlatformPkg/ArmVExpressDxe: Identify the current platformOlivier Martin
Add a function to ArmVExpressDxe to identify the current platform we are running on. This includes ARM32 and AArch64 models and hardware. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16931 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-11ArmPlatformPkg: Increase more ARM address Pcd entries to 64-bit.Leif Lindholm
Some AArch64 platforms have RAM and flash devices >4GB. Update some additional Pcd entries to 64-bit, and change the corresponding PcdGet32 calls to PcdGet64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16325 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-01ARM Packages: Removed unused PcdArmPrimaryCoreOlivier Martin
This PCD has been replaced by ArmPlatformIsPrimaryCore() function. Althrough this PCD is still used in some occasions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16026 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-26ARM Packages: Replace tabs by spaces for indentationRonald Cron
Replace tabs by spaces for indentation to comply to EDK2 coding standards. Done in files with extension ".S", ".c", ".h", ".asm", ".dsc", ".inc", "*.inf", "*.dec" or ".fdf" and located in ArmPkg, ArmPlatformPkg, EmbeddedPkg, BeagleBoardPkg or Omap35xxPkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15901 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19ARM Packages: Removed trailing spacesRonald Cron
Trailing spaces create issue/warning when generating/applying patches. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-19ARM Packages: Corrected non-DOS line endingsRonald Cron
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ronald Cron <ronald.cron@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15832 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-29ArmPlatformPkg/ArmVExpressPkg: Fix armcc warning causing build failureHarry Liebel
- Variable may be used before being set Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Reviewed-By: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15719 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Introduced helper functions to access the GIC controllerOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15621 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-20ARM Packages: Fixed missing braces (the warning was disabled by GCC)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15578 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: Use AND instead of BIC instruction with immediateBrendan Jackman
AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a AND with the immediate inverted, but Clang's integrated assembler emits an error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: use GCC_ASM_EXPORT to export functionsBrendan Jackman
This ensures the .type directive is used to mark them as function symbols Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: Remove GCC filter for AARCH64 assembly filesBrendan Jackman
Some non-GCC toolchain might support the GNU assembly language. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15504 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ArmPlatformPkg/ArmVExpressSecLibRTSM: Only use extended name of system ↵Brendan Jackman
registers for GCC Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15501 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-14ArmPlatformPkg/ArmVExpressLibRTSM: Added support for the additional 6GB ↵Olivier Martin
memory of DRAM on Foundation Model The FVP Foundation model has additional DRAM regions at 0x08_8000_0000. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15464 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-11ArmPlatformPkg/ArmVExpressLibRTSM: Added support for the additional 2GB ↵Olivier Martin
memory of DRAM on FVP The FVP Base and Foundation models have additional DRAM regions at 0x08_8000_0000. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15461 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-11ArmPlatformPkg/ArmVExpressLibRTSM: Removed unused dead codeOlivier Martin
This code is only specific to the ARM Versatile Express hardware board. There is no concept of logic tile on the FVP model. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15460 6f19259b-4bc3-4df7-8a09-765794883524
2014-02-24ARM Packages: Include 'AsmMacroIoLibV8.h' instead of the 32bit versionOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15256 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-10ArmPkg/ArmPkg.dec: Redefined PcdSystemMemory(Base|Size) as UINT64Olivier Martin
The System Memory region might be out of the 32-bit memory space. This change has been validated on the FVP AArch64 model using 4GB of DRAM at 0x8_0000_0000: - # System Memory (2GB) - gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 - gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000 + # System Memory (4GB) + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000 + gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000 EFI Shell and Linux kernel boot successfully. Note: This change has not been validated on AArch32. I expect some early assembly code to not work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
2013-12-06ArmPlatformPkg: Fix and Implement ArmPlatformGetPrimaryCoreMpIdOlivier Martin
- Used correct PCD - Implement the function for AArch64, BeagleBoard, CTA15A7 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14937 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPlatformPkg/ArmVExpressLibCTA9x4: Fixed the initial secondary core ↵Olivier Martin
bringup when remapping DRAM at 0x0 If the DRAM is remapped at 0x0 then we need to wake up the secondary cores from wfe (waiting for the memory to be initialized) as the instruction is still in the remapped flash region at 0x0 to make them jumping into the C-code which lives in the NOR1 at 0x44000000 before the region 0x0 is remapped as DRAM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14910 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPlatformPkg/ArmVExpressPkg: Removed unused PCDs declaration from INF fileOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14907 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-05ArmPlatformPkg: Added initial support for the FVP Base and Foundation ModelsOlivier Martin
The FVP Base Model has GICv3 support. UEFI SEC does limited configuration of GICv3 if present. This is required for Linux to use GICv3. UEFI itself uses the GICv3 in legacy mode (GICv2). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14824 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-21ArmPlatformPkg/ArmVExpressPkg: Added 'EfiResetPlatformSpecific' to ↵Olivier Martin
ResetSystemLib This value was missing from the switch on 'ResetType'. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14583 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPlatformPkg/ArmVExpressPkg: Add System ID of FVP models to VE LCD driver.Olivier Martin
- Setting DVI fails on VE models. The FVP models behave the same. These have updated SYS ID numbers and they need to be added to the driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14564 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-19ArmPlatformPkg: Added Aarch64 Foundation ModelHarry Liebel
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14495 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPlatformPkg: Added support for Aarch64 AEM RTSM modelHarry Liebel
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14490 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-01ArmPlatformPkg/ArmVExpressLibCTA15-A7: Mapped the extra 1GB of DRAM in the MMUOlivier Martin
ARM Versatile Express TC2 Core Tile has two profiles: the 1GB DRAM core tile or the 2GB DRAM core tile profiles. By default UEFI assumes, it is the 1GB core tile. In case of 2GB DRAM it declares this additional 1GB resource system memory to UEFI. But the previous code did not map this memory in the MMU Page Table. So, the memory was allocatable by UEFI modules, but was not accessible by the CPU (because not mapped). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Leif Lindholm <Leif.Lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14449 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-21ArmPlatformPkg/ArmVExpressPkg: Add Shutdown supportRyan Harkin
LibResetSystem was performing a cold reboot for both reboot and shutdown. This patch updates LibResetSystem to pass SYS_CFG_SHUTDOWN to the microcontroller when called wit EfiResetShutdown. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14438 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-19ArmPlatformPkg/ArmVExpressLibCTA15-A7: Fixed ARM Toolchain buildOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14429 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-05 02:15:59 +0000