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128MB of DRAM
Linux and its DTB required to be loaded in the first 128MB of the system memory.
Moving UEFI firmware above this limit ensures some XIP runtime code (part of the
UEFI firmware) are not overwritten when loading Linux kernel.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15168 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15166 6f19259b-4bc3-4df7-8a09-765794883524
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The edk2 tree mandates CRLF line terminators. Earlier patches added some
lines with LF terminators. Clean them up.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15132 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Reece R. Pollack <reece.pollack@linaro.org>
Signed-off-by: Steven Kinney <steven.kinney@linaro.org>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15131 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Reece R. Pollack <reece.pollack@linaro.org>
Signed-off-by: Steven Kinney <steven.kinney@linaro.org>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15130 6f19259b-4bc3-4df7-8a09-765794883524
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networking and PXE boot.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15129 6f19259b-4bc3-4df7-8a09-765794883524
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ARM Development Boards
This is the filesystem created by the microcontroller on NOR Flash of the ARM Versatile
Express Development Board.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15126 6f19259b-4bc3-4df7-8a09-765794883524
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emulation
This patch adds an EDK2_ARMVE_SUPPORT_QEMU macro that can be defined at build
time to build an image that supports QEMU. The default build is unchanged and
builds the RTSM configuration.
QEMU only models fixed size blocks within a flash device, and the RTSM
configuration stores EFI variables in the smaller boot blocks of the
flash. When built for QEMU the larger blocks are used that QEMU properly
emulates.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15125 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15123 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15122 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15121 6f19259b-4bc3-4df7-8a09-765794883524
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The System Memory region might be out of the 32-bit memory space.
This change has been validated on the FVP AArch64 model using 4GB
of DRAM at 0x8_0000_0000:
- # System Memory (2GB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ # System Memory (4GB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000
EFI Shell and Linux kernel boot successfully.
Note: This change has not been validated on AArch32. I expect some
early assembly code to not work.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
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The line endings for EDK2 source files should be CRLF.
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15057 6f19259b-4bc3-4df7-8a09-765794883524
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Right now the ARM Platform driver does not do much, but
I expect to move most platform specific code into platform
specific driver in the future.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
v5:
- ensure / document that the VIRTIO_BLK_DEVICE_PATH structure must be
packed
- fix whitespace damage in definition of "mVirtioBlockDevicePath"
- the platform driver is added to all platform DSC and FDF files in the
previous patch; this patch focuses on virtio only
Change-Id: I3505bfc5b31085b8017bd9e6895a155bd7a2eee9
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14981 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
v5:
- For uniformity, add the empty driver to
ArmVExpress-RTSM-AEMv8Ax4-foundation.* too in this patch, not just
ArmVExpress-RTSM-AEMv8Ax4.*. V4 added the empty driver to
ArmVExpress-RTSM-AEMv8Ax4-foundation.* not sooner than the next patch,
fusing it with other (= virtio) functionality. Let's split these changes
cleanly.
Change-Id: I7d635011c8d3ac59097c728b7c7786d8677c80cb
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14980 6f19259b-4bc3-4df7-8a09-765794883524
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stacks PCDs
We do not have (Secure) Monitor mode on AArch64.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14939 6f19259b-4bc3-4df7-8a09-765794883524
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- Used correct PCD
- Implement the function for AArch64, BeagleBoard, CTA15A7
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14937 6f19259b-4bc3-4df7-8a09-765794883524
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PcdPrePiCpuMemorySize & PcdPrePiCpuIoSize
This change introduces default values for the PCDs PcdPrePiCpuMemorySize & PcdPrePiCpuIoSize.
These values are for the architectures ARM, AARCH64, IA32 and X64.
The redefinition of these PCDs (with the same default values) have been removed from the DSC files.
Note: the default value for AARCH64 was 32. It was preventing to allocate buffer above the 32bit
address space.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14914 6f19259b-4bc3-4df7-8a09-765794883524
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bringup when remapping DRAM at 0x0
If the DRAM is remapped at 0x0 then we need to wake up the secondary cores from wfe
(waiting for the memory to be initialized) as the instruction is still in the remapped
flash region at 0x0 to make them jumping into the C-code which lives in the NOR1 at 0x44000000 before
the region 0x0 is remapped as DRAM.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14910 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14907 6f19259b-4bc3-4df7-8a09-765794883524
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If EDK2_ARMVE_STANDALONE is not defined then the value is set to 1.
The developer has to explicit set the macro to zero to build a non standalone build.
It means this macro is always defined.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14906 6f19259b-4bc3-4df7-8a09-765794883524
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The FVP Base Model has GICv3 support.
UEFI SEC does limited configuration of GICv3 if present. This is required for Linux to use GICv3.
UEFI itself uses the GICv3 in legacy mode (GICv2).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14824 6f19259b-4bc3-4df7-8a09-765794883524
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The aim is to make this driver follows the ARM GIC specifications and
be implementation independent.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14810 6f19259b-4bc3-4df7-8a09-765794883524
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AArch64 Linux kernel
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14627 6f19259b-4bc3-4df7-8a09-765794883524
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modified the comment which can mislead.
The "ldr r0, [r1]" is overrided with a immediate "mov ro, #3"
instruction. This mov instruction will over write the contents
of the ro register. So replacing 'mov' by 'orr' instruction would
prevent to override the original value.
This patch assumes mov is the right instruction to be retained
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Girish K S <ks.giri@samsung.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14606 6f19259b-4bc3-4df7-8a09-765794883524
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ResetSystemLib
This value was missing from the switch on 'ResetType'.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14583 6f19259b-4bc3-4df7-8a09-765794883524
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AArch64 platforms
This PCD ensures the transition from EL3 to EL2 in ArmPlatformPkg/Sec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14579 6f19259b-4bc3-4df7-8a09-765794883524
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- Setting DVI fails on VE models. The FVP models behave the same.
These have updated SYS ID numbers and they need to be added to the
driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14564 6f19259b-4bc3-4df7-8a09-765794883524
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the list of DEBUG_*
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14563 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14495 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14490 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14480 6f19259b-4bc3-4df7-8a09-765794883524
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ARM Versatile Express TC2 Core Tile has two profiles: the 1GB DRAM core tile or
the 2GB DRAM core tile profiles.
By default UEFI assumes, it is the 1GB core tile. In case of 2GB DRAM it declares
this additional 1GB resource system memory to UEFI. But the previous code did
not map this memory in the MMU Page Table.
So, the memory was allocatable by UEFI modules, but was not accessible by the CPU
(because not mapped).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Leif Lindholm <Leif.Lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14449 6f19259b-4bc3-4df7-8a09-765794883524
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The syntax '!ifdef $(MACRO)' is deprecated and should be replaced by '!ifdef MACRO'.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14440 6f19259b-4bc3-4df7-8a09-765794883524
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This patch changes the Versatile Express A9 BSP to build with
EDK2_ARMVE_STANDALONE=1 as the default option.
The user may then specify zero if they wish to build the non-standalone
version.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14439 6f19259b-4bc3-4df7-8a09-765794883524
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LibResetSystem was performing a cold reboot for both reboot and
shutdown.
This patch updates LibResetSystem to pass SYS_CFG_SHUTDOWN to the
microcontroller when called wit EfiResetShutdown.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14438 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14429 6f19259b-4bc3-4df7-8a09-765794883524
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The size of the FDs did not match the FD layout.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14426 6f19259b-4bc3-4df7-8a09-765794883524
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The FDT name are the one from Linaro release.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14348 6f19259b-4bc3-4df7-8a09-765794883524
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This function allows platform to do any specific actions prior to
the start the PEI phase.
For instance, this function could be used by some platforms to initialize clocks that
are required at the early stage of the PEI phase.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Acked-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14347 6f19259b-4bc3-4df7-8a09-765794883524
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ArmPlatformGetCorePosition()
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Acked-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14346 6f19259b-4bc3-4df7-8a09-765794883524
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ArmPlatformGetPrimaryCoreMpId returns the MPID of the primary core.
The primary core might not be known at build time (eg: the platform allows
the boot CPU to be changed through board config).
This function is used during the secondary core stack initialization to know
the position of the secondary core in the SoC.
A secondary core that is at the position N, with N greater than the primary
core position, will be at the position N-1 in the list of secondary stacks
(the primary core has its own separate bigger stack).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Acked-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14345 6f19259b-4bc3-4df7-8a09-765794883524
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Checking if a core if the primary/boot core used to be done with the macro
IS_PRIMARY_CORE().
Some platforms exposes configuration registers to change the primary core.
Replacing the macro IS_PRIMARY_CORE() by ArmPlatformIsPrimaryCore() allows
some flexibility in the way to check the primary core.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Ryan Harkin <ryan.harkin@linaro.org>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14344 6f19259b-4bc3-4df7-8a09-765794883524
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ArmPlatformGetAdditionalSystemMemory() function wasn't used anywhere in UEFI.
This patch deletes it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14270 6f19259b-4bc3-4df7-8a09-765794883524
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Only the Cortex A9 based platforms have an external L2 controller.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14269 6f19259b-4bc3-4df7-8a09-765794883524
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NOR flash.
Setting bit4 of SCC register 48 now triggers the erasing of the memory region
reserved for variable storage in NOR flash and the restoration of the default
headers in flash.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14177 6f19259b-4bc3-4df7-8a09-765794883524
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Formerly only the header was defined and it was expecting the SerialPortExtLib
interface to be implemented by SerialPortLib if supported. This behaviour was
not conform to the EDK2 framework.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14173 6f19259b-4bc3-4df7-8a09-765794883524
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A ArmSmcLib Null implementation has also been added for CPU without the ARM Security
Extension (Trustzone support).
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14164 6f19259b-4bc3-4df7-8a09-765794883524
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This large code change only modifies the line endings to be CRLF to be
compliant with the EDK2 coding convention document.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524
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A15x2_A7x3
This is the big.LITTLE test chip for ARM Versatile Express Motherboard.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13775 6f19259b-4bc3-4df7-8a09-765794883524
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