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This patchs adds support to VirtFdtDxe for the Xen DT node which
contains the base address of the Grant Table. This data is communicated
to XenBusDxe using a XENIO_PROTOCOL instance.
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16980 6f19259b-4bc3-4df7-8a09-765794883524
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Instead of using a dynamic PCD, store the device tree address in a HOB
so that we can also run under a configuration that does not support
dynamic PCDs.
This also adds MemoryAllocationLib to the [LibraryClasses] section of
ArmVirtualizationPlatformLib/ArmVirtualizationPlatformLib.inf, as this
dependency was formerly satisfied transitively through one of the
library dependencies that were dropped.
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16959 6f19259b-4bc3-4df7-8a09-765794883524
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This adds support for detecting the presence of a GICv3 interrupt
controller from the device tree, and recording its distributor and
redistributor base addresses in their respective PCDs.
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16956 6f19259b-4bc3-4df7-8a09-765794883524
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The DT binding for the ARM generic timer describes the secure,
non-secure, virtual and hypervisor timer interrupts, respectively.
However, under virtualization, only the virtual timer is usable, and
the device tree may omit the hypervisor timer interrupt. (Other timer
interrupts cannot be omitted simply due to the fact that the virtual
timer is listed third)
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16953 6f19259b-4bc3-4df7-8a09-765794883524
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In the Linux kernel tree,
"Documentation/devicetree/bindings/pci/host-generic-pci.txt" describes the
device tree bindings of a Generic PCI host controller.
Recent QEMU patches from Alexander Graf implement such a controller on the
"virt" machine type of qemu-system-(aarch64|arm):
pcie@10000000 {
//
// (devfn<<8, 0, 0) PCI irq
// ---------------- -------
interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
// gic irq
// (devfn<<8, 0, 0) pin+1 phandle (type, nr, level)
// ---------------- ----- -------- -----------------
interrupt-map = < 0x0 0x0 0x0 0x1 0x8001 0x0 0x3 0x4
0x0 0x0 0x0 0x2 0x8001 0x0 0x4 0x4
0x0 0x0 0x0 0x3 0x8001 0x0 0x5 0x4
0x0 0x0 0x0 0x4 0x8001 0x0 0x6 0x4
0x800 0x0 0x0 0x1 0x8001 0x0 0x4 0x4
0x800 0x0 0x0 0x2 0x8001 0x0 0x5 0x4
0x800 0x0 0x0 0x3 0x8001 0x0 0x6 0x4
0x800 0x0 0x0 0x4 0x8001 0x0 0x3 0x4
0x1000 0x0 0x0 0x1 0x8001 0x0 0x5 0x4
0x1000 0x0 0x0 0x2 0x8001 0x0 0x6 0x4
0x1000 0x0 0x0 0x3 0x8001 0x0 0x3 0x4
0x1000 0x0 0x0 0x4 0x8001 0x0 0x4 0x4
0x1800 0x0 0x0 0x1 0x8001 0x0 0x6 0x4
0x1800 0x0 0x0 0x2 0x8001 0x0 0x3 0x4
0x1800 0x0 0x0 0x3 0x8001 0x0 0x4 0x4
0x1800 0x0 0x0 0x4 0x8001 0x0 0x5 0x4>;
#interrupt-cells = <0x1>;
//
// child base cpu base
// type address address size
// --------- -------------- -------------- --------------
ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000
0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>;
//
// PCIe config PCIe config
// space base space size
// -------------- -------------
reg = <0x0 0x3f000000 0x0 0x1000000>;
//
// allowed bus numbers; inclusive range
//
bus-range = <0x0 0xf>;
#size-cells = <0x2>;
#address-cells = <0x3>;
device_type = "pci";
compatible = "pci-host-ecam-generic";
};
Parse those properties of the compatible="pci-host-ecam-generic" node into
PCDs that are relevant for PCI enumeration in edk2:
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress controls
MdePkg/Library/BasePciExpressLib,
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration controls
OvmfPkg/AcpiPlatformDxe at this point,
- the rest have been introduced earlier in this patchset, and will control
PCI range checks and translation.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16894 6f19259b-4bc3-4df7-8a09-765794883524
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Installing VenHw() device paths with this GUID, for the virtio-mmio
transports that we detect, enables other modules to recognize those
VenHw() nodes. (Note that the actual value doesn't change.)
In addition, to avoid reusing GUIDs in unrelated contexts, detach the
driver's FILE_GUID from its previous value.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16573 6f19259b-4bc3-4df7-8a09-765794883524
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Qemu's firmware configuration interface for ARM consists of two MMIO
registers, a 16-bit selector, and a 64-bit data register that allows the
guest to transfer data with 8, 16, 32, and 64-bit wide accesses. Parse the
base address from the DTB, and expose the registers to the rest of DXE via
dynamic PCDs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16566 6f19259b-4bc3-4df7-8a09-765794883524
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Only ArmVirtualizationPkg based platforms are expected to use
the dynamic method to choose between SMC and HVC to invoke PSCI.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16204 6f19259b-4bc3-4df7-8a09-765794883524
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This driver enumerates the device nodes in the device tree located at the
base address passed in gArmTokenSpaceGuid.PcdDeviceTreeBaseAddress, and
installs drivers for devices it cares about (GIC interrupt controller, RTC,
architected timer interrupt)
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16137 6f19259b-4bc3-4df7-8a09-765794883524
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