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in the entrypoint
The stack size in the entrypoint (ie: $ARCH/ModuleEntryPoint.S) is calculated such as
StackSize = PrimaryCoreStack + (core_count - 1) * SecondaryCoreStack
While we were declaring the stacksize into the stack hob as:
StackSize = PrimaryCoreStack + (cluster * 8) * SecondaryCoreStack
If the number of cluster (ie: PcdClusterCount) were not defined correctly then
the stack size declaration were not correct.
It could cause stack corruption if the allocator allocates memory in this range.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15431 6f19259b-4bc3-4df7-8a09-765794883524
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The System Memory region might be out of the 32-bit memory space.
This change has been validated on the FVP AArch64 model using 4GB
of DRAM at 0x8_0000_0000:
- # System Memory (2GB)
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x80000000
+ # System Memory (4GB)
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x800000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000
EFI Shell and Linux kernel boot successfully.
Note: This change has not been validated on AArch32. I expect some
early assembly code to not work.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15093 6f19259b-4bc3-4df7-8a09-765794883524
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- Disable data cache on all cores.
- Do not clean caches as there might be junk in them, invalidate only.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14527 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Harry Liebel <Harry.Liebel@arm.com>
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14489 6f19259b-4bc3-4df7-8a09-765794883524
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Checking if a core if the primary/boot core used to be done with the macro
IS_PRIMARY_CORE().
Some platforms exposes configuration registers to change the primary core.
Replacing the macro IS_PRIMARY_CORE() by ArmPlatformIsPrimaryCore() allows
some flexibility in the way to check the primary core.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Ryan Harkin <ryan.harkin@linaro.org>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14344 6f19259b-4bc3-4df7-8a09-765794883524
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On ARM PLatforms, there is no standard way to know how many cores are
available on the platform.
This PCD is expected to contain this number.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13769 6f19259b-4bc3-4df7-8a09-765794883524
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In case a DebugAgent library is supported for a specific debugger, we would
expect the exception be caught by DebugAgentLib.
The DebugAgentBaseLib exposes the cause of the exception to the user in the
Serial Terminal.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13766 6f19259b-4bc3-4df7-8a09-765794883524
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Registered the gArmMpCoreInfoGuid Data Hob.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13497 6f19259b-4bc3-4df7-8a09-765794883524
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ArmCpuSynchronizeSignal by sev & wfe
Previsouly the synchronization of MpCore was using the SGI (Software
Generated Interrupt) to synchronize MpCore during the early boot.
This commit replaced this mechanism by the more appropriate SEV/WFE
instructions (Send/Wait Event instructions).
That also eases the port to a new cpu/platform.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13249 6f19259b-4bc3-4df7-8a09-765794883524
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- ArmPlatformNormalInitialize() has been renamed into ArmPlatformInitialize()
- Make the function be called at the early stage of the PEI phase as some
platforms require their interconnects or clocks to be initialize before any
access to Timers or UARTs.
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13245 6f19259b-4bc3-4df7-8a09-765794883524
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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13139 6f19259b-4bc3-4df7-8a09-765794883524
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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12726 6f19259b-4bc3-4df7-8a09-765794883524
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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12645 6f19259b-4bc3-4df7-8a09-765794883524
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region settings
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12638 6f19259b-4bc3-4df7-8a09-765794883524
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These info are:
- ClusterId, CoreId
- MailBox Set/Get/Clear address
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12423 6f19259b-4bc3-4df7-8a09-765794883524
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This library hides where the 'XIP' Global Variable are located in the memory.
It is expected the Sec/PrePi modules define the Global Variable area through
the GlobalVariable HOB.
The ArmPlatformGlobalVariableLib library allows access to global variables by
their offsets in this region.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12420 6f19259b-4bc3-4df7-8a09-765794883524
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In PrePi the StackBase is automatically calculated from the top of the memory.
The information is now passed from the assembly files to the C code.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12418 6f19259b-4bc3-4df7-8a09-765794883524
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In the previous version, every cores had the same stack size.
To avoid to waste memory with secondary core stacks, the primary core stack
size is now different from the secondary cores stack size.
These are the Stack PCDs and their default values:
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000
gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0
gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12415 6f19259b-4bc3-4df7-8a09-765794883524
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On MpCore system, the primary core can now be any core of the system.
To identify the primary core, you can use 'gArmTokenSpaceGuid.PcdArmPrimaryCoreMask'
and 'gArmTokenSpaceGuid.PcdArmPrimaryCore'.
These PCDs by default use the ClusterId and CoreId to identify the core. And the
primary core is defined as the ClusetrId=0 and CoreId=0.
The helper macros are: IS_PRIMARY_CORE(MpId), GET_CORE_ID(MpId), GET_CLUSTER_ID(MpId),
GET_CORE_POS(MpId), PRIMARY_CORE_ID.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12412 6f19259b-4bc3-4df7-8a09-765794883524
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Arm Packages: Fixed mispelling
Arm Packages: Reduced warnings all over the code
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12407 6f19259b-4bc3-4df7-8a09-765794883524
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PrePeiHobListPointerLib function
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12166 6f19259b-4bc3-4df7-8a09-765794883524
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This second initialization does not make sense in this context.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12164 6f19259b-4bc3-4df7-8a09-765794883524
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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12001 6f19259b-4bc3-4df7-8a09-765794883524
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In the former memory model, the UEFI firmware was expected to be located
at the top of the system memory. Stacks & Pi memory regions were set below
the firmware.
On some platform, the UEFI firmware could be shadowed by the ROM firmware
(case of the BeagleBoard) and in some cases the firmware is copied at the
beginning of the system memory.
With this new memory model, stack and Pi/DXE memory regions are set at the
top of the system memory wherever the UEFI firmware is located in the memory
map.
Because DXE core does not support shadowed firmwares, the system memory covered
by the UEFI firmware is marked as 'Non Present' to avoid to be overlapped by
DXE allocations.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11992 6f19259b-4bc3-4df7-8a09-765794883524
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Other compiler version ... other warnings
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11970 6f19259b-4bc3-4df7-8a09-765794883524
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This module should handle the Pre PI phase before the DXE core is
executed when there is no PEI Core support.
It declares the required information needed by the DXE core through HOBs.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11949 6f19259b-4bc3-4df7-8a09-765794883524
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