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The patch reads a valid MAC address from the Juno IOFPGA registers
and pushes it into onboard Marvell Yukon NIC.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The number of memory map entries used exceeded the allocated count,
thereby causing memory corruption.
Fixed the number of Virtual Memory Map Descriptors allocated in
describing the RTSM Memory Map. Also added an assert to confirm
that the descriptor count has not been exceeded, in the hope that it may
help highlight the problem should a new entry be added.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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This change is purely cosmetic, with no functional impact, and only
exists to isolate cosmetic changes from a functional fix.
Some indentation is adjusted.
Overlength lines are re-flowed.
alignment on = is adjusted as some lines exceeded 80 columns.
if statement converted to conditional assignment.
Redundant re-calculation of CacheAttributes removed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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When CMD6 & ACMD51 are added into identifying SD process, PL180
should also support CMD6 & ACMD51. Otherwise, it will hang when
system tries to read expected data.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
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Get rid of functions that are no longer available when defining
DISABLE_NEW_DEPRECATED_INTERFACES
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This module contains an implementation of the Android Fastboot Platform
protocol. So follow common Tianocore practice, and duplicate the per-method
comment blocks from the interface definition into the implementation.
In addition, let's make all methods and the procotol struct STATIC, given
that they are never referenced via external linkage.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
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Bring the RVCT version of the PrePi entry point code in line with the
GCC version, by using a relative rather than an absolute reference to
the mSystemMemoryEnd variable.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Get rid of functions that are no longer available when defining
DISABLE_NEW_DEPRECATED_INTERFACES
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This is no longer used, and does not belong in a reference code base,
so remove it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
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While most compilers happily allow arithmetic on void pointer,
the RVCT compiler does not, and throws the following warning for
NorFlashDxe:
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.c(894,48) :
error #1254-D: arithmetic on pointer to void or function type
Since the expression in question involves a cast from UINTN to VOID*,
simply add some parentheses to eliminate this warning.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The global variable mSystemMemoryEnd is initialized by PrePi only if
it has not been initialized by ArmPlatformPeiBootAction(). This allows
platforms executing under, e.g., ARM Trusted Firmware to dynamically
reserve a window at the top of memory that will be used by the secure
firmware.
However, PrePi is a SEC module, and writing to a global variable
violates the SEC constraints, since SEC and PEI may execute from NOR
flash.
So instead, initialize mSystemMemoryEnd statically. This will ensure
it holds the correct value for all implementations where the value
is not overridden, but still allows it to be overridden during the
call to ArmPlatformPeiBootAction().
Note that this patch also fixes a latent bug on 32-bit platforms where
a value of mSystemMemoryEnd exceeding 4 GB would be truncated to 32-bits
rather than limited to (4 GB - 1)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Interestingly the build used to succeed even with missing leading '0x'
prefix for a hex value before the commit 0613ccbd1357
("CorebootPayloadPkg/PciHostBridgeLib: Fix the wrong PCI resource limit")
With the above commit, luckily we get
...
raise BadExpression(ERR_ARRAY_ELE % self._Token)
BadExpression: This must be HEX value for NList or Array: [e6].
This patch fixes the above error by adding the missing '0x' prefix to
the hex value.
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Cycle
The fix handles the PCI Dual Address Cycle Attribute case. It allows
drivers using PCI DAC run on Juno.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
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SerialPortInitialize() set the BaudRate variable (type UINT64) as:
BaudRate = (UINTN)FixedPcdGet64 (PcdUartDefaultBaudRate);
This commit fixes a potential problem on ARM 32-bit builds, where the
UINTN type is defined as UINT32, by removing the cast:
BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Correct some obviously incorrect comments that have invalid details for
the returned values. (Copy /Paste problem?)
There are no functional changes in this commit.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This change updates PL011UartInitializePort to compare ReceiveFifoDepth
with the correct hardware FIFO size instead of the constant 32 used
previously.
This corrects a minor bug where a request for a fifo size > 15 and < 32
would not have been honoured on a system with a 16 byte FIFO.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The UEFI spec stipulates that unaligned accesses should be enabled
on CPUs that support them, which means all of them, given that we
no longer support pre-v7 ARM cores, and the AARCH64 bindings mandate
support for unaligned accesses unconditionally.
This means that one should not assume that CopyMem () is safe to call
on regions that may be mapped using device attributes, which is the
case for the NOR flash. Since we have no control over the mappings when
running under the OS, and given that write accesses require device
mappings, we should not call CopyMem () in the read path either, but
use our own implementation that is guaranteed to take alignment into
account.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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On ARM systems, mapping normal memory as device memory may have unintended
side effects, given that unaligned accesses or loads and stores with special
semantics (e.g., load/store exclusive) may fault or may not work as expected.
Similarly, DC ZVA instructions are only supported on normal memory, not
device memory.
So remove the EFI_MEMORY_UC attribute that we set by default on system RAM.
If any region requires this attribute, it is up to the driver to set this
attribute, and to ensure that no offending operations are performed on it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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According to the ACPI 6.0/6.1 spec, the physical base address of GICC,
GICD, GICR and GIC ITS is 64-bit. So change the type of the various GIC
base address PCDs to 64-bit, and fix up all users.
Contributed-under: TianoCore Contribution Agreement 1.0
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Dennis Chen <dennis.chen@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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this bug was introduced by:
d2fa09a ArmPlatformPkg/PrePi: switch to ASM_FUNC() asm macro
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
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Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.
While we're at it, replace some inefficient uses of LoadConstantToReg(),
and remove the workaround that was added to allow conditional branches
to functions with external linkage.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.
While we're at it, replace some inefficient uses of LoadConstantToReg()
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.
While we're at it, replace some inefficient uses of LoadConstantToReg()
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.
While we're at it, replace some inefficient uses of LoadConstantToReg()
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.
While we're at it, replace some inefficient uses of LoadConstantToReg()
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Annotate functions with ASM_FUNC() so that they are emitted into
separate sections.
While we're at it, replace some inefficient uses of LoadConstantToReg()
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The RVCT .asm files include AsmMacroIoLib.h only for the definition of
LoadConstantToReg (), which makes it tedious to make change to that file
without the risk of making the RVCT assembler unhappy. So simply replace
LoadConstantToReg() with mov32, which does the right thing in all cases.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The built-in Linux Loader is obsolete and not included in most builds.
The patch sets the PcdBdsLinuxSupport default value to FALSE and prevents
ArmBds from looking for built-in Linux Loader by default and ASSERTing
when it cannot be found. Platforms which still using built-in loader have
to set this PCD in their platform description file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daniil Egranov <daniil.egranov@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Now that the code to detect the Juno revision is in
the header go ahead and covert the ArmJunoDxe to use it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The code to detect what juno revision we are running on
is fairly small put it in a common header where it may be
used in a couple places.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The AXI<->PCIe translation comments are out of date with
respect to the code. In the first case the AXI master port
is incorrectly called a slave. In the second case the the
translation direction indicated for the slave port is the
wrong direction.
Correct both of these comments to reflect what the code is
doing.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The Juno PIO mapping is 8M, so it should be using a 32-bit
PIO address translation. Further, PIO addresses should start
at 0 and be translated to/from the ARM MMIO region.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Juno has several serial ports, one of which may be used for a remote
debug interface (e.g. gdb, WinDbg). The debug serial port needs to
be distinct from that used for UEFI trace to prevent corruption of
debugger protocol messaging.
The UEFI spec requires that serial devices be initialised to default
settings. (11.8 Serial I/O Protocol - "The default attributes for all
UART-style serial device interfaces are: 115,200 baud, ..."
and 17.3.3 EFI Debugport Variable - "These defaults must be used in the
absence of a DEBUGPORT variable...")
This change adds initialization of the serial device reported in the
ACPI DBG2 table. The initialisation is done early in the boot to allow
the possibility of remote debug of UEFI itself.
NOTE: This is functionally dependent on the DBG2 table being updated in
OpenPlatformPkg, but is required as a precursor to that change.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Switch all users of ArmLib that depend on the MMU routines to the new,
separate ArmMmuLib. This needs to occur in one go, since the MMU
routines are removed from ArmLib build at the same time, to prevent
conflicting symbols.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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This module is now identical in functionality to NorFlashDxe, and is no
longer used, so remove it altogether.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Now that the generic Variable Runtime DXE code no longer distinguishes
between gEfiVariableGuid and gEfiAuthenticatedVariableGuid in the varstore
FV header, we can relax the check in the NOR flash driver to accept either
GUID regardless of whether we are running a secure boot capable build or not.
This also means we can always use gEfiAuthenticatedVariableGuid when we
encounter an empty NOR flash that needs to be initialized before use. So
remove the mNorFlashVariableGuid global from the shared code and from both
versions of NorFlashDxe.inf. This essentially collapses the two drivers into
a single one, which means we can remove NorFlashAuthenticatedDxe entirely
in a subsequent patch.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This change corrects 3 problems in the PL011 driver.
1. The TRM states "The UARTLCR_H, UARTIBRD, and UARTFBRD registers must
not be changed:...when the UART is enabled"
2. The TRM (3.3.8) describes logic requiring the UART to be disabled and
flushed before adjusting UARTCR.
3. Several redundant calls get made to PL011UartInitializePort, where
the characteristics do not change, but updating the registers can
cause glitches in the output stream.
The parameters are compared to the current state and no action taken if
no change of state is required.
Where an update is required, the specified logic is followed, and the
register updates only made when the UART is disabled.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
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On some platforms the UART clock is not the same for all the serial
ports. The PL011 driver must be capable of handling serial ports with
different clock rates, so must not rely on a PCD for the clock rate.
This patch allows the UART clock rate to be passed as a parameter
to PL011UartInitializePort(), which is called from the serial port
library. This patch also contains the corresponding changes in the
serial port library.
The PCD in Drivers/PL011Uart is replaced by an extra parameter for
PL011UartInitializePort. The PCD is moved to Library/PL011SerialPortLib
to supply the value to pass.
A corresponding patch to ArmVirtPkg is included in the same bundle to
align that with these changes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
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The variable LineControl was initialised to zero, then updated in a
condition. This change converts that to a write in each branch of the
condition, removing the Write/Read/Modify/Write sequence.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
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The PCDs used in the PL011 UART Driver and Serial Port Library are
inherently "fixed at build". This change updates the source to use
Fixed PCDs for these values. This improves clarity and efficiency.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
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This cosmetic change only tidies things up in preparation for actual
updates. (This reflects responses to a previously submitted patch,
which has been split into several discrete changes.)
There are no functional changes in this commit.
Changes comprise:
Minor corrections to comment typos.
Minor formatting mods.
Expansion of function comments.
Remove OUT from UartBase parameter.
Addition of #define for "magic mumbers".
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
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Since the only reason for keeping a local copy mRT of the gRT pointer
is to be able to call GetVariable/SetVariable at runtime, use the
UefiRuntimeLib helpers instead, so that we can drop mRT altogether.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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PL031RealTimeClockLib is a base library that could potentially (although
unlikely) be incorporated into other modules than the DXE_RUNTIME_DRIVER
module that it was intended to complement.
This means the library has no business whatsoever setting the Runtime
Service table pointers directly (since we have no way of knowing which
instance will 'win', and the pointers may end up referring to a module
that is not a DXE_RUNTIME_DRIVER). So remove the assignment altogether.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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When combining UEFI firmware built from Tianocore with ARM Trusted
Firmware running in EL3, it is the responsibility of ATF that only
a single core enters the UEFI firmware in EL2, and the remaining cores
are released directly to the OS via PSCI SMC calls.
In this case, we don't need the MpCore flavor of PrePi or PrePeiCore,
but the UniCore flavor currently checks the CPU identification registers
directly, and refuses to proceed if the boot CPU is part of a MpCore
system.
So drop the ASSERT()'s that implement this check.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The PCI related PCDs are not platform specific, and architectural
protocols such as CpuIo2 are based on PCI provided MMIO to IO
translation, so these PCDs belong in ArmPkg not ArmPlatformPkg.
NOTE: this *WILL* break some out-of-tree platforms, the fix is changing
all consumers of gArmPlatformTokenSpaceGuid.PcdPci* to
gArmTokenSpaceGuid.PcdPci*
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The 64-bit version of the DS-5 debug script that retrieves the debug file
path from the PE/COFF image in memory assumes that the PE/COFF header is
packed, and that the debug directory entry in the optional header appears
at a fixed offset into the file. This is no longer true, now that we pad
between the file header and the PE header if the section alignment exceeds
the size of the header (which may be the case when the module contains a
vector table or small model code, which requires 2 KB or 4 KB section
alignment, respectively), to allow this padding to be emitted if the image
is subsequently converted to TE format.
So replace the fixed offset with a dereference of the appropriate header
field.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reported-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
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This patch adds a PCD for the PL011 UART Interrupt as this is needed by
the Serial Port Console Redirection Table.
Code at: https://github.com/EvanLloyd/tianocore/commit/68f26f23a236501d9e4294077da0d5070bbdab80
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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This retypes some stack base PCD as 64-bit, and fixes up a number of references
to 64-bit PCDs (including the retypes ones), to use the correct PcdGet64()
accessors. Note that, in the case of FixedPcdGet64, this does not actually
caused any problems, since that resolves to an immediate value. But the
generic PcdGetxx accessors should be typed according to the size of the PCD.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
[ard.biesheuvel: fixed up some instances in the 32-bit ARM code]
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Support multiple PL061 controllers. If platform gpio driver couldn't be
found, PL061 gpio driver will continue to load PcdPL061GpioBase as the
register base.
It could be compatible with the use case of current PL061 gpio driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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