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2016-09-09BaseTools/EfiRom: supply missing machine type lookup stringsLaszlo Ersek
"EfiRom --dump" does not recognize the 0x8664 machine type: > EFI ROM header contents > EFI Signature 0x0EF1 > Compression Type 0x0001 (compressed) > Machine type 0x8664 (unknown) > Subsystem 0x000B (EFI boot service driver) > EFI image offset 0x0050 (@0xF650) Add lookup strings for the remaining EFI_IMAGE_MACHINE_* numeric macros that can be found in "BaseTools/Source/C/Include/IndustryStandard/PeImage.h". The strings follow Table 12. "UEFI Image Types" from the UEFI v2.6 spec. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-09-08BaseTools VfrCompile Pccts: Update GCC Flags to the specific one with BUILD_ ↵Liming Gao
prefix This change is also applied to VfrCompile Pccts antlr and dlg tool. In V2, add the missing C rules. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-09-08BaseTools VfrCompile GNU makefile: Replace CXX with BUILD_CXXLiming Gao
The change is missing in VfrComile GNUmakefile. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-09-08BaseTools GNU makefile: remove unused .S ruleLiming Gao
Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-09-08BaseTools GNU makefile: Add BUILD_CXXFLAGS to align make built-in ruleLiming Gao
GNU make built-in rule to Compiling C++ programs with ‘$(CXX) $(CPPFLAGS) $(CXXFLAGS) -c’. To align to it, add empty BUILD_CXXFLAGS in cpp rule. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-09-04BaseTools: Change source files to DOS formatYonghong Zhu
Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-23BaseTools/GenFw: ignore dynamic RELA sectionsArd Biesheuvel
When building PIE (ET_DYN) executables, an additional RELA section is emitted (in addition to the per-section .rela.text and .rela.data sections) that is intended to be resolved at runtime by a ET_DYN compatible loader. At the moment, due to the fact that we don't support GOT based relocations, this dynamic RELA section only contains relocations that are redundant, i.e., each R_xxx_RELATIVE relocation it contains duplicates a R_xxx_xx64 relocation appearing in .rela.text or .rela.data, and so we can simply ignore this section (and we already ignore it in practice due to the fact that it points to the NULL section, which has the SHF_ALLOC bit cleared). For example, Section Headers: [Nr] Name Type Address Offset Size EntSize Flags Link Info Align [ 0] NULL 0000000000000000 00000000 0000000000000000 0000000000000000 0 0 0 [ 1] .text PROGBITS 0000000000000240 000000c0 000000000000427c 0000000000000008 AX 0 0 64 [ 2] .rela.text RELA 0000000000000000 00009310 0000000000001bf0 0000000000000018 I 7 1 8 [ 3] .data PROGBITS 00000000000044c0 00004340 00000000000046d0 0000000000000000 WA 0 0 64 [ 4] .rela.data RELA 0000000000000000 0000af00 0000000000000600 0000000000000018 I 7 3 8 [ 5] .rela RELA 0000000000008bc0 00008a10 0000000000000600 0000000000000018 0 0 8 [ 6] .shstrtab STRTAB 0000000000000000 0000b500 0000000000000037 0000000000000000 0 0 1 [ 7] .symtab SYMTAB 0000000000000000 00009010 0000000000000210 0000000000000018 8 17 8 [ 8] .strtab STRTAB 0000000000000000 00009220 00000000000000eb 0000000000000000 0 0 1 Relocation section '.rela.data' at offset 0xaf00 contains 64 entries: Offset Info Type Sym. Value Sym. Name + Addend 000000004800 000100000001 R_X86_64_64 0000000000000240 .text + 3f5b 000000004808 000100000001 R_X86_64_64 0000000000000240 .text + 3f63 000000004810 000100000001 R_X86_64_64 0000000000000240 .text + 3f79 000000004818 000100000001 R_X86_64_64 0000000000000240 .text + 3f90 000000004820 000100000001 R_X86_64_64 0000000000000240 .text + 3fa6 ... Relocation section '.rela' at offset 0x8a10 contains 64 entries: Offset Info Type Sym. Value Sym. Name + Addend 000000004800 000000000008 R_X86_64_RELATIVE 419b 000000004808 000000000008 R_X86_64_RELATIVE 41a3 000000004810 000000000008 R_X86_64_RELATIVE 41b9 000000004818 000000000008 R_X86_64_RELATIVE 41d0 000000004820 000000000008 R_X86_64_RELATIVE 41e6 000000004828 000000000008 R_X86_64_RELATIVE 41ff ... Note that GOT based relocations result in entries that *only* appear in the dynamic .rela section and not in .rela.text or .rela.data. This means two things if we intend to add support for GOT based relocations: - we must check that a dynamic RELA section exists; - we must filter out duplicates between .rela and .rela.xxx, to prevent emitting duplicate fixups into the PE/COFF .reloc section. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-23BaseTools GnuMakefile: Update GCC Flags to the specific one with BUILD_ prefixLiming Gao
To avoid the conflict with the default GCC flag name, BUILD_ prefix is added. Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-23BaseTools GNU Makefile: Add the missing rules for cpp source fileLiming Gao
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-08-22BaseTools PeCoffLib: Fix the issue to get RelocationsStripped from TE imageLiming Gao
If PE image has no relocation section, and has not set RELOCS_STRIPPED, after it is converted to TE image, GenFw will set its relocation section VirtualAddress to non-zero address, and keep Size value as Zero. MdePkg BasePeCoffLib applied this rule to get RelocationsStripped attribute. But, it is missing in BaseTools BasePeCoffLib. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-08-14BaseTools/GenFv: Account for rebase of FV section containing VTF fileLeo Duran
Account for rebase of FV section containing VTF file on IA32/IA64. This supports cases where the reset vector may not be set at 0xFFFFFFF0. For example, FV section defined as: [FV.FvSecPei] FvBaseAddress = $(FV_BOOT_BASE) FvForceRebase = TRUE Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-12BaseTool/VfrCompile: Remove reset button opcode in CheckQuestionOpCodeDandan Bi
"EFI_IFR_RESET_BUTTON_OP" is a statement, not a question, so remove it from function CheckQuestionOpCode. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-08-08BaseTools X64: fold PLT relocations into simple relative referencesArd Biesheuvel
For X64/GCC, we use position independent code with hidden visibility to inform the compiler that symbol references are never resolved at runtime, which removes the need for PLTs and GOTs. However, in some cases, GCC has been reported to still emit PLT based relocations, which we need to handle in the ELF to PE/COFF perform by GenFw. Unlike GOT based relocations, which are non-trivial to handle since the indirections in the code can not be fixed up easily (although relocation types exist for X64 that annotate relocation targets as suitable for relaxation), PLT relocations simply point to jump targets, and we can relax such relocations by resolving them using the symbol directly rather than via a PLT entry that does nothing more than tail call the function we already know it is going to call (since all symbol references are resolved in the same module). So handle R_X86_64_PLT32 as a R_X86_64_PC32 relocation. Suggested-by: Steven Shi <steven.shi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-08-08BaseTools/VfrCompile: Add two new option for VfrCompileDandan Bi
1.--autodefault option VfrCompile will generate default opcodes for questions if some default are missing. 2 --checkdefault option VfrCompile will check whether every question has no default or has all default. If not, will generate an error to let user know the question misses default. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-08-08BaseTool/VfrCompile: Add missing question opcodeDandan Bi
The function CheckQuestionOpCode is to check whether the opcode is question opcode, but it misses two question opcodes: 'EFI_IFR_REF_OP' and 'EFI_IFR_RESET_BUTTON'. Now add them. Cc: Liming Gao <liming.gao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-08-02BaseTools/GenFw AARCH64: convert ADRP to ADR instructions if binary size ↵Ard Biesheuvel
allows it The ADRP instruction in the AArch64 ISA requires the link time and load time offsets of a binary to be equal modulo 4 KB. The reason is that this instruction always produces a multiple of 4 KB, and relies on a subsequent ADD or LDR instruction to set the offset into the page. The resulting symbol reference only produces the correct value if the symbol in question resides at that exact offset into the page, and so loading the binary at arbitrary offsets is not possible. Due to the various levels of padding when packing FVs into FVs into FDs, this alignment is very costly for XIP code, and so we would like to relax this alignment requirement if possible. Given that symbols that are sufficiently close (within 1 MB) of the reference can also be reached using an ADR instruction which does not suffer from this alignment issue, let's replace ADRP instructions with ADR after linking if the offset can be encoded in this instruction's immediate field. Note that this only makes sense if the section alignment is < 4 KB. Otherwise, replacing the ADRP has no benefit, considering that the subsequent ADD or LDR instruction is retained, and that micro-architectures are more likely to be optimized for ADRP/ADD pairs (i.e., via micro op fusing) than for ADR/ADD pairs, which are non-typical. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-05-18BaseTools: Eliminate two shift-negative-value in FvLib.cZenith432
clang 3.8 flags -Wshift-negative-value warning, which turns fatal due to use of -Werror. Fixes: https://github.com/tianocore/edk2/issues/49 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Zenith432 <zenith432@users.sourceforge.net> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-05-16BaseTools: Add HII definitions from UEFI 2.6Samer El-Haj-Mahmoud
Add HII definitions from UEFI 2.6 for HII Image Variability and PNG Blocks Cc: Yonghong Zhu <yonghong.zhu@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Samer El-Haj-Mahmoud <elhaj@hpe.com> Reviewed-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-05-16BaseTools/GenFw: enhance to use Magic Field to identify the imageYonghong Zhu
Original use the File Header Machine Field to identify EFI_IMAGE_OPTIONAL_HEADER32 or EFI_IMAGE_OPTIONAL_HEADER64, it cannot correctly handle EBC arch PE32 image. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-04-15BaseTools/VolInfo: Update to handle PE image with .code section onlyYonghong Zhu
rebase the image which only has .code section, but no other section, the tool return error. this patch fix this bug to support it. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-04-15BaseTools/GenFw: Update to handle PE image with .code section onlyYonghong Zhu
current GenFw rebase the image which only has .code section, but no other section, the tool return error. this patch fix this bug to support it. Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-04-12BaseTools/VolInfo: generate HASH value for each PE imageYonghong Zhu
VolInfo Tool add new option --hash to use openssl to generate hash value for each PE image. If the image base address is not zero, we will rebase its base address to zero before generate hash value. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-10BaseTools: Update ARM/AArch64 GenFv vector processing for encapsulated FVsCohen, Eugene
Instead of only handling SEC Core or PEI Core instances in the outer FV, the GenFv tool will now recurse into FV image FFS files to look for instances in encapsulated FVs so the vector area can be updated appropriately. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-03-10BaseTools: Change source files to DOS format.Liming Gao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-03-03BaseTools/LZMA: fix the format issue for last patchYonghong Zhu
There are no functional changes in this patch. fixing the format base on last commit. The only change is 1) add back the blank line, which can help we better compare with the original LZMA source code. 2) remove the indent of #ifndef and #endif. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-02-29BaseTools: fix LzmaCompress VS2013 make failureYonghong Zhu
when make BaseTools by VS2013, LzmaEnc.c report warning C4127: conditional expression is constant, so this patch fix this issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-02-18BaseTools: LzmaCompress: fix gcc-6 warning "misleading-indentation"Laszlo Ersek
The way the first use of the "_maxMode" variable is commented out (i.e., together with the enclosing "if" statement) in GetOptimum() triggers the "misleading-indentation" warning that is new in gcc-6.0, for the block of code that originally depended on the "if" statement. Gcc believes (mistakenly) that the programmer believes (mistakenly) that the block depends on (repIndex == 0) higher up. Restore the if statement, with a controlling expression that comprises the constant 1 and "_maxMode" commented out. Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Cole Robinson <crobinso@redhat.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Yonghong Zhu <yonghong.zhu@intel.com> Reported-by: Cole Robinson <crobinso@redhat.com> Suggested-by: Jordan Justen <jordan.l.justen@intel.com> Build-tested-by: Cole Robinson <crobinso@redhat.com> Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1307439 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-02-18BaseTools/VolInfo: add some generic optionsYonghong Zhu
The Help information provided by VolInfo does not follow the EDK II Tools Design doc, so this patch update the help text and add the generic options: -d, -v, -q, -s. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-02-18BaseTools/GenFw: Fix a bug for GCC buildYonghong Zhu
current GCC build report error: 'for' loop initial declarations are only allowed in C99 or C11 mode, the patch fix this failure. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-02-17BaseTools/GenFw: Correct datatypes in diagnostic messages and check for ↵Michael LeMay
string termination This patch revises multiple diagnostic messages to use correct datatypes. It also checks that a symbol name that is about to be used in a diagnostic message is terminated by a null character within the contents of the string table section so that the print routine does not read past the end of the string table section contents when reading the symbol name. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael LeMay <michael.lemay@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-02-17BaseTools/GenFw: Enhance error message for bad symbol definitionsMichael LeMay
This patch expands the error message that is output when GenFw encounters a bad symbol definition or an unsupported symbol type. It displays the symbol name, the symbol address, and a message that describes both possibilities (bad symbol definition or unsupported symbol type). It also provides two examples of unsupported symbol types. Furthermore, this patch revises the conditional for detecting bad symbol definitions to eliminate a redundant test (a Sym->st_shndx value of SHN_ABS should certainly be greater than mEhdr->e_shnum) and to change another test from 'Sym->st_shndx > mEhdr->e_shnum' to 'Sym->st_shndx >= mEhdr->e_shnum' for consistency with the test in GetShdrByIndex. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael LeMay <michael.lemay@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-02-17BaseTools/GenFw: Exit with error when header lookup failsMichael LeMay
This patch revises GetPhdrByIndex and GetShdrByIndex to cause GenFw to exit with an error message when a section header lookup fails. The current behavior of those functions in such circumstances is to return NULL, which can cause GenFw to subsequently fault when it attempts to dereference the null pointer. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael LeMay <michael.lemay@intel.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
2016-02-16BaseTools-Source: Update displayed version informationedk2 dev
Standardize the --version and --help text command-line options Updated tools to correctly display the Build number when using command-line option --version and exit successfully after termination. Ecc was also updated to print informational messages after the options are parsed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Larry Hauch <larry.hauch@intel.com> Reviewed-by: Erik Bjorge <erik.c.bjorge@intel.com>
2016-02-15BaseTools/GenFw AARCH64: add support for relative data relocationsArd Biesheuvel
This adds support to the ELF to PE/COFF conversion performed by GenFw for the AArch64 ELF relocation types R_AARCH64_PREL64, R_AARCH64_PREL32 and R_AARCH64_PREL16. Since we already require the ELF and PE/COFF section layouts to be identical in order to support other relative relocation types, this is simply a matter of whitelisting these new relocation types in the same way. While we're at it, clean up the code a bit, and add a comment explaining why these relocations are ignored in WriteRelocations64 (). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-01-29BaseTools: Update BaseTools to pass VS2015 compilerYonghong Zhu
Fix some errors to pass VS2015 compiler. 1. warning C4456: declaration of xxx hides previous local declaration 2. warning C4005: 'UINT8_MAX': macro redefinition Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19768 6f19259b-4bc3-4df7-8a09-765794883524
2016-01-11BaseTools/VfrCompile: honor CC if it is setMichael Thomas
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Thomas <malinka@entropy-development.com> Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19636 6f19259b-4bc3-4df7-8a09-765794883524
2016-01-06BaseTools: Fix 'caculate' typosHao Wu
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19604 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-14BaseTools/GenFw RVCT: fix relocation processing of PT_DYNAMIC sectionsArd Biesheuvel
Unlike GNU ld, which can be instructed to emit symbol based static relocations into fully linked binaries using the --emit-relocs command line switch, the RVCT armlink tool can only emit dynamic relocations into the PT_DYNAMIC segment. This has two consequences . we can only identify absolute relocations, so there is no way to fix up relative relocations between sections, or check their validity in the PE/COFF layout . the r_offset fields of the PT_DYNAMIC DT_REL entries are relative either to the base of the image or to any of its segments but *not* to the base of the input section that contains the location they refer to, and converting them to PE/COFF image offsets is non-trivial unless the sections are laid out in the same way in the ELF and PE/COFF versions of the binary. There is really only one way to deal with this, and that is to require that the ELF and PE/COFF versions of the binary are identical in memory. So enforce that in the code. Also, fix the utterly broken relocation fixup code that dereferences ELF32_R_SYM(r_info) both as a 1-based program header index and a 0-based section header index. If this code ever produced working binaries, it was purely by chance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19236 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-07BaseTools: Enhance GenFv Tool to report error messageYonghong Zhu
When two vtf files in one FV image, no FV file can be generated, but it report the stack trace info. so we enhance the tool to report error message directly but not the stack trace info. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19141 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-07Revert the change in r19137.Yonghong Zhu
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19138 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-07BaseTools: Enhance GenFv Tool to report error messageYonghong Zhu
When two vtf files in one FV image, no FV file can be generated, but it report the stack trace info. so we enhance the tool to report error message directly but not the stack trace info. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19137 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-24BaseTools/GenFw ARM: allow R_ARM_REL32 relocationsArd Biesheuvel
R_ARM_REL32 are relative relocations, so we don't need to do anything special when performing the ELF to PE/COFF conversion, since our memory layout is identical between the two binary formats. So just allow them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18931 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17BaseTools: Fix two warning reported in the make phase.Yonghong Zhu
when we make BaseTools, it report warnings about VfrError.cpp and VolInfo, so this patch fix this warning. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18851 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-11BaseTools/GenFw: add new option to not zero PE/COFF optional header fieldsYonghong Zhu
Add new option --keepoptionalheader and that flag does not zero PE/COFF optional header fields including the version fields. It can support the case that the PE/COFF optional header would be kept. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18767 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-27BaseTools:remove the redundant directories for '-f' with absolute path.Yonghong Zhu
when the absolute path is given to '-f', it would create some redundant empty directories. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18675 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-15BaseTools VfrCompiler: In order to keep consistent, add an optional ";" for ↵Eric Dong
condition op-code. Current grammar for suppressif opcode not consistent in statement and option case, this patch fixed this issue. The same case also existed for other condition opcodes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18606 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-09BaseTools/PeCoffLoader: fix handling of ARM MOVW/MOVT instruction relocsArd Biesheuvel
The handling of ARM MOVW/MOVT relocations sets the FixupData twice (once incorrectly), but fails to advance the *FixupData pointer afterwards. This is not actually a problem, since the fixup data is never used but let's fix it anyway in case anyone reuses this code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18596 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-24BaseTools/GenFw: disable RVCT linker size optimizationArd Biesheuvel
Disable the RVCT size optimization that may put sections at an offset that is not aligned to their own alignment, by adding the --no_legacyalign switch to the RVCT linker command line. This is necessary since such sections cannot be correctly converted into PE/COFF sections without padding them at the front, which defeats the purpose of the optimization anyway. With the optimization gone, we can also remove the special case for ARM in GenFw that could result in corrupt PE/COFF images to be emitted. Instead, sections whose base address is not aligned correctly are outright rejected. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18540 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-24BaseTools/GenFw: remove ARM and RVCT references from ELF64 codeArd Biesheuvel
ARM and RVCT apply to 32-bit code only, so remove any references to them (including the workaround for the linker) from the 64-bit version of ElfConvert.c Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18539 6f19259b-4bc3-4df7-8a09-765794883524
2015-09-11BaseTools/GenFw: align RVA of debugArd Biesheuvel
SVN commit r18077 ("BaseTools/GenFw: move .debug contents to .data to save space") removed the separate .debug section after moving its contents into .text or .data. However, this change does not take into account that some of these contents need to appear at a 32-bit aligned offset. So align the debug data RVA to 32 bits. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18443 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-08 05:48:42 +0000