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2018-04-25Remove Core PackageGuo Mang
Remove Core Package since we will use EDK2 code from edk2 repository: https://github.com/tianocore/edk2 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang <mang.guo@intel.com>
2018-02-09UefiCpuPkg MpInitLib: Save/restore original WakeupBuffer for DxeMpLibGuo Mang
Current code always allocates/frees < 1MB WakeupBuffer for DxeMpLib until ExitBootService, but the allocation may be failed at late phase of the boot. This patch is to always save/restore original WakeupBuffer for DxeMpLib. Sync from edk2 master: a6b3d753f98118ee547ae935b347f4f00fa67e7c Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-07-12UefiCpuPkg/MpInitLib: Force to enable X2APIC if CPU number > 255Jeff Fan
Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit 71d8226ac6f256d360626c8072337f9373f95671)
2017-07-12UefiCpuPkg/MpInitLib: Check APIC mode change around AP functionJeff Fan
If APIC ID values are changed during AP functions execution, we need to update new APIC ID values in local data structure accordingly. But if APIC mode change happened during AP function execution, we do not support APIC ID value changed. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit c6b0feb39637867744bb7bffaa8534ecb1de707d)
2017-07-12UefiCpuPkg/CpuCommonFeaturesLib: Support X2APIC enableJeff Fan
Current X2APIC is enabled in MpInitLib (used by CpuMpPei and CpuDxe) to follow SDM suggestion. That means we only enable X2APIC if we found there are any initial CPU ID value >= 255. This patch is to provide one chance for platform to enable X2APIC even there is no any initial CPU ID value >= 255. Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit 6661abb6953fcb6dafe4eee9ec741685ceb3a552)
2017-07-12UefiCpuPkg/MpInitLib: Fix X64 XCODE5/NASM compatibility issuesMichael Kinney
https://bugzilla.tianocore.org/show_bug.cgi?id=565 Fix NASM compatibility issues with XCODE5 tool chain. The XCODE5 tool chain for X64 builds using PIE (Position Independent Executable). For most assembly sources using PIE mode does not cause any issues. However, if assembly code is copied to a different address (such as AP startup code in the MpInitLib), then the X64 assembly source must be implemented to be compatible with PIE mode that uses RIP relative addressing. The specific changes in this patch are: * Use LEA instruction instead of MOV instruction to lookup the addresses of functions. * The assembly function RendezvousFunnelProc() is copied below 1MB so it can be executed as part of the MpInitLib AP startup sequence. RendezvousFunnelProc() calls the external function InitializeFloatingPointUnits(). The absolute address of InitializeFloatingPointUnits() is added to the MP_CPU_EXCHANGE_INFO structure that is passed to RendezvousFunnelProc(). Cc: Andrew Fish <afish@apple.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Andrew Fish <afish@apple.com> (cherry picked from commit 3b2928b46987693caaaeefbb7b799d1e1de803c0)
2017-07-12UefiCpuPkg: Use FINIT instead of hex valuesMichael Kinney
https://bugzilla.tianocore.org/show_bug.cgi?id=560 Update X64 NASM file to match IA32 NASM file and use FINIT instruction instead of hand assembled hex values for the FINIT instruction. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit b9dbc03e5a4c90b9e3efe0e0e8c014c428528261)
2017-07-12UefiCpuPkg/BaseUefiCpuLib: Use NASM read-only data section nameMichael Kinney
https://bugzilla.tianocore.org/show_bug.cgi?id=556 NASM requires read-only data sections to use the section name .rodata. This fix changes .rdata to .rodata. The build failure from use of .rdata is seen when using the XCODE5 tool chain. Section "7.8.1 macho extensions to the SECTION Directive" of the NASM documentation at http://www.nasm.us/doc/ describes the section name requirements. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Andrew Fish <afish@apple.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 5b78f30d81d7e536df37bafb48c4cb5b6d44edb8)
2017-07-12UefiCpuPkg/PiSmmCpuDxeSmm: Add missing JMP instructionMichael Kinney
https://bugzilla.tianocore.org/show_bug.cgi?id=555 Add JMP instruction in SmiEntry.S file that is missing. This updates SmiEntry.S to match the logic in SmiEntry.asm and SmiEntry.nasm. The default BUILDRULEORDER has .nasm higher priority than .asm or .S, so this issue was not seen with MSFT or GCC tool chain families. The XCODE5 tool chain overrides the BUILDRULEORDER with .S higher than .nasm, so this issue was only seen when using XCODE5 tool chain when IA32 SMM is enabled. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Andrew Fish <afish@apple.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> (cherry picked from commit 0d0a19cb14ba6867813f56a52cfc89545ad07f3a)
2017-07-12UefiCpuPkg/PiSmmCpuDxeSmm: Fix logic check errorJeff Fan
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> (cherry picked from commit 29dc8aa861fac78c6d62391dff312db934b755e3)
2017-07-12UefiCpuPkg/PiSmmCpuDxeSmm: Check ProcessorId == INVALID_APIC_IDJeff Fan
If PcdCpuHotPlugSupport is TRUE, gSmst->NumberOfCpus will be the PcdCpuMaxLogicalProcessorNumber. If gSmst->SmmStartupThisAp() is invoked for those un-existed processors, ASSERT() happened in ConfigSmmCodeAccessCheck(). This fix is to check if ProcessorId is valid before invoke gSmst->SmmStartupThisAp() in ConfigSmmCodeAccessCheck() and to check if ProcessorId is valid in InternalSmmStartupThisAp() to avoid unexpected DEBUG error message displayed. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit b7025df8f9102a1698879aa451bf5af592c37bc1)
2017-07-12UefiCpuPkg/SmmCpuFeaturesLib: Correct print levelJeff Fan
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit 5d0933f9bab2781bf5df078d12c22d50df165617)
2017-07-12UefiCpuPkg/SmmCpuFeaturesLib: Fix Ia32/SmiEntry.asm build issueJeff Fan
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit 6afc643ce0eded9ccbd015a5cd6d2ba0e264b01d)
2017-07-12UefiCpuPkg/MtrrLib: Don't report OutOfResource when MTRR is enoughRuiyu Ni
The MTRR calculation algorithm contains a bug that when left subtraction cannot produce better MTRR solution, it forgets to restore the BaseAddress/Length so that MtrrLibGetMtrrNumber() returns bigger value of actual required MTRR numbers. As a result, the MtrrLib reports OutOfResource but actually the MTRR is enough. MEMORY_RANGE mC[] = { 0, 0x100000, CacheUncacheable, 0x100000, 0x89F00000, CacheWriteBack, 0x8A000000, 0x75000000, CacheUncacheable, 0xFF000000, 0x01000000, CacheWriteProtected, 0x100000000, 0x7F00000000, CacheUncacheable, 0xFC240000, 0x2000, CacheWriteCombining // <-- trigger the error }; Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 3654c4623c9b37ddc64426995fa399d8626b7ced)
2017-07-12UefiCpuPkg: Update package version to 0.80Jeff Fan
Cc: Feng Tian <feng.tian@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit 007b51e180d2202637dfc6d2afbe8a34704c423f)
2017-07-12UefiCpuPkg: Update package version to 0.80Jeff Fan
Cc: Feng Tian <feng.tian@intel.com> Cc: Eric Dong <eric.dong@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> (cherry picked from commit 93041972617af5f538fac8291e7a57b7766c6e10)
2017-07-12PeCoffGetEntryPointLib: Fix spelling issueJeff Fan
*Serach* should be *Search* Cc: Liming Gao <liming.gao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> (cherry picked from commit 9e981317be20ab85bb68a670e79735f9685a3348)
2017-07-12UefiCpuPkg/MpLib.c: Set AP state after X2APIC mode enabledJeff Fan
After X2APIC mode is enabled, APs need to be set tp IDLE state, otherwise APs cannot be waken up by MP PPI services. https://bugzilla.tianocore.org/show_bug.cgi?id=505 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 59a119f0fcaed5a7cab4829bb19dd7ffa94e16a0)
2017-07-12UefiCpuPkg: Move ProgramVirtualWireMode() to MpInitLibJeff Fan
In PEI phase, BSP did not program vitural wired mode while APs did. Move program virtual wired mode from CpuDxe to MpInitLib, thus it could benefit on both CpuDxe and CpuMpPei. https://bugzilla.tianocore.org/show_bug.cgi?id=496 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 9d64a9fd9ee05f0b0228fc1f8b66398dac85e2c9)
2017-07-12UefiCpuPkg/MpInitLib: needn't to allocate AP reset vectorJeff Fan
Because we will always borrow the AP reset vector space for AP waking up. We needn't allocate such range to prevent other module to use it. It could simply the code. https://bugzilla.tianocore.org/show_bug.cgi?id=500 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit c934a0a5816e38ca5dbdb25936c4f841958a008e)
2017-07-12UefiCpuPkg/MpInitLib: save/restore original contentsJeff Fan
If APs is in HLT-LOOP mode, we need AP reset vector for waking up APs. This updating is to save/restore original contents of AP reset vector around waking up APs always. https://bugzilla.tianocore.org/show_bug.cgi?id=500 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> (cherry picked from commit 9293d6e42e677e4a38e055258c0993ad8a9df14e)
2017-07-12UefiCpuPkg/PiSmmCpuDxeSmm: Lock should be acquiredJeff Fan
SMM BSP's *busy* state should be acquired. We could use AcquireSpinLock() instead of AcquireSpinLockOrFail(). Cc: Hao Wu <hao.a.wu@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> (cherry picked from commit 170a3c1e0fff7de43501ef851b4ad5cbe355e220)
2017-07-12UefiCpuPkg/MtrrLib: Avoid running unnecessary codeRuiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com> (cherry picked from commit c9b449213337172d629197a75390a151eba65eb6)
2017-05-26GCC build support.zwei4
Change code which is not compatible with GCC. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-04-27UefiCpuPkg: Move to new locationGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
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