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2016-01-21IntelFspWrapperPkg: Add NOOPT target in IntelFspWrapperPkg.dscHao Wu
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19703 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15Fix >4G issue on IDT not restored correctly.Yao, Jiewen
Idtr might be changed inside of FSP. 32bit FSP only knows the <4G address. If IDTR.Base is >4G, FSP can not handle. So we need save/restore IDTR here. Interrupt is already disabled here, so it is safety to update IDTR. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> Reviewed-by: "Yarlagadda, Satya P" <satya.p.yarlagadda@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19246 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-27Publish FspHob to PEI Hob by default.Yao, Jiewen
because most platforms use such logic. PcdDataBaseHobGuid GuidHob is excluded because PCD database in FSP is different with the one in PEI. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18687 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-27Fix issue that calling GetS3MemoryInfo() with wrong order.Yao, Jiewen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18679 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-27Do not deadloop if Microcode not found in FspTempRamInit.Yao, Jiewen
We do not consider microcode not found as critical error, because Microcode might be applied later. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18678 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-28FspNotifyDxe need handle >4G memory.Yao, Jiewen
The FSP API is always 32bit, but FspNotifyDxe might load to >4G memory. In order to make thunk work, we need reload FspNotifyDxe to <4G memory. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18094 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-07FspInitPei function calling parameters not matching with the function ↵Yao, Jiewen
definition. IntelFspWrapperPkg, In the file FspInitPeiV1.c and FspInitPeiV2.c, there are function calling: GetStackInfo (BootMode, FALSE, &StackBase, &StackSize); But the function GetStackInfo() defined as EFI_STATUS EFIAPI GetStackInfo ( IN UINT32 BootMode, IN BOOLEAN FspInitDone, OUT UINT64 *StackSize, OUT EFI_PHYSICAL_ADDRESS *StackBase ) It should be GetStackInfo (BootMode, FALSE, &StackSize, &StackBase); Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.yao@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17850 6f19259b-4bc3-4df7-8a09-765794883524
2015-05-08IntelFspWrapperPkg: Update PeiFspHobProcessLibSample to consume PI CapsulePpiLiming Gao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17376 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-29Add dual FSP binaries support.Ma, Maurice
There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version) TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17249 6f19259b-4bc3-4df7-8a09-765794883524
2015-04-23IntelFspWrapperPkg update for FSP1.1Yao, Jiewen
-- Add BootLoaderTolumSize support -- Fix LibraryClasses declaration in DEC file. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <Jiewen.Yao@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17197 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-12Fix comments format error.Fsp1.1 update.Yao, Jiewen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16843 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-12Fsp1.1 update.Yao, Jiewen
Update ApiEntry.asm to use MACRO instead of direct XMM access. Add sanity parameter check for FSP API. Add sanity return code check for internal API. Call LoadUcode before CarInit to meet silicon requirement. Remove unnecessary VpdBase for PatchTable. Add ASSERT for NULL check FSP1.1 entrypoint. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16834 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-11Update IntelFspWrapperPkg according to FSP1.1.Yao, Jiewen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16826 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-03*/Contributions.txt: Update example email addressJordan Justen
Use the example.com domain as recommended in RFC 2606. NOTE: This does not modify the wording of the "TianoCore Contribution Agreement 1.0" section Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Bruce Cran <bruce.cran@gmail.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16724 6f19259b-4bc3-4df7-8a09-765794883524
2015-02-03IntelFsp*Pkg: Add Contributions.txtJordan Justen
This was copied from MdePkg. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16721 6f19259b-4bc3-4df7-8a09-765794883524
2015-01-19IntelFspWrapperPkg: Refine the format of meta data files.Shumin Qiu
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Shumin Qiu <shumin.qiu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16623 6f19259b-4bc3-4df7-8a09-765794883524
2014-12-04Fix typo.Yao, Jiewen
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Rangarajan, Ravi P" <ravi.p.rangarajan@intel.com> Reviewed-by: "Ma, Maurice" <maurice.ma@intel.com> Reviewed-by: "Mudusuru, Giri P" <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16475 6f19259b-4bc3-4df7-8a09-765794883524
2014-09-03IntelFspPkg/IntelFspWrapperPkg: Fix some typos.Star Zeng
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16040 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-08Rollback file GUID change, because it is VTF file and GUID is predefined.jyao1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed off by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Chris Li <chris.li@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15775 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-06Eliminate duplicated file GUID.jyao1
Eliminate duplicate GUID definition. Do explicit data cast. Use StrnCpy instead of StrCpy. Update GCC assembly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed off by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Eric Dong <eric.dong@intel.com> Reviewed by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15762 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-04Clean up code.jyao1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed off by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15744 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-04Clean up code.jyao1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed off by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Eric Dong <eric.dong@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15743 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-24Add IntelFspWrapper to support boot EDKII on FSP bin.jyao1
Contributed-under: TianoCore Contribution Agreement 1.0 Signed off by: Jiewen Yao <jiewen.yao@intel.com> Reviewed by: Ravi Rangarajan <ravi.p.rangarajan@intel.com> Reviewed by: Maurice Ma <maurice.ma@intel.com> Reviewed by: Giri Mudusuru <giri.p.mudusuru@intel.com> Reviewed by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15676 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 08:22:28 +0000