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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
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In the original code, there exists some mismatches between the real
waiting time and the corresponding timeout comments. For example, the
XHC_GENERIC_TIMEOUT comment says it's 10ms timeout value, but the real
code in fact waits 10s.
So the code is refined to be consistent in code logic and comments.
Note XHC_POLL_DELAY macro also be removed and the polling interval in
XhcWaitOpRegBit() is changed from 1ms to 1us to keep same code style
with other code. It has no real functionality impact.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18235 6f19259b-4bc3-4df7-8a09-765794883524
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Updating the async polling interval from 50ms to 1ms for better performance.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Tian Feng <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17585 6f19259b-4bc3-4df7-8a09-765794883524
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15617 6f19259b-4bc3-4df7-8a09-765794883524
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enabled in XhciDxe driver.
Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14760 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Elvin Li <elvin.li@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14546 6f19259b-4bc3-4df7-8a09-765794883524
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polling cmd execution status
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Elvin Li <elvin.li@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14442 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: Li Elvin <elvin.li@intel.com>
Reviewed-by: Yao Jiewen <jiewen.yao@intel.com>
Reviewed-by: Ni Ruiyu <ruiyu.ni@intel.com>
Reviewed-by: Gao Liming <liming.gao@intel.com>
Reviewed-by: Tian Feng <feng.tian@intel.com>
Reviewed-by: Fan Jeff <jeff.fan@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13890 6f19259b-4bc3-4df7-8a09-765794883524
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that those completed async transfer events don't get handled in time and are flushed by newer coming events.
Signed-off-by: erictian
Reviewed-by: li-elvin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13145 6f19259b-4bc3-4df7-8a09-765794883524
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1) XHCI host controller hw always provides more than 5 interrupters.
Now using interrupter 0 to accommodate all received events.
2) XHCI host controller hw always provides 32bytes context size.
Now it dynamically detect context size and construct it.
also solved several issues:
1) Divides 64byte width register access to two 32bit registers access because some XHCI chipsets cannot support a single 64bit access.
2) Remove halt host controller statement in UsbBusDriverBindingStop(). It has been done by host controller’s DriverBindingStop(). And XhciDriverBindingStop() need XHCI host controller is in running state because it need execute DISABLE_SLOT cmd to release h/w resource.
signed-off-by: erictian
Reviewed-by: li-elvin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12785 6f19259b-4bc3-4df7-8a09-765794883524
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there are multiple XHCI host controllers.
2) coding style clean up.
Signed-off-by: erictian
Reviewed-by: ydong10
Reviewed-by: jshi19
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12351 6f19259b-4bc3-4df7-8a09-765794883524
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Signed-off-by: erictian
Reviewed-by: jshi19
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12185 6f19259b-4bc3-4df7-8a09-765794883524
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