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2017-02-21MdeModulePkg/PciBusDxe: Refine code to make it more readableRuiyu Ni
The patch doesn't impact functionality. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
2017-02-21MdeModulePkg/SdMmc: Avoid assigning 0 to the BlockSize of TrbHao Wu
Refine code to avoid potential divide by zero when calculating block number. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-02-17MdeModulePkg/PciBusDxe: Fix IA32 build failureRuiyu Ni
Compiler calculates the PciBar[BarIndex] using sizeof (PciBar[0]) * BarIndex, when BarIndex is type of UINT64, the above calculation generates assembly code using _allmul. Change BarIndex to UINTN to avoid the build failure. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
2017-02-10MdeModulePkg/IncompatiblePci: Use MAX_UINTN to match any IDsRuiyu Ni
When the VendorId/DeviceId/RevisionId/SubsystemVendorId /SubsystemDeviceId is MAX_UINTN, IncompatiblePciDeviceSupport driver doesn't use it to match any IDs. The patch fixes this bug. Since PciBus driver always calls IncompatiblePciDeviceSupport using IDs read from HW, MAX_UINTN is never passed to this driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-02-10MdeModulePkg/IncompatiblePciDevice: Do not use deprecated macrosRuiyu Ni
The patch replaces the following macros: DEVICE_ID_NOCARE (0xFF) --> MAX_UINT64 PCI_ACPI_UNUSED (0) --> 0 PCI_BAR_ALL (0xFF) --> MAX_UINT64 PCI_BAR_NOCHANGE (0) --> 0 PCI_BAR_EVEN_ALIGN --> EVEN_ALIGN (local definition) Since the PciBus driver was updated to accept Spec defined values in previous commit, the above replacements don't impact functionality. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-02-10MdeModulePkg/PciBus: Accept Spec values as BarIndex and AlignmentRuiyu Ni
PI spec IncompatiblePciSupport part defines (UINT64)-1 as all BARs and 0 to use existing alignment. PciBus driver didn't accept these values. It treated 0xFF as all BARs and 0xFFFFFFFFFFFFFFFFULL to use existing alignment. The patch changes the code to still accept old values while also accept values defined in PI spec. So that the driver can provide backward compatibility and follow spec. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-02-10MdeModulePkg/PciSioSerialDxe: Use MAX_UINT8 instead of PCI_BAR_ALLRuiyu Ni
When BarIndex equals to 0xFF, default value 0 is used as the BAR index. Though PCI_BAR_ALL and MAX_UINT8 shares the same value, using PCI_BAR_ALL is like to match any BAR not BAR 0, it's more proper to use MAX_UINT8 here. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-01-20MdeModulePkg: Remove superfluous return statementsThomas Huth
If the code eventually returns "Status" anyway, it does not make sense to explicitly return "Status" in case of an error, too. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-01-20MdeModulePkg/UfsBlockIoPei: fix initialize OCS value to 0x0FHaojian Zhuang
The OCS value should be initiliazed as 0x0F according to UFS spec. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-01-20MdeModulePkg/UfsPassThruDxe: fix initialize OCS value to 0x0FHaojian Zhuang
The OCS value should be initiliazed as 0x0F according to UFS spec. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-01-20MdeModulePkg/UfsBlockIoPei: fix the bit in UFS_HC_UTRLDBR_OFFSET regHaojian Zhuang
When UPIU packet is sent, (BIT0 << Slot) should be set according to context. But BIT0 is used without Slot when UfsWaitMemSet () is invoked. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-01-20MdeModulePkg/UfsPassThruDxe: fix the bit in UFS_HC_UTRLDBR_OFFSET regHaojian Zhuang
When UPIU packet is sent, (BIT0 << Slot) should be set according to context. But BIT0 is used without Slot when UfsWaitMemSet () is invoked. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-01-20MdeModuelPkg/UfsPassThruDxe: fix to identify 32 bits address modeHaojian Zhuang
When UFS_HC_CAP_64ADDR bit is set, it means 64-bit address, not 32-bit address. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-01-12MdeModulePkg/NonDiscoverable: Compare SIZE_4GB with address typeHao Wu
Refine the codes to compare the definition 'SIZE_4GB' with type EFI_PHYSICAL_ADDRESS. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2017-01-05MdeModulePkg/StaControllerDxe: Fix coding style issueDandan Bi
Remove the empty line. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-26MdeModulePkg Ps2KbDxe: Execute key notify func at TPL_CALLBACKStar Zeng
Current implementation executes key notify function in TimerHandler at TPL_NOTIFY. The code change is to make key notify function executed at TPL_CALLBACK to reduce the time occupied at TPL_NOTIFY. The code will signal KeyNotify process event if the key pressed matches any key registered and insert the KeyData to the EFI Key queue for notify, then the KeyNotify process handler will invoke key notify functions at TPL_CALLBACK. Cc: Ruiyu Ni <Ruiyu.ni@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
2016-12-26MdeModulePkg UsbKbDxe: Execute key notify func at TPL_CALLBACKStar Zeng
Current implementation executes key notify function in TimerHandler at TPL_NOTIFY. The code change is to make key notify function executed at TPL_CALLBACK to reduce the time occupied at TPL_NOTIFY. The code will signal KeyNotify process event if the key pressed matches any key registered and insert the KeyData to the EFI Key queue for notify, then the KeyNotify process handler will invoke key notify functions at TPL_CALLBACK. Cc: Ruiyu Ni <Ruiyu.ni@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
2016-12-20MdeModulePkg/SataControllerDxe: Fix coding style issueDandan Bi
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-20MdeModulePkg/EmmcDxe: Avoid Non-Boolean type used as BooleanDandan Bi
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-19MdeModulePkg/NonDiscoverablePciDevice: Make variable definition follow ruleDandan Bi
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-19MdeModulePkg/NonDiscoverablePciDeviceDxe: Add comments for functionsDandan Bi
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-19MdeModulePkg/NonDiscoverablePciDeviceDxe: Fix VS2010/2012 build failureDandan Bi
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-15MdeModulePkg/NonDiscoverablePciDeviceDxe: add support for non-coherent DMAArd Biesheuvel
Add support for non-coherent DMA, either by performing explicit cache maintenance when DMA mappings are aligned to the CPU's DMA buffer alignment, or by bounce buffering via uncached mappings otherwise. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-13MdeModulePkg/NonDiscoverablePciDev: Fix type mismatch in switch/caseHao Wu
Fix switch/case statement type mismatch in functions PciIoMemRead & PciIoMemWrite. Parameter 'Width' is of enum type EFI_PCI_IO_PROTOCOL_WIDTH, but the enum type provided in 'switch (Width)' block is of type EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-09MdeModulePkg/NonDiscoverablePciDevice: add missing cast and EFIAPI modifiersArd Biesheuvel
Add missing EFIAPI modifiers to the functions that are exposed via the PCI I/O protocol. At the same time, add a missing UINT8 cast which breaks the build on Visual Studio. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Dandan Bi <dandan.bi@intel.com>
2016-12-07MdeModulePkg: implement generic PCI I/O driver for non-discoverable devicesArd Biesheuvel
This implements support for non-discoverable PCI compatible devices, i.e, devices that are not on a PCI bus but that can be controlled by generic PCI drivers in EDK2. This is implemented as a UEFI driver, which means we take full advantage of the UEFI driver model, and only instantiate those devices that are necessary for booting. Care is taken to deal with DMA addressing limitations: DMA mappings and allocations are moved below 4 GB if the PCI driver has not informed us that the device being driven is 64-bit DMA capable. DMA is implemented as coherent, support for non-coherent DMA is implemented by a subsequent patch. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Tested-by: Marcin Wojtas <mw@semihalf.com>
2016-12-06MdeModulePkg/PciSioSerial: Fix bad EOLRuiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-02MdeModulePkg/Ehci: don't clear port status bits during initFeng Tian
Port status bits are clear in original code, so no enumeration takes place. Changing this to prevent the status bits from being cleared allows enumeration to proceed normally. Cc: Star Zeng <star.zeng@intel.com> Cc: Mike Turner <Michael.Turner@microsoft.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mike Turner <Michael.Turner@microsoft.com> Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-12-02MdeModulePkg/SdMmc: Fix build failure caused by last check-inFeng Tian
The commit e27cca has a typo on DEBUG level macro. And this debug message should be DEBUG_INFO rather than DEBUG_ERROR. Cc: Jan Dabros <jsd@semihalf.com> Cc: Marcin Wojtas <mw@semihalf.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> reviewed-by: Marcin Wojtas <mw@semihalf.com>
2016-11-30MdeModulePkg/SdMmcPciHcDxe: Replace deprecated debug level macrosFeng Tian
EFI_D_INFO, EFI_D_VERBOSE, EFI_D_WARN and EFI_D_ERROR are replaced with currently recommended values. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jan Dabros <jsd@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-11-24MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in AhciMarcin Wojtas
According to AHCI Spec 1.3 GHC.AE bit description: "The implementation of this bit is dependent upon the value of the CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall have a reset value of '1'." Being in AhciMode, for proper operation it is required, that GHC.AE bit is always set, before any other AHCI registers are written to. Current AhciMode implementation, both in AhciReset() and AhciModeInitialization() functions, set GHC.AE bit only depending on 'CAP.SAM == 0' condition, assuming (according to the AHCI spec), that otherwise it has to be set anyway. It may however happen, that even if 'CAP.SAM == 1', GHC.AE requires updating by software. This patch enables in AhciMode setting GHC.AE in case its initial value is '0'. It fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC families. The change is transparent to all other platforms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Jan Dabros <jsd@semihalf.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-11-24MdeModulePkg/Xhci: Add 10ms delay before sending SendAddr cmd to devFeng Tian
We send ADDRESS DEVICE CMD in XhcInitializeDeviceSlot(), which will cause XHC issue a USB SET_ADDRESS request to the USB Device. According to USB spec, there should have a 10ms delay before this operation after resetting a given port. But in original code, there is a possible path which may have no such 10ms delay: UsbHubResetPort()->UsbHubSetPortFeature()->Stall(20)->UsbHubGetPortSt atus()->XhcPollPortStatusChange()->(if RESET_C bit is set)-> XhcInitializeDeviceSlot()->(if RESET_C bit is set)->Stall(10) So this patch is used to fix above issue. Cc: Star Zeng <star.zeng@intel.com> Cc: Baraneedharan Anbazhagan <anbazhagan@hp.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Tested-by: Baraneedharan Anbazhagan <anbazhagan@hp.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-11-14MdeModulePkg/UsbMass: Revert changes of removing retry logicFeng Tian
This patch is used to revert changes done in commit 17f3e942 bc527fbd75068d2d5752b6af54917487 - "MdeModulePkg/UsbMass: Not retry if usb bot transfer execution fail" It's because Usb Floppy will report DEVICE_ERROR for the first several cmds when it need spin up. so retry logic makes sense. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-11-10MdeModulePkg/PciSioSerial: Fix a bug that wrongly produces 2 UARTsRuiyu Ni
When PciSioSerial is firstly started with a non-NULL remaining device path, the UART instance is created using the parameters specified in the remaining device path. Later when the driver is started again on the same UART controller with NULL remaining device path, the correct logic is to directly return SUCCESS instead of current buggy implementation which wrongly produces another UART using the default parameters. The bug causes two UARTs are created when the UART is configured in 57600 baud rate. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Cc: Eric Dong <eric.dong@intel.com>
2016-11-09MdeModulePkg/Ufs: ensure the DBC field of UTP PRDT is dword-alignedFeng Tian
According to UFS Host Controller Spec(JESD223), the bits 1:0 of this DataByteCount field shall be 11b to indicate Dword granularity. But the size of UFS Request Sense Data Response defined in UFS Spec (JESD220C) is 18 which is not Dword aligned, we would have to round down to the multiple of 4 to fill the DBC field to avoid bring issue on some UFS HCs. Cc: Hao Wu <hao.a.wu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com>
2016-11-01MdeModulePkg/Xhci: Change short packet debug message to verbose levelFeng Tian
Short Packet case is a normal case, we shouldn't print it as an error Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-11-01MdeModulePkg/AtaAtapiPassThru: update AtaStatusBlock after cmd execFeng Tian
AhciDumpPortStatus doesn't fully populate all the fields of AtaStatusBlock after completing command execution, which may bring issue if someone depends on the return status. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-10-27MdeModulePkg/UsbBusDxe: rebase to ARRAY_SIZE()Laszlo Ersek
Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-10-27MdeModulePkg/PciHostBridgeDxe: rebase to ARRAY_SIZE()Laszlo Ersek
Cc: Feng Tian <feng.tian@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-10-27MdeModulePkg/PciBusDxe: rebase to ARRAY_SIZE()Laszlo Ersek
Cc: Feng Tian <feng.tian@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Feng Tian <feng.tian@Intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-10-27MdeModulePkg/Bus: Fix typos in commentsGary Lin
- TURE -> TRUE - stoping -> stopping - doule -> double - Peroidic -> Periodic - stardard -> standard - a a -> a - reseting -> resetting - excute -> execute - connectted -> connected - Sumbit -> Submit Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gary Lin <glin@suse.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-09-28MdeModulePkg/PciSioSerialDxe: Remove unused global variablesRuiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-26MdeModulePkg/PciBusDxe: make OPROM BAR degradation configurableArd Biesheuvel
The 'universal' PCI bus driver in MdeModulePkg contains a quirk to degrade 64-bit PCI MMIO BARs to 32-bit in the presence of an option ROM on the same PCI controller. This quirk is highly specific to not just the X64 architecture in general, but to the PC platform in particular, given that only X64 platforms that require legacy PC BIOS compatibility require it. However, making the quirk dependent on the presence of the legacy BIOS protocol met with resistance, due to the fact that it introduces a dependency on the IntelFrameworkModulePkg package. So instead, make the quirk configurable, by introducing a feature flag PCD 'PcdPciDegradeResourceForOptionRom' which defaults to TRUE only for X64. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-09-21MdeModulePkg/XhciPei:1ms delay before access MMIO reg during resetFeng Tian
Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during HC reset. As this delay is not defined by XHCI spec, we use this workaround to fix the issue. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-09-21MdeModulePkg/XhciDxe:1ms delay before access MMIO reg during resetFeng Tian
Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during HC reset. As this delay is not defined by XHCI spec, we use this workaround to fix the issue. Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-09-06MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that support itArd Biesheuvel
Currently, the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute is completely ignored by the PCI host bridge driver, which means that, on an implementation that supports DMA above 4 GB, allocations above 4 GB may be provided to devices that have not expressed support for it. So in addition to checking 'RootBridge->DmaAbove4G' to establish whether the root bridge itself supports DMA above 4 GB, we must also take into account the operation type (EfiPciOperationBusMaster{Read|Write|CommonBuffer}64), and the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, when mapping and allocating DMA memory, respectively. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
2016-09-06MdeModulePkg/XhciDxe: enable 64-bit PCI DMAArd Biesheuvel
PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-06MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMAArd Biesheuvel
PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-06MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMAArd Biesheuvel
PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-06MdeModulePkg/EhciDxe: enable 64-bit PCI DMAArd Biesheuvel
PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
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