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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
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Some processor may return small cache line size, we should return 32 bytes at
least for spin lock alignment.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
(cherry picked from commit 52f5bd2669916c54845eda8829b2f129b6088896)
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From Intel(R) 64 and IA-32 Architectures Software Developer's Manual, one lock
or semaphore is suggested to be present within a cache line. If the processors
are based on Intel NetBurst microarchitecture, two cache lines are suggested.
This could minimize the bus traffic required to service locks.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
(cherry picked from commit 5f0a17d83a6443931068d428600824276ca2bd37)
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Current AcquireSpinLock() will check if timeout happens when PcdSpinLockTimeout
is not zero, even though the spin lock is already released. It may do
unnecessary operation to read timer's counter. This update is trying to acquire
spin lock firstly. If it could be acquired successfully, needn't to check
timeout at all.
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
(cherry picked from commit 0f18e1eda2a807283484adfbf5eaae6a92b1ffa7)
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The HeaderLog field of the PCIe Extended Capabilities Advanced Error
Reporting structure was incorrectly defined as a 32-bit field. The PCIe
2.1 Base Specification, section 7.10, lists this as 16 bytes, or 4
DWORDs.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
(cherry picked from commit 0a38a95a35e30490be5ceab2517da37f8fcbb3fa)
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Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
(cherry picked from commit 415aa2f1cb915a00b2d91fdfb1798bb75bcaed09)
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It is the follow up of 3ab41b7a325ca11a12b42f5ad1661c4b6791cb49
to replace UnicodeStrToAsciiStr/AsciiStrToUnicodeStr with
UnicodeStrToAsciiStrS/AsciiStrToUnicodeStrS.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
(cherry picked from commit ca2ac9d521b595e969dbe65f1a19fd96d499fa61)
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Add UnicodeStrToAsciiStrS() and AsciiStrToUnicodeStrS() API.
These 2 safe version APIs are used to replace UnicodeStrToAsciiStr() and
AsciiStrToUnicodeStr() API.
The safe version string convert APIs use similar check as StrCpyS().
Cc: Liming Gao <Liming.Gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <Jiewen.Yao@intel.com>
Reviewed-by: Liming Gao <Liming.Gao@intel.com>
Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
(cherry picked from commit 3ab41b7a325ca11a12b42f5ad1661c4b6791cb49)
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Cc: Liming Gao <Liming.Gao@intel.com>
Cc: Amy Chan <Amy.Chan@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <Jiewen.Yao@intel.com>
Reviewed-by: Liming Gao <Liming.Gao@intel.com>
Reviewed-by: Amy Chan <Amy.Chan@intel.com>
(cherry picked from commit d3858e1006f3b88cb510f7c71452a53ff6f75c05)
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Update WSMT table link to official MSDN URL.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
(cherry picked from commit e6877b56b2e6d781fe0ce808318c779eb703657c)
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
(cherry picked from commit 19d539af756429815310ebaffb443409e94da809)
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The ComId for Block SID authentication command is
0x0005 according to "TCG Storage Feature Set: Block
SID Authentication Specification Version 1.0.0". Update code to
follow this spec requirement.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
(cherry picked from commit 81c1b6df92184f07446b6cf197b18c61ad8b73f0)
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buffer.
This patch adds more check in SmmIsBufferOutsideSmmValid(), to make sure that
SMM communication buffer is only EfiReservedMemoryType/EfiRuntimeServicesCode/
EfiRuntimeServicesData/EfiACPIMemoryNVS. So that the communication buffer will
not touch any OS memory.
The assumption is that a platform reports valid SMM communication buffer at
EndOfDxe, because EndOfDxe is last hook point that SMM code can call-out to
get memory map information.
A platform MUST finish SMM communication buffer allocation before EndOfDxe.
If a DXE or OS driver need do communication after EndOfDxe, it can either
allocate SMM communication buffer before EndOfDxe and save it, or consume
EDKII_PI_SMM_COMMUNICATION_REGION_TABLE table to get general fixed comm buffer.
This is designed to meet Microsoft WSMT table definition on FIXED_COMM_BUFFERS
requirement.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
(cherry picked from commit 91f51fcc84d9ce3b801fdd895e514cd5525975c7)
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This patch adds Windows SMM Security Mitigation
Table @ http://download.microsoft.com/download/1/8/A/18A21244-EB67-4538-BAA2-1A54E0E490B6/WSMT.docx
Cc: "Gao, Liming" <liming.gao@intel.com>
Cc: "Kinney, Michael D" <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Gao, Liming" <liming.gao@intel.com>
(cherry picked from commit 6a0d24221241bb1b13bafc7b2d264240d19d2993)
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The definitions are defined in TCG storage core and opal spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
(cherry picked from commit 79af8319e0d05a44defbc5c0d4d4fa211bd57888)
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Add UEFI2.6 MemoryAttributesTable GUID definition.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Gao, Liming" <liming.gao@intel.com>
(cherry picked from commit 9c06accda2cac131e54217097fc3abab35bbb348)
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Add UEFI2.6 MemoryAttributes Table definition header
file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Gao, Liming" <liming.gao@intel.com>
(cherry picked from commit 63ca5179dd60983527d17a31c0e44e0a3be5124f)
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Add NFIT definition from ACPI 6.1 for the NVDIMM Control Region
Structure Valid Fields for Manufacturing Location and Manufacturing Date
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
(cherry picked from commit 71a2a892658baac6301e81ad58a8abbc05fa17d2)
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Fix ACPI 6.0 and 6.1 NFIT GUID definitions to avoid GCC compiler error
for missing braces.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
(cherry picked from commit 5f87f979c6f5b05f97eab02f7e3c01fabeb839c6)
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Add missing definition in ACPI6.0 specification.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Gao, Liming" <liming.gao@intel.com>
(cherry picked from commit 08575c19df2fd0047850fdf9497d2828eeb80e4f)
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Add ACPI 6.1 definitions from the ACPI
Specification Revision 6.1 January, 2016.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Gao, Liming" <liming.gao@intel.com>
(cherry picked from commit f2e4f2fc066710a14b9d156801dddc69926397fe)
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Update Acpi.h to include latest Acpi6.1
header file.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Gao, Liming" <liming.gao@intel.com>
(cherry picked from commit 922db0fddcd27926bd0e43066d8c0ebe00ac53d9)
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MdePkg: Add AuditMode/DeployedMode name definition
Add AuditMode/DeployedMode definition from Enable Secure Boot feature defined in UEFI2.5 Mantis 1263.
https://mantis.uefi.org/mantis/view.php?id=1263
(Sync patch r19130 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Zeng Star <star.zeng@intel.com>
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MdePkg: Restore SetupMode macro definition
Restore SetupMode macro definition to keep backward compatibility. No current module is referencing them now.
(Sync patch r19175 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
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TPM TIS (TPM Interface Specification) is TCG standard.
Add definition here.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19739 6f19259b-4bc3-4df7-8a09-765794883524
(cherry picked from commit ac6f9d7c127523a9509ede36e053adff8acfdbe1)
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TPM PTP (Platform TPM Profile) is TCG standard.
Add definition here.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19738 6f19259b-4bc3-4df7-8a09-765794883524
(cherry picked from commit fb7abacad93b19489e24570277caeef4bb17abad)
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Microsoft updated secure MOR lock document with version 2.
So we update comment here.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed: "Zhang, Chao B" <chao.b.zhang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19687 6f19259b-4bc3-4df7-8a09-765794883524
(cherry picked from commit 31a9d3b419accbbc5463c71221b3b30a46f9ee73)
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This PciSegmentLib instance only supports Segment 0 access.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19657 6f19259b-4bc3-4df7-8a09-765794883524
(cherry picked from commit 32fa5588ff703507e82bd9c64d56e1baa4076f60)
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Add common HTTP 1.1 industry standard definitions for use in HTTP
clients/applications. List includes: HTTP methods, request/response
headers, and encodings.
(Sync patch r19435 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
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Update Ipmi2.0 definitions header files for data structure
name suffix for request/response data and completion code.
(Sync patch r19484 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daocheng Bu <daocheng.bu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19493 6f19259b-4bc3-4df7-8a09-765794883524
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Re-add Ipmi2.0 definitions header files based on Ipmi category:
App, Storage and etc.
In V3, the file name has been changed for short.
(Sync patch r19272 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Daocheng Bu <daocheng.bu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19492 6f19259b-4bc3-4df7-8a09-765794883524
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Raise the Tpl of async SCSI I/O callback function to TPL_NOTIFY to match
the behavior in ScsiDiskDxe driver.
(Sync patch r19453 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19474 6f19259b-4bc3-4df7-8a09-765794883524
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The ScsiExecuteSCSICommand() function in ScsiBusDxe driver will not signal
the event passed from UefiScsiLib when error occurs.
In this case, UefiScsiLib should close the event passing to
ScsiExecuteSCSICommand().
(Sync patch r19448 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19469 6f19259b-4bc3-4df7-8a09-765794883524
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Add 3 macro to TPM_RH Constants, which is in latest TPM2 spec.
(Sync patch r19230 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Zhang, Chao B" <chao.b.zhang@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19278 6f19259b-4bc3-4df7-8a09-765794883524
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(Sync patch r18415 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19277 6f19259b-4bc3-4df7-8a09-765794883524
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UefiDebugLibDebugPortProtocol is an implementation of DebugLib.
It calls EFI_DEBUGPORT_PROTOCOL.Write in DebugPrint and DebugAssert.
(Sync patch r18414 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Masamitsu MURASE <masamitsu.murase@gmail.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19276 6f19259b-4bc3-4df7-8a09-765794883524
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Four new functions are added to UefiScsiLib:
ScsiRead10CommandEx
ScsiWrite10CommandEx
ScsiRead16CommandEx
ScsiWrite16CommandEx
They support both blocking and non-blocking SCSI Read/Write operation
depending on the optional parameter 'Event' passed to those APIs.
When 'Event' is NULL, these four functions will call the non-EX version
couterparts to execute blocking SCSI I/O. When 'Event' is not NULL,
non-blocking I/O operation is executed.
(Sync patch r19214 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19221 6f19259b-4bc3-4df7-8a09-765794883524
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Restore SetupMode macro definition to keep backward compatibility. No current module is referencing them now.
(Sync patch r19175 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19192 6f19259b-4bc3-4df7-8a09-765794883524
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Add AuditMode/DeployedMode definition from Enable Secure Boot feature defined in UEFI2.5 Mantis 1263.
https://mantis.uefi.org/mantis/view.php?id=1263
(Sync patch r19130 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Zeng Star <star.zeng@intel.com>
Reviewed-by: Long Qin <qin.long@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19186 6f19259b-4bc3-4df7-8a09-765794883524
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C4701 & C4703 may cause false positive issues.
They have been disabled in VS2013.
(Sync patch r19111 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19118 6f19259b-4bc3-4df7-8a09-765794883524
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The extended interfaces GetControl/SetControl/SetAttributes are from
EmbeddedPkg/Include/Library/SerialPortExtLib.h.
(Sync patch r18963 from main trunk.)
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19013 6f19259b-4bc3-4df7-8a09-765794883524
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The "read" word in SerialPortWrite() header comment block should be
"write".
(Sync patch r18908 from main trunk.)
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19009 6f19259b-4bc3-4df7-8a09-765794883524
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(Sync patch r18907 from main trunk.)
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19008 6f19259b-4bc3-4df7-8a09-765794883524
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The BasePostCodeLibPort80 instance just prints UINT8 to IoPort 80. Some boards
may support 16bit or 32bit. To support them, new PCD PcdPort80DataWidth is
introduced to specify the width of data bits to Port80.
(Sync patch r18765 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Liming Gao <liming.gao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18871 6f19259b-4bc3-4df7-8a09-765794883524
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So that other module can also refer to them.
(Sync patch r18674 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com>
Reviewed-by: "Zeng, Star" <star.zeng@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18806 6f19259b-4bc3-4df7-8a09-765794883524
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Declare GetRandomNumber128 in RngLib.h.
Create GetRandomNumber128 in BaseRngLib, which is simply calling
GetRandomNumber64 twice.
A GetRandomNumber128 function allows platforms with 128bit HWRNGs to
save on IO overhead that comes from having to prime the HWRNG device
before each read operation.
Using the HWRNG installed on the HP ProLiant m400 moonshot cartridge,
this will save about 50ms per RAW Entropy operation as compared with
calling GetRandomNumber64 twice.
(Sync patch r18590 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Thomas Palmer <thomas.palmer@hpe.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Qin Long <qin.long@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18791 6f19259b-4bc3-4df7-8a09-765794883524
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Add one library class (RngLib.h) with three GetRandomNumber16/32/64
APIs to provide random number generator services, and one library
instance (BaseRngLib), based on Intel RdRand instruction access,
to provide high-quality random numbers generator.
(Sync patch r18519 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qin Long <qin.long@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18786 6f19259b-4bc3-4df7-8a09-765794883524
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Add AsmRdRand16/32/64 APIs for RdRand instruction access to generate
high-quality random number.
(Sync patch r18518 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Qin Long <qin.long@intel.com>
Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18785 6f19259b-4bc3-4df7-8a09-765794883524
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Fix spelling typos in EFI_HTTP_STATUS_CODE definitions for error 415 and 501.
(Sync patch r18521 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@hpe.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18523 6f19259b-4bc3-4df7-8a09-765794883524
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Add HttpMethodMax enum value to EFI_HTTP_METHOD to make it easier to iterate
through the HTTP methods using a loop.
(Sync patch r18520 from main trunk.)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@hpe.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18522 6f19259b-4bc3-4df7-8a09-765794883524
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