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Change code to integrate MR3 FSP.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Guo Mang <mang.guo@intel.com>
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Cleanup libraries for multi boards.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
CC: Mang Guo <mang.guo@intel.com>
CC: Shifei Lu <shifeix.a.lu@intel.com>
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BOARD_ID bits and GPIO pins mapping:
BOARD_ID0 GPIO_224(J45)
BOARD_ID1 GPIO_213(M47)
BOARD_ID2 GPIO_223(H48)
BOARD_ID3 GP_CAMERASB10(R34)
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: zwei4 <david.wei@intel.com>
CC: Mang Guo <mang.guo@intel.com>
CC: Shifei Lu <shifeix.a.lu@intel.com>
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RAM SIZE in frontpage is not correct. Pass correct DRAM density parameter to FSP to fix this issue.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: zwei4 <david.wei@intel.com>
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MCR parameter restored in the second time of boot, so the boot time is less than the first time of boot.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: zwei4 <david.wei@intel.com>
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These code cause HDMI cable of some vendor couldn't work.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
Reviewed-by: lushifex <shifeix.a.lu@intel.com>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Guo Mang <mang.guo@intel.com>
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