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This patch introduces I2c description, using the new structures
and template in MvHwDescLib. This change enables more flexible
addition of multiple I2c controllers and also allows for
removal of string PCD parsing. Update Armada 70x0 DB description
and PortingGuide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Simplify obtaining lane data, using arrays with direct enum values,
rather than strings. This is another step to completely remove
ParsePcdLib.
This patch replaces string-based description of ComPhy lanes
on Armada 70x0 DB with the enum values of type and speed -
for that purpose new [Defines] section was added to Armada.dsc.inc
file in order to increase readability.
PortingGuide is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Added PcdWatchdogCount to specify the number of Watchdog timers
that are available on Juno and FVP platform.
Also added DISABLE_SBSA_WATCHDOG option to disable the watchdog
timers if required for testing.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch correct style of two variables to the camel-case
version.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Although, hitherto support allowed for using configurable EraseSize,
the erase command was fixed to CMD_ERASE_64K. Also it was
assumed that EraseSize equals SectorSize, which is not true
for some flash devices. Fix both issues by adding new PCD
(gMarvellTokenSpaceGuid.PcdSpiFlashPageSize) and using
this parameter properly in MvSpiFlashUpdate routine instead
of the EraseSize. Also erase command is adjusted to the settings.
Update PortingGuide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Fix casting and related issues to make this code build for 32-bit ARM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Fix casting and related issues to make this code build for 32-bit ARM.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Fix a misplaced closing parenthesis.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch makes use of recently added SPI configuration
PCDs and sets CS with SCLK mode on Armada 7040 DB.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Until now transfer SCLK mode and CS were fixed, when using
shell 'sf' command. This patch enables their configuration.
Update porting guide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch prevents possible NULL pointer dereference
during SPI transfers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Joe Zhou <shjzhou@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Make log information clear where it came from and return correct code to
be interpreted by caller.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch introduces following improvements to the PortingGuide
* Replace split documentation with single file
* Update paths to new directory structure in edk2-platforms
* Align format to Doxygen constraints
Moreover the PortingGuide and remaining Drivers' documentation
is moved to the new location under Silicon/Marvell, where in future
all other bits of the support will be moved.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The PerTuning function is not stable, it will cause the
LSI SAS 3008/3108 crash, disable this function first.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chenhui Sun <chenhui.sun@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are
0x20000000 and 0x30000000 based. These addresses overlap with the DDR
memory range 0-1G. In this situation, on the inbound direction, our pcie
will drop the DDR address access that are located in the pci range window
and lead to a dataflow error.
Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000
and decrease PciRegion Size accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Fix bug of PcieRegion size definition and IO size definition.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Value of the environment variable FIRMWARE_VER is GIT SHA by default,
and you can add the environment variable FIRMWARE_VER to EXTRA_OPTIONS
at build time to specify something else, eg. "16.12-<commit id>".
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The drivers build from separate sources, their GUID should
be different.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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1. Add Drivers/SasPlatform;
2. Add Drivers/Net/SnpPlatform;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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1. Add Drivers/SasPlatform;
2. Add Drivers/Net/SnpPlatform;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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A recent change in edk2:
EmbeddedPkg/EmbeddedPkg.dsc: fix build for non-ARM architectures
actually broke the build for AARCH64 architectures (well Juno, really).
The PCD moved, PcdIsp1761BaseAddress, is used by
edk2\EmbeddedPkg\Drivers\Isp1761UsbDxe\Isp1761UsbDxe.inf, which was
included by Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc
This patch moves the Isp1761UsbDxe.inf to [Components.ARM] so that it
doesn't invoke the PCD for Juno.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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After Pp2Dxe data migrated to MvHwDescLib, both controllers
could be used, but not at the same time. It was caused by
ports' insufficient description. This patch fixes this problem by
introducing new PCD responsible for the mapping between port and
its controller. Also it was possible to remove redundant
PcdPp2NumPorts. Update documentation accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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This patch introduces Pp2Dxe description, using the new structures
and template in MvHwDescLib. This change enables more flexible
addition of multiple Pp2Dxe controllers. For that purpose, static global
variables (BufferLocation and Mvpp2Shared) had to be replaced by
dynamically allocated resources. PortingGuide is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Modify ethernet Port0 and Port1 types to be on par with the board
settings. Initial support required extra extension boards and
converters. This patch sets ports to following settings:
* Port0 (eth0) -> SFI @ 10Gbps
* Port1 (eth1) -> SGMII over 88E1512 PHY @ 1Gbps
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Increase Rx ring and BM pool size for each port, which is
helpful when dealing with more intense incoming network
traffic.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Joe Zhou <shjzhou@marvell.com
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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In order to operate simultaneously properly, all ports
should use their own resources instead of shared BM
Pool and queues.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Joe Zhou <shjzhou@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Since now SerDes can be properly configured to support 10G
link, add this feature to the Armada 7k/8k network driver
as well. This patch extends low-level configuration routines
with SFI additions, which required two new fields in
PP2DXE_PORT structure (XpcsBase and MpcsBase).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Registers' offset are constant for each PP2 controller instance,
so use macros with relative addresses for their description.
This allowed to remove 5 PCD's and will ease enabling second
controller on Armada8k. Update PortingGuide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Remove the shared ArmDmaLib resolution from the shared .dsc include
file: it will be removed soon from upstream EDK2. Instead, replace
it with an explicit NonCoherentDmaLib resolution for each driver that
depends on DmaLib. This makes it more obvious which peripherals are
non cache coherent, and forces derived platforms to choose a DmaLib
resolution explicitly for newly added drivers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Instead of hardcoding the non-cache coherent nature of this device
by invoking UncachedMemoryAllocationLib directly for allocating
shared buffers, switch to DmaLib, which encapsulates this at a
more abstract level. This allows the driver to be shared with
platforms that are cache coherent (by simply switching to another
DmaLib implementation), and removes the hardcoded dependency on
UncachedMemoryAllocationLib, which will be removed from upstream
EDK2.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Marcin Wojtas <mw@semihalf.com>
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The HiKey platform does not incorporate any drivers that depend on
the DmaLib library class so we can remove the resolution for it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Nothing in the ARM builds depends on DmaLib anymore, so let's remove
the resolution for it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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No ARM platforms depend on UncachedMemoryAllocationLib anymore, so
remove the library class resolution for it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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We no longer need a resolution for UncachedMemoryAllocationLib so
remove it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Replace the open coded PCI 'emulation' with a simple call into
the NonDiscoverable device registration library, and fix up all
platform .DSCs/FDFs accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Remove the references to ArmDmaLib and UncachedMemoryAllocationLib
from the various Styx based platforms. They are intended for non-cache
coherent DMA only, which is not used on these platforms.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The comment indicating that only the first SATA controller is operational
on SoftIron-branded OverDrive 3000 boards is incorrect. Re-enable the
second SATA controller.
Signed-off-by: Alan Ott <alan@softiron.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Import Armada 70x0 suppport from OpenPlatformPkg,
together with its documentation and utilities.
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
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Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
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Common files for AMD Overdrive, SoftIron Overdrive 1000
and LeMaker Cello, as well as actual platform support.
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
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Import ARM Ltd. platforms Juno, FVP, TC2 at commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
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