summaryrefslogtreecommitdiff
path: root/Silicon/BroxtonSoC/BroxtonSiPkg
AgeCommit message (Collapse)Author
2017-05-09Fix S3 resume failureGuo Mang
When restoring MSR for S3 setting, SmmStartupThisAp will return error if CPU index is BSP. This issue caused S3 resume failed sometimes. This patch is mainly fix this issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Add SATA initialization.lushifex
Add additional SATA initialization code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Fix get variable issueGuo Mang
Fix "AcpiGlobalVariable" couldn't be get issue. S3 memory info was saved in this variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Add PEI SPI library.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09Add BPDT library.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09Fix MRC restore issueGuo Mang
MCR parameter restored in the second time of boot, so the boot time is less than the first time of boot. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Fixed Map-r issue.Lu, ShifeiX A
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-05-09SPI Flash Lock.zwei4
Cleanup code about locking SPI Flash; Change the default value of BIOS Lock setup option to FALSE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com>
2017-05-09Add SPI modules.lushifex
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
2017-05-09Change MRC parameterGuo Mang
These code cause HDMI cable of some vendor couldn't work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: lushifex <shifeix.a.lu@intel.com>
2017-05-09Fix MRC parameters restore failure issueGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09Add USB peripheral modeGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
2017-05-09Restore P2SB MMIO resourcezwei4
Restore P2SB's, as well as GPIO controllers', MMIO resources to original values which have been overridden by PCI bus driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09Remove platform policyzwei4
Remove silicon platform policy which is not used by any silicon code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com> Reviewed-by: Mang Guo <mang.guo@intel.com>
2017-05-09Fix build error.Wei, David
Fix build error for latest VS2015 compiler with IA32 tip. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Remove platform policies which are not used.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09BroxtonSiPkg: Add VariableStorageGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SampleCode/MdeModulePkgGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SampleCode/IntelFrameworkPkgGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SampleCode/IncludeGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add HeciGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add Txe/Include/ and Txe/LibraryGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SiInitGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add Include and LibraryGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SmmControlGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SdioGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09Add ScSmiDispatcherGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add ScInitGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SataControllerGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SampleCodeGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add ResetGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add Include and LibraryGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SaInitGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add PciHostBridgeGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add MemoryInitGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add NorthCluster/AcpiTablesGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SmmAccessGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SecCoreGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add ResetVectorGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add PowerManagementGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add CpuInitGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add Cpu/AcpiTablesGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add Cpu Include file and LibraryGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add IncludeGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add LibraryGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add BroxtonSiPkg .dsc and .dec filesGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 18:10:57 +0000