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2018-02-07Hisilicon/Smbios: Indicate use of ProcessorFamily2 in type 4 tableHeyi Guo
modify processorFamily of type 4 to ProcessorFamilyIndicatorFamily2, indicator to obtain the processor family from the Processor Family 2 field. ProcessorFamily2 is already specified as ProcessorFamilyARM in the existing table. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-07Hilisicon: Change DmaLib to CoherentDmaLibHeyi Guo
Unify all D0x(include D06 in further) to cache coherent DmaLib. This can improve boot speed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Wang Yue <wangyue41@huawei.com> Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-07Hisilicon D03/D05: Open SnpPlatform source codeHeyi Guo
1. This driver install a protocol for SnpPV600Dxe driver. The protocol indicate which ethernet port to use and port sequence. 2. Fixed bug:Confusing Ethernet port sequence. Move the most right Ethernet port (when looking from the front of the chassis) to the first one in BootManage for PXE boot. https://bugs.linaro.org/show_bug.cgi?id=2657 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com> Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2018-02-07Hisilicon D03/D05: Open SasPlatform source codeHeyi Guo
This module install a protocol for SasDriverDxe. the protocol include main information of sas controller, like controller ID, enable or disable,base address of registers. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com> Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2017-10-05Platform/Hisilicon: fix D02 driver indentation errorsLeif Lindholm
When building with a somewhat recent toolchain (GCC 6.3), the D02 platform fails due to (the implicit) -Werror=misleading-indentation. Cc: Heyi Guo <heyi.guo@linaro.org> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2017-10-05Hisilicon/D03/D05: Add AddressTranslationOffset supportYan Zhang
Assign valid value to AddressTranslationOffset to support address translation between domains of CPU and PCIe, which is need by GOP to enable frame buffer. This patch fix the bug: Kernel (4.12, without the vga driver) boot hang with kernel panic while kernel accesses UEFI GOP frame buffer. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yan Zhang <zhangyan81@huawei.com> Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-10-05Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device.Jason zhang
1. Because Hi161x chip doesn't support "ARI Forwarding Enable" function, BIOS will enumerate 32 same devices (Device Number 0~31) when a Non-ARI capable device attached in the RP. Hi161x chip will not fix it, need BIOS patch. 2. Just enlarge iatu for those root port with ARI capable device attached, Non-ARI capable device's RP, keep iatu limitation. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason zhang <zhangjinsong2@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-10-05Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBaseHeyi Guo
Io BAR should be based IoBase and Mem BAR should be based PciRegionBase. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang <huangming23@huawei.com> Signed-off-by: Heyi Guo <heyi.guo@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-08-29Silicon/Hisilicon: switch to NonDiscoverable driver for EHCIArd Biesheuvel
Replace the open coded PCI 'emulation' with a simple call into the NonDiscoverable device registration library, and fix up all platform .DSCs/FDFs accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-08-29Silicon/Hisilicon/SasV1Dxe: remove bogus UncachedMemoryAllocationLib refArd Biesheuvel
This driver does not actually use UncachedMemoryAllocationLib anymore, so remove the bogus reference. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-08-03Platform,Silicon: Import Hisilicon D02,D03,D05 and HiKeyLeif Lindholm
Imported from commit efd798c1eb of https://git.linaro.org/uefi/OpenPlatformPkg.git Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>