| Age | Commit message (Collapse) | Author |
|---|
|
Commit 4bf95a9f361e ("MdeModulePkg/ResetSystemRuntimeDxe: Add more
debug message") broke the DEBUG build for all platforms that rely on
MMIO mapped UART devices, since it introduces a DEBUG() print that
may trigger at runtime, at which such UART devices are usually not
mapped, resulting in an OS crash.
Given that this mostly only affects ARM and AARCH64, it is not unlikely
that similar inadvertent breakage will occur again in the future, so
let's fix this once and for all by switching affected platforms to the
new DxeRuntimeDebugLibSerialPort DebugLib implementation that takes care
not to touch the UART hardware after ExitBootServices().
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
A set of mostly Ebl-related Pcds are about to be deleted from
edk2. Delete references to them here to keep platforms building.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Remove unused ArmPlatformPkg PCDs from all platform descriptions.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
'PciEmulation' is not a proper naming for a driver, which
uses NonDiscoverableDeviceRegistrationLib for handling
the devices attached via internal bus of the SoC.
Rename it to MvNonDiscoverableDxe and move under
Silicon/Marvell/Drivers directory.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
MvEeprom driver nesting into additional Devices directory
under Silicon/Marvell/Drivers/I2c is redundant. Align
its level with MvI2cDxe.
Change MvEeprom to MvEepromDxe in order to be
more consistent in Marvell drivers naming.
On the occasion add sorting in the .inf file.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
MvPhyDxe driver nesting into additional Phy directory
under Silicon/Marvell/Drivers/Net is redundant. Align
its level with MvMdioDxe and Pp2Dxe.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Hitherto MvSpiDxe driver name was very generic. In order to
be ready for adding new SPI master drivers, use the controller's
traditional name (it's called SPI Orion in Linux and
U-Boot) for files and the entry point.
Additionally, move the files to new 'MvSpiOrionDxe' directory
and rename the 'Devices' and 'Variables' to reflect actual drivers'
names. Change MvSpiFlash to MvSpiFlashDxe in order to be
more consistent. On the occasion add sorting in the .inf files.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
As a part of files reorganization, switch to using '7k8k'
in all SoC-specific driver/library code instead of
'70x0'/'7040', so that to ensure consistent naming for
entire SoC family.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
In edk2-platforms it is expected to provide a separation between
SoC and boards files in 'Silicon' and 'Platform' directories
accordingly.
This patch aligns Marvell code to this requirement with no functional
changes in the actual source files, unless required due to modified
paths. Change the supported board's files names to proper Armada70x0Db.
Also rename 'Armada' directory to 'Armada7k8k' in order to properly
refer to the SoC family and prevent confusion in future, when
adding new Armada machines. On the occasion add ARM copyright,
which was wrongly missing in the dsc.inc file.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Hitherto mechanism of fixing SPI flash model in the PCDs,
occured to be very inefficient and problematic. Enable
dynamic detection by reworking MvSpiFlashReadId() command,
which now uses newly added NorFlashInfoLib, that helps to
obtain description of the JEDEC compliant devices.
This patch updates the MvSpiFlashProtocol ReadId() protocol
callback on both producer's (MvFlashDxe) and consumers' sides
(FirmwareUpdate and SpiTool applications). Because all
information about detected SPI NOR flash is now stored in
the obtained NorFlashInfo structure fields, use them instead
of the PCDs.
Enable compilation of the NorFlashInfoLib and update
PortingGuide documentation accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
When switching to generic PSCI reset library, obsolete parts
of previous custom reset library (PCDs, documentation) remained.
Remove them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This patch removes tabs and wrong line endings in the file, maiking
it acceptable to the PatchCheck.py script.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Hitherto PHY handling in Pp2Dxe was not flexible. It allowed for using
only single MDIO controller, which may not be true on Armada 80x0 SoCs.
For this purpose introduce the MDIO description, using the new structures
and template in MvHwDescLib. This change enables addition of multiple
CP110 hardware blocks with MDIO controllers.
This change required different PHY handling and obtaining data over
desired MDIO bus. Now given Pp2 port is matched with the PHY via
its index in gMarvellTokenSpaceGuid.PcdPhyDeviceIds. The PHY itself
is mapped to the MDIO controller, using
gMarvellTokenSpaceGuid.PcdPhy2MdioController. Also obtaining
SMI addresses was moved to the PHY initialization routine.
All above allow for much cleaner and logical PHY description
in the .dsc file, which now uses macros for connection type
and speed.
Update PortingGuide documentation accordingly and Armada 70x0 DB
NIC/PHY description.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This patch introduces UTMI description, using the new structures
and template in MvHwDescLib. This change enables more flexible
addition of multiple CP with UTMI PHY's and also significantly
reduces amount of used PCD's for that purpose. Update PortingGuide
documentation accordingly.
This patch replaces string-based description of Utmi on
Armada 70x0 DB with new, reduced format, which uses macros
in Armada.dsc.inc file for better readability.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This patch introduces I2c description, using the new structures
and template in MvHwDescLib. This change enables more flexible
addition of multiple I2c controllers and also allows for
removal of string PCD parsing. Update Armada 70x0 DB description
and PortingGuide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Simplify obtaining lane data, using arrays with direct enum values,
rather than strings. This is another step to completely remove
ParsePcdLib.
This patch replaces string-based description of ComPhy lanes
on Armada 70x0 DB with the enum values of type and speed -
for that purpose new [Defines] section was added to Armada.dsc.inc
file in order to increase readability.
PortingGuide is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Although, hitherto support allowed for using configurable EraseSize,
the erase command was fixed to CMD_ERASE_64K. Also it was
assumed that EraseSize equals SectorSize, which is not true
for some flash devices. Fix both issues by adding new PCD
(gMarvellTokenSpaceGuid.PcdSpiFlashPageSize) and using
this parameter properly in MvSpiFlashUpdate routine instead
of the EraseSize. Also erase command is adjusted to the settings.
Update PortingGuide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Until now transfer SCLK mode and CS were fixed, when using
shell 'sf' command. This patch enables their configuration.
Update porting guide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This patch introduces following improvements to the PortingGuide
* Replace split documentation with single file
* Update paths to new directory structure in edk2-platforms
* Align format to Doxygen constraints
Moreover the PortingGuide and remaining Drivers' documentation
is moved to the new location under Silicon/Marvell, where in future
all other bits of the support will be moved.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
