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2018-02-14IDTP9180 PMIC Power Sequence Configuration.zwei4
Change Bit 2 (SUSPWRDNACKCFG) of Power Sequence Configuration register (offset 0x2A) to 1. If SUSPWRDNACKCFG is 0, SUSPWRDNACK signal is ignored. PMIC will not go to G3 when SUSPWRDNACK goes high in S4 state. If SUSPWRDNACKCFG is 1, PMIC responses to SUSPWRDNACK signal. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 <david.wei@intel.com>
2018-02-13SMBus Host driver.zwei4
Add Apollo Lake SMBus host controller DXE driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 <david.wei@intel.com>
2018-02-12SMBus Library.zwei4
Apollo Lake South Cluster SMBus executive code, which is common for PEI, DXE and SMM modules. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 <david.wei@intel.com> Cc: Mang Guo <mang.guo@intel.com>
2017-12-22I2S Audio Configurezwei4
Customize I2S virtual bus ID for different boards. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 <david.wei@intel.com>
2017-12-20Build Script.lushifex
Add build script for E0 stepping LeafHill FAB D CRB board. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-12-05Spi driver changeGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-11-24Minnowboard3 Next Pre-production.zwei4
Add code for Minnowboard3 Next pre-production board. Build Command: BuildBios /vs13 /MX /A Broxton Release. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 <david.wei@intel.com>
2017-11-15SueCreek Bypasszwei4
Add code in ACPI table for TI audio codec under I2C5. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 <david.wei@intel.com>
2017-11-15fTPMxianhu2x
Boot failed after PTT is enabled with gcc-built image Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: xianhu2x <xianhuix.liu@intel.com>
2017-10-10Enable SueCreekYeon Sil Yoon
1. Change SPI mode and speed for SueCreek 2. Update SueCreek HOST_IRQ and HOST_RST GPIO configuration 3. Add a PCD to make sure that SueCreek only reported to OS when it is actually present on the board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yeon Sil Yoon <yeon.sil.yoon@intel.com> Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-09-27Changed Max Baud RateGuo Mang
Change Max Baud Rate to 115200. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-09-21Calibrate PMIC IMON.zwei4
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 <david.wei@intel.com>
2017-09-12Change Reset TypeLu, ShifeiX A
Change Reset Type according to different Board. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-09-05Change reset type.zwei4
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 <david.wei@intel.com>
2017-08-24BroxtonSiPkg: Add I2CLibPeiGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-08-04Enable source level debug.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-08-04Change ResetVector.ia32.port80.rawGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-07-28Integrate MR3 FSPGuo Mang
Change code to integrate MR3 FSP. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-07-06Enable GCC Yocto S3Guo Mang
Enable GCC build BIOS image Yocto S3 support. Replace CPU drivers with drivers from core packages. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-06-13Change eMMC device path.zwei4
Signed-off-by: zwei4 <david.wei@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0
2017-06-09Add eMMC/SD.Lu, ShifeiX A
Add Platform eMMC/SD driver. This reverts commit 66d48af2d24645263b8068e261abc58d84cc2b93. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-05-26Using Core eMMC/SD driver.Lu, ShifeiX A
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-05-26GCC build support.zwei4
Change code which is not compatible with GCC. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-24BroxtonSiPkg:Fix Debug image assert issueGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-14Fix GCC build errors.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-12Fix some GCC build error.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-11Fixed some GCC build errors.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09Extend IBB region.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09Upgrade coreGuo Mang
Upgrade core to UDK2017 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Add script to build ResetVector.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09Fix S3 resume failureGuo Mang
When restoring MSR for S3 setting, SmmStartupThisAp will return error if CPU index is BSP. This issue caused S3 resume failed sometimes. This patch is mainly fix this issue. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Add SATA initialization.lushifex
Add additional SATA initialization code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Fix get variable issueGuo Mang
Fix "AcpiGlobalVariable" couldn't be get issue. S3 memory info was saved in this variable. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Add PEI SPI library.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09Add BPDT library.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09Fix MRC restore issueGuo Mang
MCR parameter restored in the second time of boot, so the boot time is less than the first time of boot. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Fixed Map-r issue.Lu, ShifeiX A
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com>
2017-05-09SPI Flash Lock.zwei4
Cleanup code about locking SPI Flash; Change the default value of BIOS Lock setup option to FALSE. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: David Wei <david.wei@intel.com>
2017-05-09Add SPI modules.lushifex
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
2017-05-09Change MRC parameterGuo Mang
These code cause HDMI cable of some vendor couldn't work. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: lushifex <shifeix.a.lu@intel.com>
2017-05-09Fix MRC parameters restore failure issueGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09Add USB peripheral modeGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
2017-05-09Restore P2SB MMIO resourcezwei4
Restore P2SB's, as well as GPIO controllers', MMIO resources to original values which have been overridden by PCI bus driver. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09Remove platform policyzwei4
Remove silicon platform policy which is not used by any silicon code. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com> Reviewed-by: Mang Guo <mang.guo@intel.com>
2017-05-09Fix build error.Wei, David
Fix build error for latest VS2015 compiler with IA32 tip. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: lushifex <shifeix.a.lu@intel.com> Reviewed-by: zwei4 <david.wei@intel.com>
2017-05-09Remove platform policies which are not used.zwei4
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 <david.wei@intel.com>
2017-05-09BroxtonSiPkg: Add VariableStorageGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SampleCode/MdeModulePkgGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SampleCode/IntelFrameworkPkgGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
2017-05-09BroxtonSiPkg: Add SampleCode/IncludeGuo Mang
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Guo Mang <mang.guo@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 05:55:30 +0000