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Add description of SBSA watchdogs to ACPI GTDT on D05.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chenhui Sun <sunchenhui@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Hi1616 GIC does not fully support GICv2 legacy mode, and SBSA watchdog
interrupts 400 and 496 cannot be signaled to CPU, so we switch to pure
GICv3 mode.
For other Hisilicon platforms, we suppose they don't need V2 legacy
mode either if they have GICv3. D03 also works for this patch. If the
platforms only have GICv2, this change will have no impact on them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: gongchengya <gongchengya1@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Timer is always working on Hisilicon D0x, even system enters WFI/WFE,
and there is no other low power status, so we set "always-on" flag in
ACPI GTDT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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The Designware PCIe IP in the SynQuacer SoC needs a little help to
appear sane to the OS. Not only does it lack a true root port, and
therefore does not perform any filtering whatsoever of type 0 config
TLPs that are not intended for the link peer, it also has trouble
issuing 64-bit wide MMIO accesses, which are often used on MMIO BARs
with memory semantics (e.g., frame buffers).
So let's create a stage 2 mapping covering the entire physical address
space, and remap some ECAM regions and demote write combine attributes
to device/strongly ordered. This is not a water tight fix, but it does
work around the issues in the majority of cases.
(Note that the ECAM remapping can also be addressed in the SMMU mapping
of the PCIe IP exposed to the CPU, but this is currently under
development, and it does not hurt to have it in two places)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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It is no longer necessary to inhibit DEBUG() calls at runtime, due to
the fact that we switched to a DebugLib implementation that takes care
of this. Since a platform could theoretically wire up DXE_RUNTIME_DRIVER
modules to a DebugLib/SerialPortLib implementation combo that does remap
the UART MMIO region for runtime and produces UEFI debug output on a UART
that is not owned by the OS, it is better not to handle this in the
driver directly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Commit 4bf95a9f361e ("MdeModulePkg/ResetSystemRuntimeDxe: Add more
debug message") broke the DEBUG build for all platforms that rely on
MMIO mapped UART devices, since it introduces a DEBUG() print that
may trigger at runtime, at which such UART devices are usually not
mapped, resulting in an OS crash.
Given that this mostly only affects ARM and AARCH64, it is not unlikely
that similar inadvertent breakage will occur again in the future, so
let's fix this once and for all by switching affected platforms to the
new DxeRuntimeDebugLibSerialPort DebugLib implementation that takes care
not to touch the UART hardware after ExitBootServices().
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Wire up the various drivers for the 96Boards LS connector and the
optional Secure96 mezzanine board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This adds support for using the random number generator in the Atmel
AtSha204a over I2C. Other functionality of the chip is currently
unsupported.
Note that the the I2C support in this device essentially violates the
protocol layering, by requiring that the device is woken up by driving
SDA low for a certain amount of time, which is something that cannot be
expressed in terms of an I2C packet sent to the device's slave address.
Instead, the slave address 0x0 is added to the device's address array,
and the wake is sent by sending a dummy write to address 0x0, and
ignoring the subsequent error. This requires the I2C bus to be clocked
at 100 kHz.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Currently, SynQuacerI2cStartRequest() increases the TPL to TPL_HIGH_LEVEL
while accessing the I2C controller hardware, but fails to restore the TPL
to the original level if the call to SynQuacerI2cMasterStart() fails, and
returns right away. Given the TPL_HIGH_LEVEL implies that interrupts are
disabled, this results in a complete system hang. So instead, break out
of the loop, so that the TPL restore will occur before leaving the
function.
Note that this will result in the bus control bits to be de-asserted in
case of a failure to send the START condition, which is an appropriate
cleanup action to take after SynQuacerI2cMasterStart() fails.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add a node for the I2C controller #1 to the device tree so the OS
may attach to it. This is the I2C controller that is attached to the
96boards mezzanine connector on Developer Box.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add a node for the SPI controller to the device tree so the OS may
attach to it. This is the SPI controller that is attached to the
96boards mezzanine connector on Developer Box.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Dw8250SerialPortRuntimeLib only exists in D02.
DebugLib isn't necessary on HiKey platform. So add CONFIG_NO_DEBUGLIB
on it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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edk2 commit 1ec2e7d0e8db
("MdeModulePkg/DxeCapsuleLibFmp: Use BmpSupportLib") broke the build of
all platforms that include DxeCapsuleLibFmp, since none of them included
a BmpSupportLib (added as part of the same series).
BmpSupportLib itself depends on SafeIntLib, so add the two libraries to
all affected platforms.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
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PcdCacheEnabled was never useful for these platforms, but it was
copied over from other platforms used as templates.
Delete it here to keep the platforms building once the Pcd is removed
from EmbeddedPkg.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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PcdCacheEnabled was never useful for these platforms, but they copied it
over from other platforms used as templates.
Delete it here to keep the platforms building once the Pcd is removed
from EmbeddedPkg.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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On our SynQuacer based platform, power state handling and other
low-level duties are handled by the secure firmware, not by the
OS, so remove the various MHU/SCPI related nodes from the device
tree.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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We already disable SDR104 support on the SynQuacer eMMC controller to
work around the need for a special tuning quirk that is difficult to
implement without modifying the generic driver, even in the presence
of a SD/MMC override protocol designed to carry such quirks.
Unfortunately, as it turns out, DDR50 does not work either with the
particular 8 GB Kingston part that has been fitted on the rev0.2/0.3
96board samples. Since the mode UEFI drives the eMMC in is independent
from what the OS chooses, and the fact that you would not use eMMC in
the first place if performance was a major concern, let's just disable
DDR50 as well, and fall back to SDR50 mode.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add PXM method for Pcie device, HNS device and SAS device.
Add STA method for HNS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: hensonwang <wanghuiqiang@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
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Add ITS affinity structure in SRAT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
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In order to replace command line parameter pcie_aspm=off, BIOS needs to
disable Pcie Aspm support during Pcie initilization.
D03 and D05 do not support PCIe ASPM, so we disable it in BIOS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yan Zhang <zhangyan81@huawei.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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modify processorFamily of type 4 to ProcessorFamilyIndicatorFamily2,
indicator to obtain the processor family from the Processor Family 2 field.
ProcessorFamily2 is already specified as ProcessorFamilyARM in the existing
table.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Unify all D0x(include D06 in further) to cache coherent DmaLib.
This can improve boot speed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wang Yue <wangyue41@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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1. This driver install a protocol for SnpPV600Dxe driver.
The protocol indicate which ethernet port to use and port sequence.
2. Fixed bug:Confusing Ethernet port sequence.
Move the most right Ethernet port (when looking from the front
of the chassis) to the first one in BootManage for PXE boot.
https://bugs.linaro.org/show_bug.cgi?id=2657
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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This module install a protocol for SasDriverDxe. the protocol
include main information of sas controller, like controller ID,
enable or disable,base address of registers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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This module support updating the boot CPU firmware only.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Modify the feature of BMC set boot option as switching generic
BDS. Break BMC SetBoot option out into BmcConfigBootLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Hisilicon-specific PlatformBootManagerLib added. It is convenient
to add specific feature, like BMC control boot option.
Remove Intel BDS from dsc file because it is out of use.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Add Processor Properties Topology Table, PPTT include
Processor hierarchy node, Cache Type Structure and ID structure.
PPTT is needed for lscpu command to show socket information correctly.
https://bugs.linaro.org/show_bug.cgi?id=3206
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reveiwed-by: Jeremy Linton <jeremy.linton@arm.com>
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Move definition of Madt struct to head file, so PPTT driver
can include it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reveiwed-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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A set of mostly Ebl-related Pcds are about to be deleted from
edk2. Delete references to them here to keep platforms building.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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A set of mostly Ebl-related Pcds are about to be deleted from
edk2. Delete references to them here to keep platforms building.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Add the first part of the flash device (FD) to the capsule image so we
can update the secure and SCP firmware in one go along with the UEFI
firmware volume (FV).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Implement support for the SynQuacer eMMC controller. This involves an
implementation of the SD/MMC override protocol to handle a couple of
quirks that would otherwise prevent this IP from being driven by the
generic SDHCI driver.
Also, add a HII page to the PlatformDxe driver that allows eMMC support
to be enabled, and wire it up for both DeveloperBox and EVB.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Reuse the BootLogoLib graphical progress bar to show the progress of a
capsule update, and in absence of a graphical console, write a period
to the text console for each block updated.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Even though the ARM ARM quite clearly states that the CNTFRQ field of
each MMIO timer frame should be a read-only alias of the CNTFRQ field
of the base frame, the SynQuacer SoC implements it as a register that
is programmable separately.
So let's program it from the hardware rather than overriding the
frequency using a DT property.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add menu options to the SynQuacer Platform menu screen to limit the
maximum PCIe link speed for each slot individually. This may be useful
to work around potential PCIe issues.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The upstream version of the Linux NETSEC driver expects the PHY DT
node to appear under a MDIO subnode, so fix this in the device tree.
Fix the node name as well, this should be 'ethernet' not 'netsec',
and add a clock-names property describing the single clock reference
as 'phy_ref_clk'.
Also, move the PHY subnode into the per-platform .dts file so we can
set the unit address in the node name. This is necessary because recent
versions of the DT compiler are more finicky about this.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Align the UART DT nodes:
- use 'uart' not 'fuart' as node name for the second serial port
- create an alias 'serial1' for the second serial port
- use UART clock reference instead of hardcoded frequency
- split 'clocks' property into 1 cell per phandle
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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To ensure that the I2C master protocol is installed immediately onto
the handles created by PlatformDxe in its entry point, force the
SynQuacerI2cDxe driver to be loaded before PlatformDxe. These handles
are recursively connected by the DXE core as soon as they appear, and
so ensuring that the I2C master protocol driver is available at this
time will ensure that these handles will be connected to it right away.
This is useful when implementations of architectural protocols such as
RTC or the EFI variable store, which should become available long before
the ordinary dispatch of UEFI driver model drivers is started at the end
of DXE, are based on I2C.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Remove a %r without an associated parameter.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Instead of registering a notification callback on the driver binding
protocol, and attempting to connect our I2C master handle each time
a new driver is registered, switch to the more obvious approach of
registering a notification callback on the I2C master protocol directly.
The original code was written under the assumption that it would make
the RTC available at an earlier time, but given that all handles that
are created during the execution of a driver entry point are connected
by DXE core right away (i.e., before StartImage() returns), this is not
really necessary, and in fact, may result in the driver already having
been connected by the time we attempt to connect it.
Note that it is now up to the platform to ensure that ConnectController()
is called for the handle if DXE core does not call it by itself, or does
call it but at a time when no I2C master protocol driver is available
yet.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Do a global replace of gPcf8563RealTimeClockLibI2cMasterProtolGuid with
gPcf8563RealTimeClockLibI2cMasterProtocolGuid.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The ASM1061 SATA controller integrated into the DeveloperBox board
emits too much electromagnetic radiation, so it needs spread spectrum
mode enabled.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Remove unused ArmPlatformPkg PCDs from all platform descriptions.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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For some reason, the Asmedia 118x PCIe switch needs a little help to
make sure that the downstream links train at Gen2 speed. So add a
PCI I/O protocol notifier that implements this for each PCIe downstream
port that is present on the system.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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In order to be able to use UART #0 on the DeveloperBox's 96boards low
speed connector, expose it to the OS by adding a node to the device
tree. This requires a CM3 firmware build that makes the SCP detach
from the serial port after boot.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Masahisa KOJIMA <kojima.masahisa@socionext.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The EVB does not boot if PCI RC #0 has no card inserted, and will hang in
the PCIe initialization code. So let's check the presence detect GPIO,
and only enable PCI RC #0 if it is asserted.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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If a PCIe RC is not enabled (due to the fact that the slot is not
populated), set its DT node 'status' property to 'disabled' so that
the OS will not attempt to attach to it.
This means we will need to switch from the default DtPlatformDtbLoaderLib
to a special one for our platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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In order to accommodate the EVB, whose PCIe RC #0 should not be touched
by software if no card is inserted, add a PCD that tells the PCIe driver
code which RCs should be initialized and exposed to the PCI host bridge
driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Attempt to adhere more closely to the PCIe spec by ensuring that PERST#
remains asserted for at least 100 ms. Give it a good margin, and delay
for 150 ms; the additional boot time delay is not going to be noticeable
by anyone anyway.
Add some missing barriers as well, so that the reset takes effect right
when we think it does.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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