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In order to support capsule update, implement PlatformFlashAccessLib that
exposes write access to the UEFI NOR partition.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Wire up the non-volatile EFI variable store support, by switching from
the emulation driver to the real one, and enabling the prerequisite
FTW and NOR flash drivers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This imports the driver sources provided by Socionext for the FIP006
SPI NOR flash device found on SynQuacer SoCs. It has been slightly
tweaked to bring it up to date with the changes made on the EDK2 side
since it was forked.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Pipat Methavanitpong <methavanitpong.pipat@socionext.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add the platform glue for the NOR flash driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add a device tree description of the SynQuacer SoC, and expose it for
the SynQuacerEvalBoard platforms. This includes the menu option in the
UEFI boot menu to switch between ACPI and DT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The SynQuacer SOC has two separate PCIe RCs, which means there is
no single value for the translation offset between I/O port accesses
and MMIO accesses. So add a special implementation of EFI_CPU_IO2_PROTOCOL
that takes the two disjoint I/O windows into account.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Implement the glue library that exposes the PCIe root complexes to
the generic PCI host bridge driver. Since that driver is the first
one to access the PCI config space, put the low level init code for
the RCs into this library's constructor.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Having two distinct root complexes is not supported by the standard
set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one
of the latter specifically for this platform (and forget about the
others).
This also allows us to implement the Synopsys Designware PCIe specific
workaround for PCI config space accesses to devices 1 and up on bus 0.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
code provided by Socionext. It can boot into the UiApp menu screen
or the UEFI Shell, but lacks support for any peripherals.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Implement MemoryInitPeiLib based on the newly added DramInfo
PPI, which retrieves the DRAM information from lower level
firmware.
Note that the firmware volumes in SPI NOR are mapped with
different attributes: the FV containing the PEI modules that
may execute in place is mapped as uncached memory, given that
it requires executable permissions. The FV containing the
compressed DXE modules is mapped with device attributes for
performance (!), and copied into DRAM by the platform PEIM
once permanent memory is installed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This implements a driver that will take care of platform specific
initialization, such as declaring non-discoverable devices, and
installing the device tree blob as a configuration table.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Create a specialized PlatformPeiLib implementation that invokes the
platform specific firmware interface (currently, just a data structure
left in SRAM) to set the ARM standard PcdSystemMemoryBase|Size PCDs,
and expose the information via a newly added DramInfo PPI.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This adds the NetSecDxe driver provided by Socionext, but reworked
extensively to improve compliance with the SimpleNetworkProtocol API,
and to avoid uncached allocations for streaming DMA.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add a package .DEC description for SynQuacer with an [Includes]
section, and add header files containing descriptions of the
platform's memory map and PCIe configuration. No code yet.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Hitherto mechanism of fixing SPI flash model in the PCDs,
occured to be very inefficient and problematic. Enable
dynamic detection by reworking MvSpiFlashReadId() command,
which now uses newly added NorFlashInfoLib, that helps to
obtain description of the JEDEC compliant devices.
This patch updates the MvSpiFlashProtocol ReadId() protocol
callback on both producer's (MvFlashDxe) and consumers' sides
(FirmwareUpdate and SpiTool applications). Because all
information about detected SPI NOR flash is now stored in
the obtained NorFlashInfo structure fields, use them instead
of the PCDs.
Enable compilation of the NorFlashInfoLib and update
PortingGuide documentation accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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When switching to generic PSCI reset library, obsolete parts
of previous custom reset library (PCDs, documentation) remained.
Remove them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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In preparation of adding capsule support to the AMD Styx aka Seattle
based platforms, implement a PlatformFlashAccessLib instance that
invokes the ISCP to update the FV containing our UEFI image.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The StyxFlashUefi application was not migrated correctly from
OpenPlatformPkg to edk2-platforms. It will be superseded shortly
by capsule update support, but let's put it back into a working
state before we remove it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The IORT spec has been updated to include more specific defines for the
MMU-401, which supports more page sizes than the generic SMMU v1. Note
that this requires an OS that understands these new definitions.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch removes tabs and wrong line endings in the file, maiking
it acceptable to the PatchCheck.py script.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Hitherto PHY handling in Pp2Dxe was not flexible. It allowed for using
only single MDIO controller, which may not be true on Armada 80x0 SoCs.
For this purpose introduce the MDIO description, using the new structures
and template in MvHwDescLib. This change enables addition of multiple
CP110 hardware blocks with MDIO controllers.
This change required different PHY handling and obtaining data over
desired MDIO bus. Now given Pp2 port is matched with the PHY via
its index in gMarvellTokenSpaceGuid.PcdPhyDeviceIds. The PHY itself
is mapped to the MDIO controller, using
gMarvellTokenSpaceGuid.PcdPhy2MdioController. Also obtaining
SMI addresses was moved to the PHY initialization routine.
All above allow for much cleaner and logical PHY description
in the .dsc file, which now uses macros for connection type
and speed.
Update PortingGuide documentation accordingly and Armada 70x0 DB
NIC/PHY description.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch introduces UTMI description, using the new structures
and template in MvHwDescLib. This change enables more flexible
addition of multiple CP with UTMI PHY's and also significantly
reduces amount of used PCD's for that purpose. Update PortingGuide
documentation accordingly.
This patch replaces string-based description of Utmi on
Armada 70x0 DB with new, reduced format, which uses macros
in Armada.dsc.inc file for better readability.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch introduces I2c description, using the new structures
and template in MvHwDescLib. This change enables more flexible
addition of multiple I2c controllers and also allows for
removal of string PCD parsing. Update Armada 70x0 DB description
and PortingGuide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Simplify obtaining lane data, using arrays with direct enum values,
rather than strings. This is another step to completely remove
ParsePcdLib.
This patch replaces string-based description of ComPhy lanes
on Armada 70x0 DB with the enum values of type and speed -
for that purpose new [Defines] section was added to Armada.dsc.inc
file in order to increase readability.
PortingGuide is updated accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Although, hitherto support allowed for using configurable EraseSize,
the erase command was fixed to CMD_ERASE_64K. Also it was
assumed that EraseSize equals SectorSize, which is not true
for some flash devices. Fix both issues by adding new PCD
(gMarvellTokenSpaceGuid.PcdSpiFlashPageSize) and using
this parameter properly in MvSpiFlashUpdate routine instead
of the EraseSize. Also erase command is adjusted to the settings.
Update PortingGuide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Until now transfer SCLK mode and CS were fixed, when using
shell 'sf' command. This patch enables their configuration.
Update porting guide accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This patch introduces following improvements to the PortingGuide
* Replace split documentation with single file
* Update paths to new directory structure in edk2-platforms
* Align format to Doxygen constraints
Moreover the PortingGuide and remaining Drivers' documentation
is moved to the new location under Silicon/Marvell, where in future
all other bits of the support will be moved.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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When building with a somewhat recent toolchain (GCC 6.3), the D02
platform fails due to (the implicit) -Werror=misleading-indentation.
Cc: Heyi Guo <heyi.guo@linaro.org>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Assign valid value to AddressTranslationOffset to support
address translation between domains of CPU and PCIe, which
is need by GOP to enable frame buffer.
This patch fix the bug:
Kernel (4.12, without the vga driver) boot hang with kernel panic
while kernel accesses UEFI GOP frame buffer.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Yan Zhang <zhangyan81@huawei.com>
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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1. Because Hi161x chip doesn't support "ARI Forwarding Enable"
function, BIOS will enumerate 32 same devices (Device Number 0~31)
when a Non-ARI capable device attached in the RP. Hi161x chip will
not fix it, need BIOS patch.
2. Just enlarge iatu for those root port with ARI capable device
attached, Non-ARI capable device's RP, keep iatu limitation.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason zhang <zhangjinsong2@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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1. Disable I2C0 device avoiding access conflict in OS, for it is used
by UEFI to access DS3231 RTC chip and provide time services;
2. Modify _HID of I2C2 for matching the string in OS driver;
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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There is no interface from SAS0 or SAS2 controller on D05,
so SAS0 and SAS2 can't be used.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The PerTuning function is not stable, it will cause the
LSI SAS 3008/3108 crash, disable this function first.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chenhui Sun <chenhui.sun@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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On D05 PCIe now, 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses are
0x20000000 and 0x30000000 based. These addresses overlap with the DDR
memory range 0-1G. In this situation, on the inbound direction, our pcie
will drop the DDR address access that are located in the pci range window
and lead to a dataflow error.
Modify 2p NA PCIe2 and 2p NB PCIe0's pci domain addresses to 0x40000000
and decrease PciRegion Size accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Io BAR should be based IoBase and Mem BAR should be based PciRegionBase.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The drivers build from separate sources, their GUID should
be different.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Remove the shared ArmDmaLib resolution from the shared .dsc include
file: it will be removed soon from upstream EDK2. Instead, replace
it with an explicit NonCoherentDmaLib resolution for each driver that
depends on DmaLib. This makes it more obvious which peripherals are
non cache coherent, and forces derived platforms to choose a DmaLib
resolution explicitly for newly added drivers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Replace the open coded PCI 'emulation' with a simple call into
the NonDiscoverable device registration library, and fix up all
platform .DSCs/FDFs accordingly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This driver does not actually use UncachedMemoryAllocationLib anymore,
so remove the bogus reference.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This is a continuation of the work carried out by Leif Lindholm to
implement a driver for the ChaosKey USB device. This driver uses the
UEFI driver model, which is a slightly awkward fit, due to the fact
that a UEFI implementation may legally only instantiate those protocols
that are needed to access the device path that the active Boot####
options refers to.
However, it is expected that UEFI implementations typically instantiate
all USB I/O protocols and connect them as well, as those are required
for a USB keyboard to be able to control the boot sequence. This should
result in this driver being connected and given the opportunity to
produce the EFI_RNG_PROTOCOL.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The previous implementation used only the lower bits for both the first
and second SATA controller, when the upper bits should have been used for
the second SATA controller.
Also ASSERT that SataChPerSerdes is 2, because the even/odd logic doesn't
work if it's not.
Signed-off-by: Alan Ott <alan@softiron.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Extra bits are needed to accomodate all 14 SATA ports
Signed-off-by: Alan Ott <alan@softiron.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
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Common files for AMD Overdrive, SoftIron Overdrive 1000
and LeMaker Cello, as well as actual platform support.
Imported from commit efd798c1eb of
https://git.linaro.org/uefi/OpenPlatformPkg.git
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org>
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