summaryrefslogtreecommitdiff
path: root/UefiCpuPkg/Include
AgeCommit message (Collapse)Author
2016-03-14UefiCpuPkg/Include: Add Pentium 4 MSR include fileMichael Kinney
Add Pentium 4 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit f4d9afde4c5b173ba7e143d50f1489bb94c5b80b)
2016-03-14UefiCpuPkg/Include: Add Xeon Phi MSR include fileMichael Kinney
Add Xeon Phi MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 3adf6316608d7701757f05f87fe855e39e2245ef)
2016-03-14UefiCpuPkg/Include: Add Skylake MSR include fileMichael Kinney
Add Skylake MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 6b55a245f133d045af4263b093278c2026196f21)
2016-03-14UefiCpuPkg/Include: Add Xeon Processor D MSR include fileMichael Kinney
Add Xeon Processor D MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 54307cea18916474edf3080e3102ca8df3c0fa33)
2016-03-14UefiCpuPkg/Include: Add Broadwell MSR include fileMichael Kinney
Add Broadwell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit d57201c0a3f201c75d295fab9e1f1110dd09256f)
2016-03-14UefiCpuPkg/Include: Add Haswell-E MSR include fileMichael Kinney
Add Haswell-E MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit c67b579cd6169d8293376fd84de4e9596d3ddd1b)
2016-03-14UefiCpuPkg/Include: Add Haswell MSR include fileMichael Kinney
Add Haswell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 7ae88a6295edfd45793097783b8a057519798328)
2016-03-14UefiCpuPkg/Include: Add Ivy Bridge MSR include fileMichael Kinney
Add Ivy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 84ada87c6b1f40a5f24af8fb9acb2d032d33674c)
2016-03-14UefiCpuPkg/Include: Add Sandy Bridge MSR include fileMichael Kinney
Add Sandy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit dc5d621c60f29cedf382f7ae4c91cf268aaa7176)
2016-03-14UefiCpuPkg/Include: Add Xeon E7 MSR include fileMichael Kinney
Add Xeon E7 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit ebb74e4a3c4cd159cdd2253317e63b84c08ef050)
2016-03-14UefiCpuPkg/Include: Add Xeon 5600 MSR include fileMichael Kinney
Add Xeon 5600 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit c5d7b07abb73e5671d8db7c853f698340481a08e)
2016-03-14UefiCpuPkg/Include: Add Nehalem MSR include fileMichael Kinney
Add Nehalem MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit bd946618a078b0479ae13b55d1209f5618980818)
2016-03-14UefiCpuPkg/Include: Add Silvermont MSR include fileMichael Kinney
Add Silvermont MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 053a6ae991b590a03f6f31ae4833f79feb260220)
2016-03-14UefiCpuPkg/Include: Add Atom MSR include fileMichael Kinney
Add Atom MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit a646000f9b2aa608938a231bf1cc64e17648c521)
2016-03-14UefiCpuPkg/Include: Add Core 2 MSR include fileMichael Kinney
Add Core 2 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 63f3a74dd91c50b5c92158ccc7f75fee75f38421)
2016-03-14UefiCpuPkg/Include: Add Architectural MSR include fileMichael Kinney
Add Architectural MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 04c980a6305c7ae61fc4649ffbf8333e5cb7f188)
2016-02-26UefiCpuPkg/Cpuid.h: Add CPUID leaf/sub-leaf defines and structuresMichael Kinney
Add CPUID leaf and sub-leaf indexes and structures as described by Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, December 2015, CPUID instruction. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> (cherry picked from commit 57d16ba1e7593e4fabc2b483ed5ac53cbfd5d9c7)
2016-02-25UefiCpuPkg/PiSmmCpu: Add 2 APIs in SmmCpuFeaturesLib.Yao, Jiewen
SmmCpuFeaturesCompleteSmmReadyToLock() is a hook point to allow CPU specific code to do more registers setting after the gEfiSmmReadyToLockProtocolGuid notification is completely processed. SmmCpuFeaturesAllocatePageTableMemory() is an API to allow CPU to allocate a specific region for storing page tables. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: "Yao, Jiewen" <jiewen.yao@intel.com> Reviewed-by: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Cc: "Kinney, Michael D" <michael.d.kinney@intel.com> Cc: "Laszlo Ersek" <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18979 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit e3840072cd932fc1c9fc48510866534297a58dd2)
2016-02-24UefiCpuPkg/Include: Expand description of AcpiCpuData.h structuresMichael Kinney
Provide a more detailed description of each field of the ACPI_CPU_DATA and CPU_REGISTER_TABLE structures. Cc: Laszlo Ersek <lersek@redhat.com> Cc: "Yao, Jiewen" <jiewen.yao@intel.com> Cc: "Fan, Jeff" <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Laszlo Ersek <lersek@redhat.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18950 6f19259b-4bc3-4df7-8a09-765794883524 (cherry picked from commit af381fda9b63f548a1b9f71bac3d4721f1fd8db4)
2015-12-18UefiCpuPkg/CpuMpPei: Add GetApLoopMode() to get AP loop modeJeff Fan
Add GetApLoopMode() that will get PCD PcdCpuApLoopMode firstly. If it is ApInMwaitLoop, we will check if MONITOR/MWAIT feature supported by CPUID. If MONITOR/MWAIT feature is not supported, force AP loop mode to ApInHltLoop. GetApLoopMode() also return the largest line size required. (Sync patch r19343 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19360 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Add MtrrSetMemoryAttributeInMtrrSettings()Michael Kinney
Add new API MtrrSetMemoryAttributeInMtrrSettings() in MtrrLib. Platform could use this API to set MTRR setting into local MTRR settings buffer instead of MTRRs. At last, platform could use MtrrSetAllMtrrs() to set the MTRR settings into MTRRs totally. It could improve MTRRs programming performance obviously, specially when platform is going to program a set of MTRRs. (Sync patch r19162 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19206 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Fix some typo and clean up code formatMichael Kinney
Fixed some typo. Removed some trailing spaces and TAB key. Clean up code format. (Sync patch r19152 from main trunk.) Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19196 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib: Add PCD PcdCpuNumberOfReservedVariableMtrrsJeff Fan
Current MtrrLib reserves 2 variable MTRRs for some legacy OS boot (CSM boots) may require some MTRRs to be reserved for OS use. But UEFI OS boot will not use MTRRs. Per Scott's suggestion in link: http://article.gmane.org/gmane.comp.bios.edk2.devel/4099 Add one PCD PcdCpuNumberOfReservedVariableMtrrs to specify the number of variable MTRRs reserved for OS use. Setting its default value to 2 is for back-compatibility. (Sync patch r19151 from main trunk.) Cc: Scott Duplichan <scott@notabs.org> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Suggested-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@19195 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17UefiCpuPkg: LocalApicLib: Add API to set SoftwareEnable bitMichael Kinney
The LocalApicLib does not provide a function to manage the state of the Local APIC SoftwareEnable bit in the Spurious Vector register. There are cases where this bit needs to be managed without side effects to. other Local APIC registers. One use case is in the DebugAgent in the SourceLevelDebugPkg. (Sync patch r18711 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18848 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17UefiCpuPkg: Add CPU Hot Plug Data include fileMichael Kinney
Add CpuHotPlugData.h that defines a data structure that is shared between modules and is required for to support hot plug CPUs. (Sync patch r18643 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18838 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17UefiCpuPkg: Add ACPI CPU Data include fileMichael Kinney
Add AcpuCpuData.h that defines a data structure that is shared between modules and is required for ACPI S3 support. APState field removed between V1 and V2 patch. (Sync patch r18642 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18837 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17UefiCpuPkg: Add SMRAM Save State include fileMichael Kinney
Add SmramSaveStateMap.h file that defines the 32-bit and 64-bit CPU SMRAM Save State Map. (Sync patch r18641 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18836 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17UefiCpuPkg: Add SMM CPU Service ProtocolMichael Kinney
Add definition of the SMM CPU Service Protocol that is produced by the PiSmmCpuDxeSmm module. (Sync patch r18640 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18835 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17UefiCpuPkg: Add SmmCpuPlatformHookLibMichael Kinney
Add SmmCpuPlatformHookLib that provides platform specific functions that are used to initialize SMM and process SMIs. A Null instance of this library is provided that should work for most platforms. (Sync patch r18639 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18834 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17UefiCpuPkg: Add SmmCpuFeaturesLibMichael Kinney
Add SmmCpuFeaturesLib that provides CPU specific functions that are used to initialize SMM and process SMIs. A functional implementation of this library class is provided that is based on the Intel(R) 64 and IA-32 Architectures Software Developer's Manual (Sync patch r18638 from main trunk.) [jeff.fan@intel.com: Fix code style issues reported by ECC] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18833 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17UefiCpuPkg: Add PlatformSecLibMichael Kinney
Add PlatformSecLib class and PlatformSecLibNull instance that is used by the SecCore. PlatformSecLibNull should not be used in a platform build. Instead, it should be used as a template for implementing a platform specific instance of the PlatformSecLib library class. (Sync patch r18635 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18830 6f19259b-4bc3-4df7-8a09-765794883524
2015-11-17UefiCpuPkg: Add Cpuid.h include files for CPUID related definesMichael Kinney
Move CPUID related defines from LocalApic.h to Cpuid.h Update LocalApicLib instances to include Cpuid.h Update CpuMpPei module to include Cpuid.h (Sync patch r18633 from main trunk.) Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/branches/UDK2015@18828 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-15UefiCpuPkg: Add some CPUID definitionsJeff Fan
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18001 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-111. Save/restore ICR high 32bit value and check Delivery Status before ↵Jeff Fan
sending IPI. It could be fix the interrupted issue between ICR high/low writes by SMI handler. 2. Save/restore CPU Interrupt state around sending IPI. It could avoid sending IPI be interrupted by CPU interrupt handler. 3. Add note for SetApicMode() API that must not be called from an interrupt handler or SMI handler. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com> Reviewed-by: Mudusuru, Giri <giri.p.mudusuru@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15652 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-161. Read 32bit CPU Init APIC ID from CPUID leaf B in XAPIC mode.Jeff Fan
2. Read CPU APIC ID from CPUID leaf B in case CPU Init APIC ID is larger 255 in XAPIC mode. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14674 6f19259b-4bc3-4df7-8a09-765794883524
2012-08-231. Added SetLocalApicBaseAdress() and GetLocalApicBaseAddress() APIs in ↵vanjeff
Local APIC library. 2. Updated Local APIC library instances to get Local APIC base Address by invoking GetLocalApicBaseAddress() instead of by PCD PcdCpuLocalApicBaseAddress. Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Kinney Michael D <michael.d.kinney@intel.com> Reviewed-by: Rui Sun <rui.sun@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13668 6f19259b-4bc3-4df7-8a09-765794883524
2011-10-281. Introduce the API MtrrGetDefaultMemoryType () in Mtrr Library.vanjeff
2. Invoke MtrrGetDefaultMemoryType() to get the default memory type instead of the hard code value in module. 3. Add go though for UC attributes. Signed-off-by: vanjeff Reviewed-by: rsun3 git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12587 6f19259b-4bc3-4df7-8a09-765794883524
2011-09-02Add generic HPET Timer DXE Driver and support librariesmdkinney
Signed-off-by: mdkinney Reviewed-by: li-elvin git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12259 6f19259b-4bc3-4df7-8a09-765794883524
2010-10-28Fix build break when doing 32-bit build with some certain C compiler option ↵rsun3
combinations. Use the library functions for shift operations in BaseLib for a 64-bit integer where the code is shared for 32-bit and 64-bit. Defining bitfields in structures with > 32 bits will cause these types of issues on IA32 builds. So the largest bitfield should be type UINT32 with a max size of :32. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10983 6f19259b-4bc3-4df7-8a09-765794883524
2010-08-27Add DisableLvtInterrupts() for the Local APIC library class.rsun3
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10827 6f19259b-4bc3-4df7-8a09-765794883524
2010-08-26Improve Local APIC library class. Add new library APIs: GetApicVersion(), ↵rsun3
SendFixedIpi(), SendFixedIpiAllExcludingSelf(), GetApicTimerState(). Remove GetApicTimerDivisor (), its functionality can be covered by GetApicTimerState(). git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10824 6f19259b-4bc3-4df7-8a09-765794883524
2010-08-23Add Local APIC Library class defining APIs for common Local APIC operations. ↵rsun3
Add two Local APIC library instances, one is for xAPIC mode only, the other is for x2APIC capable processors which have xAPIC and x2APIC modes. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10814 6f19259b-4bc3-4df7-8a09-765794883524
2010-07-13Code refinement.xli24
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10647 6f19259b-4bc3-4df7-8a09-765794883524
2010-04-24Update the copyright notice formathhtian
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10429 6f19259b-4bc3-4df7-8a09-765794883524
2010-04-16Fixed GCC 4.4 build issues due to EFIAPI not being used when required.geekboy15a
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10380 6f19259b-4bc3-4df7-8a09-765794883524
2010-03-10Add Checking for MTRR existence.xli24
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10223 6f19259b-4bc3-4df7-8a09-765794883524
2010-02-05Revert incompatible change:jyao1
1) No API change from old version. 2) Change MACRO: #define MTRR_NUMBER_OF_VARIABLE_MTRR 32 // the semantics are changed from NUMBER to MAX_NUMBER. #define FIRMWARE_VARIABLE_MTRR_NUMBER 6 // wrong and deprecated #define MTRR_LIB_IA32_VARIABLE_MTRR_END 0x20F // wrong and deprecated #define RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER 2 // add new one. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9941 6f19259b-4bc3-4df7-8a09-765794883524
2010-02-05Original MTRR lib hardcode VARIABLE_MTRR as 8. But it is 7 in Core2 if SMRR ↵jyao1
enabled, and 10 in latest Corei7. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9935 6f19259b-4bc3-4df7-8a09-765794883524
2010-01-28Remove unused structuremdkinney
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9853 6f19259b-4bc3-4df7-8a09-765794883524
2009-11-25Introduce UefiCpuLib library class in UefiCpuPkg and add one instance of ↵qhuang8
BaseUefiCpuLib. The major purpose of this library class / instance is to provide some routines that are generic for IA32 family CPU git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9480 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:15:44 +0000