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2017-03-28UefiCpuPkg: Add new PCDs PROMPT/HELP string in UNI fileJeff Fan
Correct PCD declaration comments and add new PCDs in UNI file. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22UefiCpuPkg: Add CPU Features PEI/DXE driversJeff Fan
They will consume Register CPU Features library to detect and initialize CPU features. CpuFeaturesPei driver is used to initialize CPU features in PEI phase. CpuFeaturesDxe driver is used to initialize CPU features in DXE phase. Add PcdCpuFeaturesInitAfterSmmRelocation and PcdCpuFeaturesInitOnS3Resume that consumed by CpuFeaturesPei and CpuFeaturesDxe. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22UefiCpuPkg: Add NULL CPU Common Features Library instanceJeff Fan
This NULL CPU common Features Library instance will register some CPU features defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR). Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL CPU Common Features Library instance. v2: 1. Using MSR_IA32_EFER to enable/disable NX feature instead of using MSR_IA32_MISC_ENABLE. 2. Fix bug that SMX and VMX feature is swapped. v3: 1. Add AesniGetConfigData() to get current register state. v5: Move MSR reading from AesniGetConfigData() to AesniSupport(). Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22UefiCpuPkg/Include/Library: Add Register CPU Features LibraryJeff Fan
Register CPU Features Library is used to register/manage/program CPU features. NULL CPU features library instance could consume it register CPU features functions. CPU Feature module could consume this library to detect/analysis/program CPU features on BSP/APs. v4: Fix GCC build issue. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuidJeff Fan
GUID gEdkiiCpuFeaturesInitDoneGuid is used to indicate if CPU features have been initialized. On PEI phase, one gEdkiiCpuFeaturesInitDoneGuid PPI will be installed after CPU features initialized. On DXE phase, one gEdkiiCpuFeaturesInitDoneGuid Protocol will be installed after CPU features initialized. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuidJeff Fan
GUID gEdkiiCpuFeaturesSetDoneGuid is used to indicate if CPU feature related setting are set finished. For example, PCD PcdCpuFeaturesUserConfiguration. On PEI phase, one gEdkiiCpuFeaturesSetDoneGuid PPI will be installed after platform set CPU feature setting. On DXE phase, one gEdkiiCpuFeaturesSetDoneGuid Protocol will be installed after platform set CPU feature setting. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2017-03-22UefiCpuPkg/UefiCpuPkg.dec: Add a set of CPU features PCDsJeff Fan
PcdCpuFeaturesSupport supports PcdsFixedAtBuild/PcdsPatchableInModule types and used to add/remove CPU feature from firmware during build time. PcdCpuFeaturesUserConfiguration supports all PCD types and used to configurate CPU features by platforms. PcdCpuFeaturesCapability supports PcdsDynamic PCD and used to indicate the CPU features capability on processors. PcdCpuFeaturesSetting supports PcdsDynamic PCD and used to indicate the current CPU features setting on processors. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-19UefiCpuPkg: Add STM GUIDs, Protocols, and PCDsMichael Kinney
* Add GUIDed HOB that described MSEG region in SMRAM * Add SM Monitor Init Protocol * Add PCD to configure size of SMM exception stack * Add PCD to configure MSEG region size if it is not described by the gMsegSmramGuid GUIDed HOB. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-22UefiCpuPkg/PiSmmCpuDxeSmm: dynamic PcdCpuSmmApSyncTimeout, PcdCpuSmmSyncModeLaszlo Ersek
Move the declaration of these PCDs from the [PcdsFixedAtBuild, PcdsPatchableInModule] section of "UefiCpuPkg/UefiCpuPkg.dec" to the [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] section. Their types, default values, and token values remain unchanged. Only UefiCpuPkg/PiSmmCpuDxeSmm consumes these PCDs, specifically on the call stack of its entry point function, and it turns them into static or dynamically allocated data in SMRAM: PiCpuSmmEntry() [PiSmmCpuDxeSmm.c] InitializeSmmTimer() [SyncTimer.c] PcdCpuSmmApSyncTimeout -> mTimeoutTicker InitializeMpServiceData() [MpService.c] InitializeMpSyncData() [MpService.c] PcdCpuSmmSyncMode -> mSmmMpSyncData->EffectiveSyncMode However, there's another call path to fetching "PcdCpuSmmSyncMode", namely SmmInitHandler() [PiSmmCpuDxeSmm.c] InitializeMpSyncData() [MpService.c] PcdCpuSmmSyncMode -> mSmmMpSyncData->EffectiveSyncMode and this path is exercised during S3 resume (as stated by the comment in SmmInitHandler() too, "Initialize private data during S3 resume"). While we can call the PCD protocol (via PcdLib) for fetching dynamic PCDs in the entry point function, we cannot do that at S3 resume. Therefore pre-fetch PcdCpuSmmSyncMode into a new global variable (which lives in SMRAM) in InitializeMpServiceData(), just before calling InitializeMpSyncData(). This way InitializeMpSyncData() can retrieve the stashed PCD value from SMRAM, regardless of the boot mode. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=230 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-11-17UefiCpuPkg/dec: Add PcdCpuSmmStaticPageTable.Jiewen Yao
If enabled, SMM will not use on-demand paging. SMM will build static page table for all memory. The page table size depend on 2 things: 1) The 1G paging capability. 2) The whole system memory/MMIO addressing capability. A) If the system only supports 2M paging, When the whole memory/MMIO is 32bit, we only need 1+1+4=6 pages for 4G. When the whole memory/MMIO is 39bit, we need 1+1+256 pages (~ 1M) When the whole memory/MMIO is 48bit, we need 1+256+256*256 pages (~ 257M) B) If the system supports 1G paging. When the whole memory/MMIO is 32bit, we only need 1+1+4=6 pages for 4G. (We still generate 2M page for maintenance consideration.) When the whole memory/MMIO is 39bit, we still need 6 pages. (We setup 1G paging for >1G.) When the whole memory/MMIO is 48bit, we need 1+256 pages (~ 1M). Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
2016-11-08UefiCpuPkg/UefiCpuPkg.dec: Add Microcode capsule related definition.Jiewen Yao
1) Add Microcode capsule related GUID. gMicrocodeFmpImageTypeIdGuid 2) Add Microcode capsule related library. MicrocodeFlashAccessLib Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-08-17UefiCpuPkg/MpInitLib: Add MP Initialize library class definitionJeff Fan
MP Initialize library provides basic functionalities to do APs initialization, to manage MP information and to wakeup APs to execute AP task. It could be consumed by CPU MP PEI or DXE drivers to provide CPU MP PPI/Protocol services. v4: 1. MpInitLibGetProcessorInfo(): Update HealthData type from UINT32 to EFI_HEALTH_FLAGS. Add #include <Ppi/SecPlatformInformation.h> 2. MpInitLibSwitchBSP(): Return EFI_DEVICE_ERROR instead of EFI_SUCCESS if the calling processor is an AP. 3. MpInitLibStartupThisAP(): Fix several incorrect references to "APs" to match PI spec. 4. MpInitLibSwitchBSP() and MpInitLibEnableDisableAP(): Fix incorrect description on ProcessorNumber. 5. Trim whitespace at end of line. v3: 1. Add whitespace after MpInitLibInitialize 2. Rename MpInitLibSwitchBsp to MpInitLibSwitchBSP to match PI spec Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com>
2016-06-06UefiCpuPkg: change PcdCpuSmmStackGuard default to TRUELaszlo Ersek
This Feature PCD causes PiSmmCpuDxe to catch SMM stack overflow at runtime, logging a clear error message, and entering a CPU dead loop. Compared to the chaotic and catastrophic consequences of the stack leaking into, and corrupting, the SMM page table, a stack guard that is enabled by default is vastly superior. We should not require sane platforms to explicitly opt in to this safeguard; instead, we should require platforms that prefer to live dangerously to opt out of it. Stack overflow in SMM might even give rise to security vulnerabilities. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/12864 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=1341733 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-03-04UefiCpuPkg: Add dynamic type for PcdCpuMaxLogicalProcessorNumberJeff Fan
Currently, PcdCpuMaxLogicalProcessorNumber only supports fixed type. There are some requests on this PCD to support dynamic type also. For example, platform may dynamically set this PCD to actual processor count to save memory or improve boot performance. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2015-12-18UefiCpuPkg: Add PCD PcdCpuApTargetCstateJeff Fan
This new PCD is used to specify the AP C-state value by MWAIT instruction. More deeper C-state means more longer latency time when APs exiting from MWAIT state. Platforms need to balance the performance and power saving to find the proper C-state for APs. Also, some processor may not ready for the deepest C-state at the beginning. Platform also could choose the proper chance to place AP into the deeper C-state by set this PCD before hand-off to OS. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19342 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg: Add PCD PcdCpuApLoopModeJeff Fan
This new PCD is used to specify the AP loop mode during POST phase. The value 1 means we will place AP in the Hlt-Loop state by HLT instruction. BSP need to send INIT-SIPI-SIPI to wake up APs. The value 2 means we will place AP in the deepest C-state by MWAIT instruction. BSP need to modify the monitor buffer by MONITOR instruction to wake up APs. The value 3 means we will place AP in the Run-loop state. APs are running. BSP need to write one semaphore to wake up APs. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19341 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/MtrrLib: Add PCD PcdCpuNumberOfReservedVariableMtrrsJeff Fan
Current MtrrLib reserves 2 variable MTRRs for some legacy OS boot (CSM boots) may require some MTRRs to be reserved for OS use. But UEFI OS boot will not use MTRRs. Per Scott's suggestion in link: http://article.gmane.org/gmane.comp.bios.edk2.devel/4099 Add one PCD PcdCpuNumberOfReservedVariableMtrrs to specify the number of variable MTRRs reserved for OS use. Setting its default value to 2 is for back-compatibility. Cc: Scott Duplichan <scott@notabs.org> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Suggested-by: Scott Duplichan <scott@notabs.org> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19151 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-19UefiCpuPkg: Add PiSmmCpuDxeSmm module no IA32/X64 filesMichael Kinney
Add module that initializes a CPU for the SMM environment and installs the first level SMI handler. This module along with the SMM IPL and SMM Core provide the services required for DXE_SMM_DRIVERS to register hardware and software SMI handlers. CPU specific features are abstracted through the SmmCpuFeaturesLib Platform specific features are abstracted through the SmmCpuPlatformHookLib Several PCDs are added to enable/disable features and configure settings for the PiSmmCpuDxeSmm module Changes between [PATCH v1] and [PATCH v2]: 1) Swap PTE init order for QEMU compatibility. Current PTE initialization algorithm works on HW but breaks QEMU emulator. Update the PTE initialization order to be compatible with both. 2) Update comment block that describes 32KB SMBASE alignment requirement to match contents of Intel(R) 64 and IA-32 Architectures Software Developer's Manual 3) Remove BUGBUG comment and call to ClearSmi() that is not required. SMI should be cleared by root SMI handler. [jeff.fan@intel.com: Fix code style issues reported by ECC] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> [pbonzini@redhat.com: InitPaging: prepare PT before filling in PDE] Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18645 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-19UefiCpuPkg: Update DEC/DSC files for new includes and librariesMichael Kinney
Add SmmCpuPlatformHookLib library class declaration Add SmmCpuFeaturesLib library class declaration Add gEfiSmmCpuServiceProtocolGuid protocol declaration Build SmmCpuPlatformHookLibNull library instance Build SmmCpuFeaturesLib library instance Changes between [PATCH v1] and [PATCH v2]: 1) Use module type specific CpuExceptionHandlerLib in DSC file instead of Null library instance Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18644 6f19259b-4bc3-4df7-8a09-765794883524
2015-10-19UefiCpuPkg: Add SecCore module and supporting library class and PCDMichael Kinney
Add declaration of PlatformSecLib library class to DEC file Add declaration of PcdPeiTemporaryRamStackSize PCD to DEC/UNI file Add build of PlatformSecLibNull to DSC file Add build of SecCore to DSC file Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18637 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-15UefiCpuPkg: Add microcode PCDsJeff Fan
Add PCDs PcdCpuMicrocodePatchAddress and PcdCpuMicrocodePatchRegionSize that are used to detect microcode patch from microcode region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18000 6f19259b-4bc3-4df7-8a09-765794883524
2015-07-15UefiCpuPkg: Add PcdCpuApInitTimeOutInMicroSecondsJeff Fan
This PCD is used to specify timeout value for BSP to detect all APs for the first time. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17996 6f19259b-4bc3-4df7-8a09-765794883524
2014-11-13UefiCpuPkg/CpuDxe: introduce two PCD valueChen Fan
introduce PCD value: PcdCpuMaxLogicalProcessorNumber and PcdCpuApStackSize, used for initialize APs stacks. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16350 6f19259b-4bc3-4df7-8a09-765794883524
2014-08-28UefiCpuPkg: INF/DEC file updates to EDK II packagesGao, Liming
4. PCD information in DEC file comment blocks are either incomplete or incorrect. This includes detailed description, @Prompt, @ValidRange, @ValidList, @Expression, and [Error.<TokenSpaceGuid>] validation error messages. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Gao, Liming <liming.gao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15935 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-10Introduce one PCD PcdCpuInitIpiDelayInMicroSeconds to specify the delay ↵Jeff Fan
value after sending out INIT IPI instead of hard code 10 MicroSeconds. Its default value is 10 millisecond per IA32 manual. Platform could customize this PCD value for performance requirement. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Kinney, Michael <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15650 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-22Fix CRLF formatTian, Hot
Signed-off-by: Tian, Hot <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15162 6f19259b-4bc3-4df7-8a09-765794883524
2014-01-10Update UefiCpuPkg version: 0.2->0.3Jeff Fan
Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Hot Tian <hot.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15079 6f19259b-4bc3-4df7-8a09-765794883524
2011-12-14Update package version for MdeModulePkg, UefiCpuPkg.rsun3
MdeModulePkg 0.91->0.92 UefiCpuPkg 0.1->0.2 Signed-off-by: rsun3 Reviewed-by: hhtian git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12851 6f19259b-4bc3-4df7-8a09-765794883524
2010-12-07Add MtrrLib and LocalApicLib declarations to the UefiCpuPkg DEC file.mdkinney
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11128 6f19259b-4bc3-4df7-8a09-765794883524
2010-08-23Add Local APIC Library class defining APIs for common Local APIC operations. ↵rsun3
Add two Local APIC library instances, one is for xAPIC mode only, the other is for x2APIC capable processors which have xAPIC and x2APIC modes. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10814 6f19259b-4bc3-4df7-8a09-765794883524
2010-05-13Fix minor format issue in file headerqhuang8
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10488 6f19259b-4bc3-4df7-8a09-765794883524
2010-04-24Update the copyright notice formathhtian
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10429 6f19259b-4bc3-4df7-8a09-765794883524
2010-01-27Minor clean up of DEC file.mdkinney
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9842 6f19259b-4bc3-4df7-8a09-765794883524
2009-11-25Introduce UefiCpuLib library class in UefiCpuPkg and add one instance of ↵qhuang8
BaseUefiCpuLib. The major purpose of this library class / instance is to provide some routines that are generic for IA32 family CPU git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@9480 6f19259b-4bc3-4df7-8a09-765794883524
2009-05-27Add MTRR library for IA32 & X64 processor architectures.jljusten
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8394 6f19259b-4bc3-4df7-8a09-765794883524
2009-02-23Add UefiCpuPkg.dsc and UefiCpuPkg.dec for UefiCpuPkg.jljusten
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@7609 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-12 02:36:44 +0000