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2016-05-24UefiCpuPkg/PiSmmCpuDxeSmm: Using MSRs semaphores in aligned bufferJeff Fan
Update MSRs semaphores to the ones in allocated aligned semaphores buffer. If MSRs semaphores is not enough, allocate one page more. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for MSRs semaphoresJeff Fan
Allocate MSRs semaphores in allocated aligned semaphores buffer. And add it into semaphores structure. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24UefiCpuPkg/PiSmmCpuDxeSmm: Using CPU semaphores in aligned bufferJeff Fan
Update each CPU semaphores to the ones in allocated aligned semaphores buffer. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for each CPU semaphoresJeff Fan
Allocate each CPU semaphores in allocated aligned semaphores buffer. And add it into semaphores structure. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24UefiCpuPkg/PiSmmCpuDxeSmm: Using global semaphores in aligned bufferJeff Fan
Update all global semaphores to the ones in allocated aligned semaphores buffer. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24UefiCpuPkg/PiSmmCpuDxeSmm: Move forward MP sync data initializationJeff Fan
Move MP sync data initialization in front of the place that initialize page table, because the page fault spin lock is allocated in InitializeMpSyncData() while it is initialized in SmmInitPageTable(). Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-24UefiCpuPkg/PiSmmCpuDxeSmm: Allocate buffer for global semaphoresJeff Fan
Get semaphores alignment/size requirement and allocate aligned buffer for all global spin lock and semaphores. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-19UefiCpuPkg/SmmCpuFeaturesLib: Add SMRR PhysBase/PhysMask fields checkMichael Kinney
SMRR range size and alignment should follow the rules like MTRR: a. The minimum range size is 4 KBytes and the base address of the range must be on at least a 4-KByte boundary. b. For ranges greater than 4 KBytes, each range must be of length 2^n and its base address must be aligned on a 2^n boundary, where n is a value equal to or greater than 12. The base-address alignment value cannot be less than its length. Thus, it could meet "Address_Within_Range AND PhysMask = PhysBase AND PhysMask". Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
2016-05-16UefiCpuPkg/PiSmmCpuDxeSmm: Use public MSR_IA32_MISC_ENABLE definitionJeff Fan
Use the MSR MSR_IA32_MISC_ENABLE definition defined in UefiCpuPkg/Include and remove the local definition. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-16UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Remove unnecessary BTS MSRsJeff Fan
BTS used DS save area by IA32_DS_AREA MSR to get invoker IP instead of the Last Branch Record Stack. So, removed the unnecessary BTS MSRs. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-05-16UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile: Fix BTS support check bugJeff Fan
SmmProfile feature depends on BTS feature to get the invoker IP (in SMM) from last branch record. If this feature is not supported, SmmProfile cannot get the invoker IP (in SMM). Per IA-32 Architectures Software Developer's Manual, BTS feature is detected by IA32_MISC_ENABLE. If BIT11 of IA32_MISC_ENABLE is set, BTS is not supported. But current implementation check BIT11 opposite. Also, BTS feature does not depends on PEBS feature if supported or not. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Shifflett, Joseph <joseph.shifflett@hpe.com> Contributed-under: TianoCore Contribution Agreement 1.0 Reported-by: Shifflett, Joseph <joseph.shifflett@hpe.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Shifflett, Joseph <joseph.shifflett@hpe.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-04-29UefiCpuPkg/MtrrLib: Remove the loop of calculating Fixed-MTRR MaskJeff Fan
Introduce the 32bit mask seeds to calculate Fixed-MTRR or&and mask values. It could avoid the loop operation and 64bit shift operations. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-29UefiCpuPkg/MtrrLib: Remove the loop of calculating byte offset in MSRJeff Fan
Calculate byte offset in MSR directly and removing the loop. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-29UefiCpuPkg/MtrrLib: Reduce the loop time to get fixed-MTRR MSR indexJeff Fan
Add input fixed-MTRR MSR index to be start MSR index to avoid finding fixed-MTRR MSR index from 0 at each time. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-04-11UefiCpuPkg: CpuIo2Dxe: optimize FIFO reads and writes of IO portsLaszlo Ersek
* Short description: The CpuIoServiceRead() and CpuIoServiceWrite() functions transfer data between memory and IO ports with individual Io(Read|Write)(8|16|32) function calls, each in an appropriately set up loop. On the Ia32 and X64 platforms however, FIFO reads and writes can be optimized, by coding them in assembly, and delegating the loop to the CPU, with the REP prefix. On KVM virtualization hosts, this difference has a huge performance impact: if the loop is open-coded, then the virtual machine traps to the hypervisor on every single UINT8 / UINT16 / UINT32 transfer, whereas with the REP prefix, KVM can transfer up to a page of data per VM trap. This is especially noticeable with IDE PIO transfers, where all the data are squeezed through IO ports. * Long description: The RootBridgeIoIoRW() function in PcAtChipsetPkg/PciHostBridgeDxe/PciRootBridgeIo.c used to have the exact same IO port acces optimization, dating back verbatim to commit 1fd376d9792: PcAtChipsetPkg/PciHostBridgeDxe: Improve KVM FIFO I/O read/write performance OvmfPkg cloned the "PcAtChipsetPkg/PciHostBridgeDxe" driver (for unrelated reasons), and inherited the optimization from PcAtChipsetPkg. The "PcAtChipsetPkg/PciHostBridgeDxe" driver was ultimately removed in commit 111d79db47: PcAtChipsetPkg/PciHostBridge: Remove PciHostBridge driver and OvmfPkg too was rebased to the new core Pci Host Bridge Driver, in commit 4014885ffd: OvmfPkg: switch to MdeModulePkg/Bus/Pci/PciHostBridgeDxe This caused the optimization to go lost. Namely, the RootBridgeIoIoRead() and RootBridgeIoIoWrite() functions in the new core Pci Host Bridge Driver delegate IO port accesses to EFI_CPU_IO2_PROTOCOL. And, in OvmfPkg (and likely most other Ia32 / X64 edk2 platforms), this protocol is provided by "UefiCpuPkg/CpuIo2Dxe", which lacks the optimization. Therefore, this patch ports the C source code logic from commit 1fd376d9792 (see above) to "UefiCpuPkg/CpuIo2Dxe", plus it ports the NASM-converted assembly helper functions from OvmfPkg commits 6026bf460037 and ace1d0517b65: OvmfPkg PciHostBridgeDxe: Convert Ia32/IoFifo.asm to NASM OvmfPkg PciHostBridgeDxe: Convert X64/IoFifo.asm to NASM In order to support the MSFT and INTEL toolchains as well, the *.asm files are ported from OvmfPkg as well, immediately from before the above conversion (that is, at 6026bf460037^). * Notes about the port: - The write and read branches from commit 1fd376d9792 are split to the separate functions CpuIoServiceWrite() and CpuIoServiceRead(). - The EfiPciWidthUintXX constants are replaced with EfiCpuIoWidthUintXX. - The cast expression "(UINTN) Address" is replaced with "(UINTN)Address" (i.e., no space), because that's how the receiving functions spell it as well. - The labels in the switch statements are unindented by one level, to match the edk2 coding style (and the rest of UefiCpuPkg) better. * The first signoff belongs to Jordan, because he authored all of 1fd376d9792, 6026bf460037 and ace1d0517b65. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Ref: https://www.redhat.com/archives/vfio-users/2016-April/msg00029.html Reported-by: Mark <kram321@gmail.com> Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/10424/focus=10432 Reported-by: Jordan Justen <jordan.l.justen@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Mark <kram321@gmail.com> Tested-by: Mark <kram321@gmail.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-04-11UefiCpuPkg/CpuMpPei: Fix potential AP mwait wakeup issueJeff Fan
If ApLoopMode is set to ApInMwaitLoop, AP will be placed into C-State by mwait instruction. BSP will wakeup AP by write start-up signal in monitor address. However, AP maybe waken by SMI/NMI/MCE and other condition. On this case, AP will check if BSP wants to wakeup itself really. If not, AP will continue to execute mwait to C-State. One potential issue: BSP may not recognize AP was wakeup from C-State by other event and BSP still writes start-up signal to wakeup AP. But AP does not aware it and still execute mwait instruction to C-State. So, AP cannot be wakeup on this case. This fix is let AP to clear start-up signal when it really is wakeup to execute AP function. And BSP will write start-up signal till AP clears it. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-03-30UefiCpuPkg/Cpuid.h: Display Intel SGX Resource Enumeration LeavesJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-30UefiCpuPkg/Cpuid.h: Add CPUID defines and structures for Intel SGXJeff Fan
Add Intel SGX Resource Enumeration Leaves as described by Section 37.7 in Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3D, December 2015. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-25UefiCpuPkg: CpuMpPei: remove set but unused variablesLaszlo Ersek
Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-25UefiCpuPkg: PiSmmCpuDxeSmm: remove set but unused variablesLaszlo Ersek
Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-25UefiCpuPkg/MtrrLib: remove unused but set variableArd Biesheuvel
Remove variable TempQWord that is declared, assigned but never referenced. This fixes a warning emitted by GCC when -Wunused-but-set-variable is in effect. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Jeff Fan <jeff.fan@intel.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add top level MSR include fileMichael Kinney
Add top level MSR include file that includes the Architecural MSR include file and all family specific MSR files from the Msr subdirectory Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR). Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium MSR include fileMichael Kinney
Add Pentium MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-20. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add P6 MSR include fileMichael Kinney
Add P6 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-19. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium M MSR include fileMichael Kinney
Add Pentium M MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-18. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Core Solo/Duo MSR include fileMichael Kinney
Add Core Solo/Duo MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-17. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Pentium 4 MSR include fileMichael Kinney
Add Pentium 4 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-16. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon Phi MSR include fileMichael Kinney
Add Xeon Phi MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-15. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Skylake MSR include fileMichael Kinney
Add Skylake MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-14. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon Processor D MSR include fileMichael Kinney
Add Xeon Processor D MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Broadwell MSR include fileMichael Kinney
Add Broadwell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell-E MSR include fileMichael Kinney
Add Haswell-E MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell MSR include fileMichael Kinney
Add Haswell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Ivy Bridge MSR include fileMichael Kinney
Add Ivy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Sandy Bridge MSR include fileMichael Kinney
Add Sandy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon E7 MSR include fileMichael Kinney
Add Xeon E7 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon 5600 MSR include fileMichael Kinney
Add Xeon 5600 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Nehalem MSR include fileMichael Kinney
Add Nehalem MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Silvermont MSR include fileMichael Kinney
Add Silvermont MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Atom MSR include fileMichael Kinney
Add Atom MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Core 2 MSR include fileMichael Kinney
Add Core 2 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Architectural MSR include fileMichael Kinney
Add Architectural MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-10UefiCpuPkg/Application/Cpuid: Remove unnecessary code checkJeff Fan
gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> UefiCpuPkg/Application/Cpuid: Remove unnecessary code check gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> UefiCpuPkg/Application/Cpuid: Remove unnecessary code check gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-10UefiCpuPkg/Application/Cpuid: Add check for gMaximumBasicFunctionJeff Fan
Add check for gMaximumBasicFunction in CpuidVersionInfo () back. Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-04UefiCpuPkg: Add dynamic type for PcdCpuMaxLogicalProcessorNumberJeff Fan
Currently, PcdCpuMaxLogicalProcessorNumber only supports fixed type. There are some requests on this PCD to support dynamic type also. For example, platform may dynamically set this PCD to actual processor count to save memory or improve boot performance. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-03-03UefiCpuPkg/Application/Cpuid: Change DisplayFamily/DisplayModel typeJeff Fan
Change DisplayFamily/DisplayModel type to UINT32 to avoid different size in bitwise operation. Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-03UefiCpuPkg/Application/Cpuid: Remove unnecessary code checkJeff Fan
gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-03UefiCpuPkg/CpuMpPei: Load microcode if found newer revisionJeff Fan
Current implementation only loads the latest revision if there is no microcode loaded. Per IA32 User Manual, we should load the newer revision by comparing the existing microcode loaded with the updating revision. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-02-27UefiCpuPkg/Cpuid: Fix GCC build errorHao Wu
define PRINT_BIT_FIELD(Variable, FieldName) \ Print (L"%5a%42a: %x\n", #Variable, #FieldName, \ ##Variable.Bits.##FieldName); The above definition in UefiCpuPkg/Application/Cpuid/Cpuid.c will cause GCC build error. Fix it with: define PRINT_BIT_FIELD(Variable, FieldName) \ Print (L"%5a%42a: %x\n", #Variable, #FieldName, \ Variable.Bits.FieldName); The '.' has its origin meaning as a member operator in the define statement. Thus, the token-pasting operator '##' is not necessary here. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-02-24UefiCpuPkg/Cpuid: Add UEFI CPUID applicationMichael Kinney
Add UEFI application to UefiCpuPkg to display all supported CPUID leafs and sub-leafs described by UefiCpuPkg/Include/Register/Cpuid.h that is based on information from Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, December 2015, CPUID instruction. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-03 06:27:51 +0000