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2016-03-13UefiCpuPkg/Include: Add Xeon Processor D MSR include fileMichael Kinney
Add Xeon Processor D MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Broadwell MSR include fileMichael Kinney
Add Broadwell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-12. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell-E MSR include fileMichael Kinney
Add Haswell-E MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-11. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Haswell MSR include fileMichael Kinney
Add Haswell MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-10. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Ivy Bridge MSR include fileMichael Kinney
Add Ivy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-9. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Sandy Bridge MSR include fileMichael Kinney
Add Sandy Bridge MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-8. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon E7 MSR include fileMichael Kinney
Add Xeon E7 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-7. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Xeon 5600 MSR include fileMichael Kinney
Add Xeon 5600 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Nehalem MSR include fileMichael Kinney
Add Nehalem MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-5. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Silvermont MSR include fileMichael Kinney
Add Silvermont MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-4. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Atom MSR include fileMichael Kinney
Add Atom MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-3. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Core 2 MSR include fileMichael Kinney
Add Core 2 MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-13UefiCpuPkg/Include: Add Architectural MSR include fileMichael Kinney
Add Architectural MSRs from: Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-03-10UefiCpuPkg/Application/Cpuid: Remove unnecessary code checkJeff Fan
gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> UefiCpuPkg/Application/Cpuid: Remove unnecessary code check gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> UefiCpuPkg/Application/Cpuid: Remove unnecessary code check gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-10UefiCpuPkg/Application/Cpuid: Add check for gMaximumBasicFunctionJeff Fan
Add check for gMaximumBasicFunction in CpuidVersionInfo () back. Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-04UefiCpuPkg: Add dynamic type for PcdCpuMaxLogicalProcessorNumberJeff Fan
Currently, PcdCpuMaxLogicalProcessorNumber only supports fixed type. There are some requests on this PCD to support dynamic type also. For example, platform may dynamically set this PCD to actual processor count to save memory or improve boot performance. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-03-03UefiCpuPkg/Application/Cpuid: Change DisplayFamily/DisplayModel typeJeff Fan
Change DisplayFamily/DisplayModel type to UINT32 to avoid different size in bitwise operation. Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-03UefiCpuPkg/Application/Cpuid: Remove unnecessary code checkJeff Fan
gMaximumBasicFunction is set to CPUID_SIGNATURE as below, so removed the compare code. UINT32 gMaximumBasicFunction = CPUID_SIGNATURE; Cc: Qiu Shumin <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-03-03UefiCpuPkg/CpuMpPei: Load microcode if found newer revisionJeff Fan
Current implementation only loads the latest revision if there is no microcode loaded. Per IA32 User Manual, we should load the newer revision by comparing the existing microcode loaded with the updating revision. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-02-27UefiCpuPkg/Cpuid: Fix GCC build errorHao Wu
define PRINT_BIT_FIELD(Variable, FieldName) \ Print (L"%5a%42a: %x\n", #Variable, #FieldName, \ ##Variable.Bits.##FieldName); The above definition in UefiCpuPkg/Application/Cpuid/Cpuid.c will cause GCC build error. Fix it with: define PRINT_BIT_FIELD(Variable, FieldName) \ Print (L"%5a%42a: %x\n", #Variable, #FieldName, \ Variable.Bits.FieldName); The '.' has its origin meaning as a member operator in the define statement. Thus, the token-pasting operator '##' is not necessary here. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-02-24UefiCpuPkg/Cpuid: Add UEFI CPUID applicationMichael Kinney
Add UEFI application to UefiCpuPkg to display all supported CPUID leafs and sub-leafs described by UefiCpuPkg/Include/Register/Cpuid.h that is based on information from Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, December 2015, CPUID instruction. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-02-24UefiCpuPkg/Cpuid.h: Add CPUID leaf/sub-leaf defines and structuresMichael Kinney
Add CPUID leaf and sub-leaf indexes and structures as described by Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, December 2015, CPUID instruction. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-02-22UefiCpuPkg/PiSmmCpuDxeSmm: Enable/Restore XD in SMMMichael Kinney
If XD is supported, then SMM enables it. The non-SMM execution environment can choose to enable or disable XD, so the state of XD must be detected in each SMI and be enabled/restored. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
2016-02-22UefiCpuPkg/PiSmmCpuDxeSmm: Add EFIAPI to CheckFeatureSupported()Michael Kinney
The function CheckFeatureSupported() is used as an EFI_AP_PROCEDURE in the MP Services Protocol service StartAllAPs(). Any function used as an EFI_AP_PROCEDURE must use EFIAPI calling convention. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-01-19UefiCpuPkg: Add NOOPT target in UefiCpuPkg.dscHao Wu
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19681 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-24UefiCpuPkg: Add the missing module uni for CpuS3DataDxeLiming Gao
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Liming Gao <liming.gao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19510 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-24UefiCpuPkg/PiSmmCpuDxeSmm: Initialize gSmst fields on S3 resumeMichael Kinney
Update S3 resume path to initialize the fields of gSmst before the gSmst fields are used to complete initialization in S3 resume. Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19504 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-24UefiCpuPkg/PiSmmCpuDxeSmm: Correct CPUID leaf used to detect SMM modeMichael Kinney
Use Bit 29 of CPUID leaf CPUID_EXTENDED_CPU_SIG (0x80000001) to determine the SMM save state mode. The previous version of this code used CPUID leaf CPUID_VERSION_INFO (0x00000001). Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19503 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-24UefiCpuPkg/PiSmmCpuDxeSmm: Fix failure when PcdCpuSmmDebug is TRUEMichael Kinney
If PcdCpuSmmDebug is set to TRUE, then the first time the function CpuSmmDebugEntry () is called during the first normal SMI, the registers DR6 or DR7 may be set to invalid values due to gSmst not being fully initialized yet. Instead, use gSmmCpuPrivate that is fully initialized for the first SMI to look up CpuSaveState for the currently executing CPU. Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19502 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Remove un-used AsmCliHltLoop()Jeff Fan
Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19347 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Wake up APs by proper methodJeff Fan
If ApLoopMode is ApInHltLoop, BSP will send INIT-SIPI-SIPI to wake up APs. If ApLoopMode is ApInMwaitLoop or ApInRunLoop, BSP will write one semaphore to wake up APs. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19346 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Place APs in proper loop mode after AP executionJeff Fan
After AP function is executed, we will place AP in proper loop mode. Because AP maybe waken up by SMI or other reasons. We need to read signature in monitor buffer to check if APs is waken up by BSP. If it is not waken up by BSP, we will continue to place them into proper loop mode. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19345 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Prepare for monitor bufferJeff Fan
Get AP loop mode to prepare for the monitor buffer required for ApInMwaitLoop and ApInRunLoop. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19344 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Add GetApLoopMode() to get AP loop modeJeff Fan
Add GetApLoopMode() that will get PCD PcdCpuApLoopMode firstly. If it is ApInMwaitLoop, we will check if MONITOR/MWAIT feature supported by CPUID. If MONITOR/MWAIT feature is not supported, force AP loop mode to ApInHltLoop. GetApLoopMode() also return the largest line size required. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19343 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg: Add PCD PcdCpuApTargetCstateJeff Fan
This new PCD is used to specify the AP C-state value by MWAIT instruction. More deeper C-state means more longer latency time when APs exiting from MWAIT state. Platforms need to balance the performance and power saving to find the proper C-state for APs. Also, some processor may not ready for the deepest C-state at the beginning. Platform also could choose the proper chance to place AP into the deeper C-state by set this PCD before hand-off to OS. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19342 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg: Add PCD PcdCpuApLoopModeJeff Fan
This new PCD is used to specify the AP loop mode during POST phase. The value 1 means we will place AP in the Hlt-Loop state by HLT instruction. BSP need to send INIT-SIPI-SIPI to wake up APs. The value 2 means we will place AP in the deepest C-state by MWAIT instruction. BSP need to modify the monitor buffer by MONITOR instruction to wake up APs. The value 3 means we will place AP in the Run-loop state. APs are running. BSP need to write one semaphore to wake up APs. Contributed-under: TianoCore Contribution Agreement 1.0 Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19341 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-18UefiCpuPkg/CpuMpPei: Fix pack(1) issue on x64 archJeff Fan
Packing alignment for MP_CPU_EXCHANGE_INFO should be 1. This should be typo when check-in CpuMpPei driver. IA32 arch MP_CPU_EXCHANGE_INFO is luckly pack(1). It leads CpuMpPei x64 version hung. Contributed-under: TianoCore Contribution Agreement 1.0 Reported-by: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Tested-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19340 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-15UefiCpuPkg: Convert all .uni files to utf-8Jordan Justen
To convert these files I ran: $ python3 BaseTools/Scripts/ConvertUni.py UefiCpuPkg Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19264 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-11UefiCpuPkg/UefiCpuPkg.uni: Fix one typoJeff Fan
'.' should be '_'. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Shumin Qiu <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19226 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/MtrrLib:Initialize local variables before use themJeff Fan
Cc: Shumin Qiu <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Shumin Qiu <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19183 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-10UefiCpuPkg/UefiCpuPkg.uni: Add PcdCpuNumberOfReservedVariableMtrrsJeff Fan
Cc: Shumin Qiu <shumin.qiu@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Shumin Qiu <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19182 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/CpuMpPei: Add missing point at function headerJeff Fan
Cc: Qiu Shumin <shumin.qiu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Qiu Shumin <shumin.qiu@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19165 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/MtrrLib: Add MtrrSetMemoryAttributeInMtrrSettings()Michael Kinney
Add new API MtrrSetMemoryAttributeInMtrrSettings() in MtrrLib. Platform could use this API to set MTRR setting into local MTRR settings buffer instead of MTRRs. At last, platform could use MtrrSetAllMtrrs() to set the MTRR settings into MTRRs totally. It could improve MTRRs programming performance obviously, specially when platform is going to program a set of MTRRs. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19162 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/MtrrLib: Add MtrrDebugPrintAllMtrrsWorker()Michael Kinney
MtrrDebugPrintAllMtrrsWorker() provides the capability to dump the MTRR setting from MTRRs or the input MTRR settings buffer. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19161 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/MtrrLib: Add worker functions to access MTRRs or variableMichael Kinney
Add worker functions that could access MTRRs or MTRR settings in input buffer. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19160 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/MtrrLib: Print MTRR settings when set fixed/variable MTRRsMichael Kinney
Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19159 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/MtrrLib: Reduce hardware init when program variable MTRRsMichael Kinney
When MtrrSetMemoryAttribute() programs variable MTRRs, it may disable/enable cache and disable/enable MTRRs several times. This updating tries to do operation in local variable and does the hardware initialization one time only. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19158 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/MtrrLib: Reduce hardware init when program fixed MTRRsMichael Kinney
When MtrrSetMemoryAttribute() programs fixed MTRRs, it may disable/enable cache and disable/enable MTRRs several times. This updating tries to do operation in local variable and does the hardware initialization one time only. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19157 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/MtrrLib: Add MtrrGetMemoryAttributeInVariableMtrrWorker ()Michael Kinney
Add function to shadow the content of variable MTRRs into an internal array: VariableMtrr. And used MtrrGetMemoryAttributeInVariableMtrrWorker() in other functions. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19156 6f19259b-4bc3-4df7-8a09-765794883524
2015-12-08UefiCpuPkg/MtrrLib: Make use of worker functions to get MTRRs countMichael Kinney
Try to make use of worker functions to get MTRRs count. It could avoid invoking IsMtrrSupported() for many times. Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19155 6f19259b-4bc3-4df7-8a09-765794883524
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-17 21:30:59 +0000